ADN8102 (Rev. C)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 36
Technical content
3.75 Gbps Quad Bidirectional
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2008–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Optimized for dc to 3.75 Gbps data Programmable input equalization Up to 22 dB boost at 1.875 GHz Compensates up to 30 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Programmable output pre-emphasis/de-emphasis Up to 12 dB boost at 1.875 GHz (3.75 Gbps) Compensates up to 15 meters of CX4 cable up to 3.75 Gbps Compensates up to 40 inches of FR4 up to 3.75 Gbps Flexible 1.8 V to 3.3 V core supply Per lane P/N pair inversion for routing ease Low power: 125 mW/channel up to 3.75 Gbps DC- or ac-coupled differential CML inputs Programmable CML output levels 50 Ω on-chip termination Loss-of-signal detection Temperature range operation: −40°C to +85°C Supports 8b10b, scrambled, or uncoded NRZ data I2C control interface 64-lead LFCSP (QFN) package
APPLICATIONS
HiGig™ InfiniBand® 1×, 2× Fibre Channel XAUI™ Gigabit Ethernet over backplane or cable CPRI™ 50 Ω cables FUNCTIONAL BLOCK DIAGRAM RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION PE2:1 2:1 CONTROL LOGIC ADN8102 EQ Ix_B[3:0] LOS_B LB Ox_A[3:0] ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB 07060-001 F igure 1. GENERAL DESCRIPTION The ADN8102 is a quad, bidirectional, CX4 cable/backplane equalizer with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 3.75 Gbps. The receive inputs provide programmable equalization to compensate for up to 30 meters of CX4 cable (24 AWG) or 40 inches of FR4, and programmable pre-emphasis to compensate for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4 at 3.75 Gbps. Each channel also provides programmable loss-of- signal detection and loopback capability for system testing and debugging. The ADN8102 is controlled through toggle pins, an I 2C® control interface that provides more flexible control, or a combination of both. Every channel implements an asynchronous path supporting dc to 3.75 Gbps NRZ data, fully independent of other channels. The ADN8102 has low latency and very low channel-to-channel skew. The main application for the ADN8102 is to support switching in chassis-to-chassis applications over CX4 or InfiniBand cables. The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP (QFN) package and operates from −40°C to +85°C.
Rev. C | Page 2 of 36 TABLE OF CONTENTS
REVISION HISTORY
8/2021—Rev. B to Rev. C 10/2010—Rev. A to Rev. B Changes to Power Supply/Supply Current Parameter, Table 1 ... 4 Added tRESET Parameter and Note 1, Table 2 and Figure 3; Added Table 7 and Advanced Equalization Settings Section ... 17 Deleted High Current Setting and Output Level Shift Added Applications Information Section and Output Deleted Transmission Lines Section and Soldering Guidelines Changes to Printed Circuit Board (PCB) Layout Guidelines Added Figure 45, Supply Sequencing Section, Thermal Paddle Added Stencil Design for the Thermal Paddle, Figure 47, and 8/2008—Rev. 0 to Rev. A 5/2008—Revision 0: Initial Version
Rev. C | Page 3 of 36 SPECIFICATIONS VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, 3.75 Gbps, PRBS 27 − 1, TA = 25°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate/Channel (NRZ) 3.75 Gbps Deterministic Jitter Data rate < 3.75 Gbps; BER = 1 × 10−12 33 ps p-p Random Jitter VCC = 1.8 V 1.5 ps rms Residual Deterministic Jitter With Input Equalization Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 0.20 UI Data rate < 3.25 Gbps; 0 meters to 30 meters CX4 0.19 UI Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 0.24 UI Data rate < 3.75 Gbps; 0 meters to 30 meters CX4 0.21 UI With Output Pre-Emphasis Data rate < 3.25 Gbps; 0 inches to 40 inches FR4 0.13 UI Data rate < 3.25 Gbps; 0 meters to 15 meters CX4 0.37 UI Data rate < 3.75 Gbps; 0 inches to 40 inches FR4 0.14 UI Data rate < 3.75 Gbps; 0 meters to 15 meters CX4 0.41 UI Output Rise/Fall Time 20% to 80% 75 ps Propagation Delay 1 ns Channel-to-Channel Skew 50 ps OUTPUT PRE-EMPHASIS Equalization Method 1-tap programmable pre-emphasis Maximum Boost 800 mV p-p output swing 6 dB 200 mV p-p output swing 12 dB Pre-Emphasis Tap Range Minimum 2 mA Maximum 12 mA INPUT EQUALIZATION Minimum Boost EQBY = 1 1.5 dB Maximum Boost Maximum boost occurs at 1.875 GHz 22 dB Number of Equalization Settings 8 Gain Step Size 2.5 dB INPUT CHARACTERISTICS Input Voltage Swing Differential, VICM1 = VCC − 0.6 V 300 2000 mV p-p Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.4 V p-p Single-ended absolute voltage level, VH maximum VCC + 0.5 V p-p Input Resistance Single-ended 45 50 55 Ω Input Return Loss Measured at 2.5 GHz 5 dB OUTPUT CHARACTERISTICS Output Voltage Swing DC, differential, PE = 0, default, VCC = 1.8 V 635 740 870 mV p-p DC, differential, PE = 0, default, VCC = 3.3 V 800 mV p-p DC, differential, PE = 0, minimum output level,2 VCC = 1.8 V 100 mV p-p DC, differential, PE = 0, minimum output level,2 VCC = 3.3 V 100 mV p-p DC, differential, PE = 0, maximum output level,2 VCC = 1.8 V 1300 mV p-p DC, differential, PE = 0, maximum output level,2 VCC = 3.3 V 1800 mV p-p
Rev. C | Page 4 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Output Voltage Range Single-ended absolute voltage level, TxHeadroom = 0; VL minimum VCC − 1.1 V Single-ended absolute voltage level, TxHeadroom = 0; VH maximum VCC + 0.6 V Single-ended absolute voltage level, TxHeadroom = 1; VL minimum VCC − 1.2 V Single-ended absolute voltage level, TxHeadroom = 1; VH maximum VCC + 0.6 V Output Current Minimum output current per channel 2 mA Maximum output current per channel, VCC = 1.8 V 21 mA Output Resistance Single-ended 43 50 57 Ω Output Return Loss Measured at 2.5 GHz 5 dB LOS CHARACTERISTICS Assert Level IN_A/IN_B LOS threshold = 0x0C 20 mV diff Deassert Level IN_A/IN_B LOS hysteresis = 0x0D 225 mV diff POWER SUPPLY Operating Range VCC VEE = 0 V 1.7 1.8 3.6 V DVCC VEE = 0 V, DVCC ≤ (VCC + 1.3 V) 3.0 3.3 3.6 V Supply Current ITTO VTTO = 1.8 V, all outputs enabled 63 69 mA ICC VCC = 1.8 V, all outputs enabled 460 565 mA LOGIC CHARACTERISTICS Input High, VIH DVCC = 3.3 V 2.5 V Input Low, VIL 1.0 V Output High, VOH 2.5 V Output Low, VOL 1.0 V THERMAL CHARACTERISTICS Operating Temperature Range −40 +85 °C θJA 22 °C/W 1 VICM is the input common-mode voltage. 2 Programmable via I2C.
Rev. C | Page 6 of 36 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VCC to VEE 3.7 V VTTI VCC + 0.6 V VTTO VCC + 0.6 V Internal Power Dissipation 4.26 W Differential Input Voltage 2.0 V Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range −65°C to +125°C Lead Temperature 300°C Junction Temperature 125°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
- EXPOSED PAD MUST BE CONNECTED TO VEE.
Figure 4. Pin Configuration Table 4. Pin Function Descriptions
1 RESET Control Reset Input, Active Low
2 LOS_A Digital I/O Port A Loss of Signal Status, Active Low
3 IN_A0 I/O High Speed Input Complement
4 IP_A0 I/O High Speed Input
5 VCC Power Positive Supply
6 IN_A1 I/O High Speed Input Complement
7 IP_A1 I/O High Speed Input
8 VTTI Power Input Termination Supply
9 IN_A2 I/O High Speed Input Complement
10 IP_A2 I/O High Speed Input
11 VEE Power Negative Supply
12 IN_A3 I/O High Speed Input Complement
13 IP_A3 I/O High Speed Input
14 DVCC Power Digital Power Supply
15 EQ_A1 Control Port A Input Equalization MSB
16 EQ_A0 Control Port A Input Equalization LSB
17 VEE Power Negative Supply
18 LB Control Loopback Control
19 ON_B0 I/O High Speed Output Complement
20 OP_B0 I/O High Speed Output
21 VCC Power Positive Supply
22 ON_B1 I/O High Speed Output Complement
23 OP_B1 I/O High Speed Output
24 VTTO Power Output Termination Supply
25 ON_B2 I/O High Speed Output Complement
26 OP_B2 I/O High Speed Output
27 VEE Power Negative Supply
Rev. C | Page 8 of 36 Pin No. Mnemonic Type Description
28 ON_B3 I/O High Speed Output Complement
29 OP_B3 I/O High Speed Output
30 ENB Control Port B Enable
31 PE_B1 Control Port B Output Pre-Emphasis MSB
32 PE_B0 Control Port B Output Pre-Emphasis LSB
33 EQ_B0 Control Port B Input Equalization LSB
34 EQ_B1 Control Port B Input Equalization MSB
35 IN_B3 I/O High Speed Input Complement
36 IP_B3 I/O High Speed Input
37 VEE Power Negative Supply
38 IN_B2 I/O High Speed Input Complement
39 IP_B2 I/O High Speed Input
40 VTTI Power Input Termination Supply
41 IN_B1 I/O High Speed Input Complement
42 IP_B1 I/O High Speed Input
43 VCC Power Positive Supply
44 IN_B0 I/O High Speed Input Complement
45 IP_B0 I/O High Speed Input
46 LOS_B Digital I/O Port B Loss of Signal Status, Active Low
47 SDA Control I2C Control Interface Data Input/Output
48 SCL Control I2C Control Interface Clock Input
49 ADDR0 Control I2C Control Interface Address LSB
50 ADDR1 Control I2C Control Interface Address MSB
51 ON_A3 I/O High Speed Output Complement
52 OP_A3 I/O High Speed Output
53 VEE Power Negative Supply
54 ON_A2 I/O High Speed Output Complement
55 OP_A2 I/O High Speed Output
56 VTTO Power Output Termination Supply
57 ON_A1 I/O High Speed Output Complement
58 OP_A1 I/O High Speed Output
59 VCC Power Positive Supply
60 ON_A0 I/O High Speed Output Complement
61 OP_A0 I/O High Speed Output
62 ENA Control Port A Enable
63 PE_A0 Control Port A Output Pre-Emphasis LSB
64 PE_A1 Control Port A Output Pre-Emphasis MSB
EP EPAD Power EPAD Must Be Connected to VEE
emphasis on both the line card and cable sides of the device. either typical backplane or typical cable losses. ac-coupled I/O configurations. (LOS) behavior, and output levels. pin. The user can override PE and EQ settings in mixed mode. the control pin inputs are ignored, except RESET . Figure 38. Simplified Functional Block Diagram Table 5. Control Interface Mode Register 0x0F 0x00 Control 7:2 Reserved Set to 0. interface mode 1:0 MODE[1:0] 00 = toggle pin control. Asynchronous control through toggle pins only. register-based control through the I2C serial interface. via register-based control through the I2C serial interface. 11 = serial control. Register-based control through the I2C serial interface.
equalizer that can be optimized for backplane or cable operation. crossovers in the receiver channel. Table 6. Common Input Voltage Levels Figure 39. Simplified Input Structure controlled via Register 0x80 and Register 0xA0, respectively. selects equalization control from the selected optimized map.
Table 8. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)
1 X = Don’t care
Table 9. Receive Configuration and Equalization Registers and compares this measurement with a defined threshold level. occurs within 100 µs of the event. threshold = 0x0C and IN_A/IN_B LOS hysteresis = 0x0D. until cleared by the user by overwriting the bits to 0.
- Set IN_A/IN_B LOS threshold to 0x0C for an assert voltage of 20 mV differential (40 mV p-p differential).
- Set IN_A/IN_B LOS hysteresis to 0x0D for a deassert voltage of 225 mV differential (450 mV p-p differential). LANE INVERSION The input P/N inversion is a feature intended to allow the user to implement the equivalent of a board-level crossover in a much smaller area and without additional via impedance discontinuities that degrade the high frequency integrity of the signal path. The P/N inversion is available on a per port basis and is controlled through the I 2C control interface. The P/N inversion is accom- plished by writing to the PNSW AP bit (Bit 6) of the IN_A/IN_B configuration register (see Table 9) with low representing a noninverting configuration and high representing an inverting configuration. Note that using this feature to account for signal inversions downstream of the receiver requires additional attention when switching connectivity.
Table 10. LOS Threshold and Hysteresis Control Registers Table 11. LOS Status Registers
Bit 0 and Bit 1 of the loopback control register (Register 0x02). each channel. Figure 40 illustrates the three loopback modes. Figure 40. Loopback Modes of Operation Table 12. Loopback Control Functionality
1 X X Board side loopback enabled
1 Refer to Table 5 for additional information regarding control mode settings. Table 13. Loopback Control Register
Figure 41. Simplified Output Structure control, covering the entire range of settings at lower resolution. it low selects pre-emphasis control from the optimized map. Table 14. Data Rate Select Table 15. Transmit Pre-Emphasis Boost and Overshoot vs. Setting Table 16. Output Configuration Registers
Table 17. Output Level Settings
Rev. C | Page 23 of 36 VSW-DC (mV) VSW-PE (mV) VDPP-DC (mV) VDPP-PE (mV) PE (dB) ITOT (mA) OUT_A/OUT_B OLEV 0 OUT_A/OUT_B OLEV 1 450 450 900 900 0.00 18 0x00 0xC5 450 550 900 1100 1.74 22 0x11 0xC5 450 650 900 1300 3.19 26 0x22 0xC5 450 750 900 1500 4.44 30 0x33 0xC5 450 850 900 1700 5.52 34 0x44 0xC5 450 950 900 1900 6.49 38 0x55 0xC5 450 1050 900 2100 7.36 42 0x66 0xC5 500 500 1000 1000 0.00 20 0x00 0xD5 500 600 1000 1200 1.58 24 0x11 0xD5 500 700 1000 1400 2.92 28 0x22 0xD5 500 800 1000 1600 4.08 32 0x33 0xD5 500 900 1000 1800 5.11 36 0x44 0xD5 500 1000 1000 2000 6.02 40 0x55 0xD5 500 1100 1000 2200 6.85 44 0x66 0xD5 550 550 1100 1100 0.00 22 0x00 0xD6 550 650 1100 1300 1.45 26 0x11 0xD6 550 750 1100 1500 2.69 30 0x22 0xD6 550 850 1100 1700 3.78 34 0x33 0xD6 550 950 1100 1900 4.75 38 0x44 0xD6 550 1050 1100 2100 5.62 42 0x55 0xD6 550 1150 1100 2300 6.41 46 0x66 0xD6 600 600 1200 1200 0.00 24 0x00 0xE6 600 700 1200 1400 1.34 28 0x11 0xE6 600 800 1200 1600 2.50 32 0x22 0xE6 600 900 1200 1800 3.52 36 0x33 0xE6 600 1000 1200 2000 4.44 40 0x44 0xE6 600 1100 1200 2200 5.26 44 0x55 0xE6 600 1200 1200 2400 6.02 48 0x66 0xE6 650 650 1300 1300 0.00 26 0x01 0xE6 650 750 1300 1500 1.24 30 0x12 0xE6 650 850 1300 1700 2.33 34 0x23 0xE6 650 950 1300 1900 3.30 38 0x34 0xE6 650 1050 1300 2100 4.17 42 0x45 0xE6 650 1150 1300 2300 4.96 46 0x56 0xE6 700 700 1400 1400 0.00 28 0x02 0xE6 700 800 1400 1600 1.16 32 0x13 0xE6 700 900 1400 1800 2.18 36 0x24 0xE6 700 1000 1400 2000 3.10 40 0x35 0xE6 700 1100 1400 2300 3.93 44 0x46 0xE6 750 750 1500 1500 0.00 30 0x03 0xE6 750 850 1500 1700 1.09 34 0x14 0xE6 750 950 1500 1900 2.05 38 0x25 0xE6 750 1050 1500 2100 2.92 42 0x36 0xE6 800 800 1600 1600 0.00 32 0x04 0xE6 800 900 1600 1800 1.02 36 0x15 0xE6 800 1000 1600 2000 1.94 40 0x26 0xE6 850 850 1700 1700 0.00 34 0x05 0xE6 850 950 1700 1900 0.97 38 0x16 0xE6 900 900 1800 1800 0.00 36 0x06 0xE6
configuration registers through the I2C control interface. Table 18. Squelch and Disable Control Registers Table 19. Squelch and Disable Functionality
Rev. C | Page 25 of 36 I2C CONTROL INTERFACE SERIAL INTERFACE GENERAL FUNCTIONALITY The ADN8102 register set is controlled through a 2-wire I2C interface. The ADN8102 acts only as an I2C slave device. Therefore, the I2C bus in the system needs to include an I2C master to configure the ADN8102 and other I2C devices that may be on the bus. Data transfers are controlled using the two I2C wires: the SCL input clock pin and the SDA bidirectional data pin. The ADN8102 I2C interface can be run in the standard (100 kHz) and fast (400 kHz) modes. The SDA line only changes value when the SCL pin is low with two exceptions. To indicate the beginning or continuation of a transfer, the SDA pin is driven low while the SCL pin is high, and to indicate the end of a transfer, the SDA line is driven high while the SCL line is high. Therefore, it is important to control the SCL clock to toggle only when the SDA line is stable, unless indicating a start, repeated start, or stop condition. I2C INTERFACE DATA TRANSFERS—DATA WRITE To write data to the ADN8102 register set, a microcontroller, or any other I2C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that need to be completed are listed as follows, where the signals are controlled by the I2C master, unless otherwise specified. A diagram of the procedure can be seen in Figure 42. 1. Send a start condition (while holding the SCL line high, pull the SDA line low). 2. Send the ADN8102 part address (seven bits) whose upper five bits are the static value 10010b and whose lower two bits are controlled by the ADDR[1:0] input pins. This transfer should be MSB first. 3. Send the write indicator bit (0). 4. Wait for the ADN8102 to acknowledge the request. 5. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first. 6. Wait for the ADN8102 to acknowledge the request. 7. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. 8. Wait for the ADN8102 to acknowledge the request. 9a. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. 9b. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 in this procedure to perform another write. 9c. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the read procedure (in the I2C Interface Data Transfers— Data Read section) to perform a read from another address. d. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 8 of the read procedure (in the I2C Interface Data Transfers— Data Read section) to perform a read from the same address set in Step 5. F igure 42 shows the ADN8102 write process. The SCL signal is shown along with a general write operation and a specific example. In the example, Data 0x92 is written to Address 0x6D of an ADN8102 part with a part address of 0x4B. The part address is seven bits wide. The upper five bits of the ADN8102 are internally set to 10010b. The lower two bits are controlled by the ADDR[1:0] pins. In this example, the bits controlled by the ADDR[1:0] pins are set to 11b. In Figure 42, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the ADN8102 slave. As for the SDA line, the data in the shaded polygons is driven by the ADN8102, whereas the data in the nonshaded polygons is driven by the I master. The end phase case shown is that of Step 9a. Note that the SDA line only changes when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, Step 1 and Step 9 in this case. SCL SDA SDA GENERAL CASE EXAMPLE START REGISTER ADDRACK ACK ACK STOPDATAR/WFIXED PART ADDR ADDR [1:0] 2 2 3 4 5 6 7 8 9a 07060-008 F igure 42. I2C Write Diagram
mode shift measured across the output termination resistors. swing and preemphasis settings listed in Table 17. Figure 44. Simplified Output Voltage Levels Diagram Table 20. Symbol Definitions
Table 21. Output Compliance for AC-Coupled Outputs
Table 22. I2C Register Definitions
Rev. C | Page 32 of 36 Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default OUT_A configuration 0xC0 EN DATA RATE PE[2] PE[1] PE[0] 0x20 OUT_A Output Level Control 1 0xC1 PE CTL SRC OUTA_OLEV1[6:0] 0x40 OUT_A Output Level Control 0 0xC2 OUTA_OLEV0[6:0] 0x40 OUT_A squelch control 0xC3 SQUELCH[3:0] DISABLE[3:0] 0xFF OUT_B configuration 0xE0 EN DATA RATE PE[2] PE[1] PE[0] 0x20 OUT_B Output Level Control 1 0xE1 PE CTL SRC OUTB_OLEV1[6:0] 0x40 OUT_B Output Level Control 0 0xE2 OUTB_OLEV0[6:0] 0x40 OUT_B squelch control 0xE3 SQUELCH[3:0] DISABLE[3:0] 0xFF 1 Read-only register.
Rev. C | Page 33 of 36 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.80 0.75 0.70 0.50 BSC BOTTOM VIEWTOP VIEW 6.30 6.20 SQ 6.10
0.05 MAX
0.02 NOM
0.203 REF
0.08 10-26-2018-A 9.10 9.00 SQ 8.90 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.20 MIN
7.50 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 0.45 0.40 0.35 PKG-004559 EXPOSED PAD END VIEW DETAIL A (JEDEC 95) PI N 1 IN D ICATO R AR E A OP TIO N S (SEE DETAIL A) PIN 1 INDICATOR AREA SEATING PLANE F igure 49. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-17) Dimensions shown in millimeters ORDERING GUIDE Model1 T emperature Range Package Description Package Option ADN8102ACPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17 ADN8102ACPZ-R7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-17 ADN8102-EVALZ E valuation Board 1 Z = RoHS Compliant Part.
Rev. C | Page 34 of 36 NOTES
Rev. C | Page 35 of 36 NOTES
Rev. C | Page 36 of 36 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners . D07060-8/21(C)