ADN4668ARUZ

ADN4668 AD | Alldatasheet

Document overview

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Technical content

3 V LVDS Quad CMOS

Differential Line Receiver ADN4668 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

±15 kV ESD protection on receiver input pins

400 Mbps (200 MHz) switching rates

Flow-through pin configuration simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay

3.3 V power supply

High impedance outputs on power-down Low power design (3 mW quiescent typical) Interoperable with existing 5 V LVDS drivers Accepts small swing (310 mV typical) differential input signal levels Supports open, short, and terminated input fail-safe

0 V to −100 mV threshold region

Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range of −40°C to +85°C Available in low profile TSSOP package

APPLICATIONS

Point-to-point data transmission Multidrop buses Clock distribution networks Backplane receivers FUNCTIONAL BLOCK DIAGRAM RIN1+ VCC GND ADN4668 RIN1– RIN2+ RIN2– RIN3+ RIN3– RIN4+ ROUT1 ROUT2 ROUT3 ROUT4 RIN4– EN EN 07237-001 Figure 1. GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow- through pin configuration for easy PCB layout and separation of input and output signals. The device accepts low voltage (310 mV typical) differential input signals and converts them to a single-ended, 3 V TTL/CMOS logic level. The ADN4668 also offers active-high and active-low enable/disable inputs (EN and EN) that control all four receivers. They disable the receivers and switch the outputs to a high impedance state. This high impedance state allows the outputs of one or more ADN4668s to be multiplexed together and reduces the quies- cent power consumption to 3 mW typical. The ADN4668 and its companion driver, the ADN4667, offer a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).

Rev. 0 | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

3/08—Revision 0: Initial Version

Rev. 0 | Page 3 of 12 SPECIFICATIONS VDD = 3.0 V to 3.6 V , CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1, 2 Table 1. Parameter Min Typ Max Unit Conditions/Comments LVDS INPUTS (RINx+, RINx−) Differential Input High Threshold, VTH at RINx+, RINx−3 −35 0 mV VCM = 1.2 V, 0.05 V, 2.95 V Differential Input Low Threshold, VTL at RINx+, RINx−3 −100 −35 mV VCM = 1.2 V, 0.05 V, 2.95 V Common-Mode Voltage Range, VCMR at RINx+, RINx−4 0.1 2.3 V VID = 200 mV p-p Input Current, IIN at RINx+, RINx− −10 ±5 +10 μA VIN = 2.8 V, VCC = 3.6 V or 0 V −10 ±1 +10 μA VIN = 0 V, VCC = 3.6 V or 0 V −20 ±1 +20 μA VIN = 3.6 V, VCC = 0 V Input High Voltage, VIH 2.0 VCC V Input Low Voltage, VIL GND 0.8 V Input Current, II −10 ±5 +10 μA VIN = 0 V or VCC, other input = VCC or GND Input Clamp Voltage, VCL −1.5 −0.8 V ICL = −18 mA OUTPUTS (ROUTx) Output High Voltage, VOH 2.7 3.3 V IOH = −0.4 mA, VID = 200 mV 2.7 3.3 V IOH = −0.4 mA, input terminated 2.7 3.3 V IOH = −0.4 mA, input shorted Output Low Voltage, VOL 0.05 0.25 V IOL = 2 mA, VID = −200 mV Output Short-Circuit Current, IOS5 −15 −47 −100 V Enabled, VOUT = 0 V Output Off State Current, IOZ −10 ±1 +10 μA Disabled, VOUT = 0 V or VCC POWER SUPPLY No Load Supply, Current Receivers Enabled, ICC 12 15 mA EN = VCC, inputs open No Load Supply, Current Receivers Disabled, ICCZ 1 5 mA EN = GND, inputs open ESD PROTECTION RINx+, RINx− Pins ±15 kV Human body model All Pins Except RINx+, RINx− ±3.5 kV Human body model 1 Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified. 2 All typicals are given for VCC = 3.3 V and TA = 25°C. 3 VCC is always higher than the RINx+ and RINx− voltage. RINx− and RINx+ have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the common voltage range is 0.1 V to 2.3 V. 4 VCMR is reduced for larger VID. For example, if VID = 400 mV, VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode range of 0 V to 2.4 V but is supported only with inputs shorted and no external common-mode voltage applied. VID up to VCC − 0 V can be applied to the RINx+/RINx− inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common-mode range. 5 Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Only one output should be shorted at a time; do not exceed the maximum junction temperature specification.

1 All typicals are given for VCC = 3.3 V and TA = 25°C. 2 Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tR and tF (0% to 100%) ≤ 3 ns for RINx+/RINx−. each other within the operating temperature range. 5 AC parameters are guaranteed by design and characterization. 6 Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified. 7 CL includes probe and jig capacitance. 8 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel. operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), load = 15 pF (stray plus probes). Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

Rev. 0 | Page 6 of 12 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VCC to GND −0.3 V to +4 V Input Voltage (RINx+, RINx−) to GND −0.3 V to VCC + 0.3 V Enable Input Voltage (EN, EN) to GND −0.3 V to VCC + 0.3 V Output Voltage (ROUTx) to GND −0.3 V to VCC + 0.3 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C Power Dissipation (TJ MAX − TA)/θJA θJA Thermal Impedance 150.4°C/W Reflow Soldering Peak Temperature Pb-Free 260°C ± 5°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 6. Pin Configuration Table 4. Pin Function Descriptions more positive than RIN1+, ROUT1 is low. is more negative than RIN1−, ROUT1 is low. is more negative than RIN2−, ROUT2 is low. more positive than RIN2+, ROUT2 is low. more positive than RIN3+, ROUT3 is low. is more negative than RIN3−, ROUT3 is low. is more negative than RIN4−, ROUT4 is low. more positive than RIN4+, ROUT4 is low. powers down the device when EN is high. this output is high. If the differential input voltage is negative, this output is low. this output is high. If the differential input voltage is negative, this output is low. 12 GND Ground Reference Point for All Circuitry on the Part. 13 VCC Power Supply Input. These parts can be operated from 3.0 V to 3.6 V. this output is high. If the differential input voltage is negative, this output is low. this output is high. If the differential input voltage is negative, this output is low.

Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the property of their respective owners.