ADN4663BRZ-REEL7

ADN4663BRZ AD | Alldatasheet

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Technical content

Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

FEATURES

±15 kV ESD protection on output pins

600 Mbps (300 MHz) switching rates

Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.5 ns maximum propagation delay

3.3 V power supply

±355 mV differential signaling Low power dissipation: 23 mW typical Interoperable with existing 5 V LVDS receivers Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (−40°C to +85°C) Available in surface-mount (SOIC) package

APPLICATIONS

Backplane data transmission Cable data transmission Clock distribution FUNCTIONAL BLOCK DIAGRAM DIN1 DOUT1+ DOUT1– VCC ADN4663 DIN2 DOUT2+ DOUT2– GND 07927-001 Figure 1. GENERAL DESCRIPTION The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted-pair cable. The transmitted signal develops a differential voltage of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver. The ADN4663 and a companion receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).

Rev. 0 | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

1/09—Revision 0: Initial Version

Rev. 0 | Page 3 of 12 SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1, 2 Symbol Min Typ Max Unit Test Conditions LVDS OUTPUTS (DOUTx+, DOUTx−) Differential Output Voltage VOD 250 355 450 mV See Figure 2 and Figure 4 Change in Magnitude of VOD for Complementary Output States ΔVOD 1 35 |mV| See Figure 2 and Figure 4 Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 and Figure 4 Change in Magnitude of VOS for Complementary Output States ΔVOS 3 25 |mV| See Figure 2 and Figure 4 Output High Voltage VOH 1.4 1.6 V See Figure 2 and Figure 4 Output Low Voltage VOL 0.90 1.1 V See Figure 2 and Figure 4 INPUTS (DIN1, DIN2) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL GND 0.8 V Input High Current IIH −10 ±2 +10 μA VIN = 3.3 V or 2.4 V Input Low Current IIL −10 ±1 +10 μA VIN = GND or 0.5 V Input Clamp Voltage VCL −1.5 −0.6 V ICL = −18 mA LVDS OUTPUT PROTECTION (DOUTx+, DOUTx−) Output Short-Circuit Current3 I OS −5.7 −8.0 mA DINx = VCC, DOUTx+ = 0 V or DINx = GND, DOUTx− = 0 V LVDS OUTPUT LEAKAGE (DOUTx+, DOUTx−) Power-Off Leakage IOFF −10 ±1 +10 μA VOUT = VCC or GND, VCC = 0 V POWER SUPPLY Supply Current, Unloaded ICC 8 14 mA No load, DINx = VCC or GND Supply Current, Loaded ICCL 10 20 mA DINx = VCC or GND ESD PROTECTION DOUTx+, DOUTx− Pins ±15 kV Human body model All Pins Except DOUTx+, DOUTx− ±4 kV Human body model 1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS. 2 The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 Ω to 110 Ω. 3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.

Rev. 0 | Page 4 of 12 AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter2 Symbol Min Typ Max Unit Conditions/Comments3, 4 Differential Propagation Delay High to Low tPHLD 0.3 0.8 1.5 ns See Figure 3 and Figure 4 Differential Propagation Delay Low to High tPLHD 0.3 1.1 1.5 ns See Figure 3 and Figure 4 Differential Pulse Skew |tPHLD − tPLHD|5 t SKD1 0 0.3 0.7 ns See Figure 3 and Figure 4 Channel-to-Channel Skew6 t SKD2 0 0.4 0.8 ns See Figure 3 and Figure 4 Differential Part-to-Part Skew7 t SKD3 0 1.0 ns See Figure 3 and Figure 4 Differential Part-to-Part Skew8 t SKD4 0 1.2 ns See Figure 3 and Figure 4 Rise Time tTLH 0.2 0.5 1.0 ns See Figure 3 and Figure 4 Fall Time tTHL 0.2 0.5 1.0 ns See Figure 3 and Figure 4 Maximum Operating Frequency9 f MAX 350 MHz See Figure 3 1 CL includes probe and jig capacitance. 2 AC parameters are guaranteed by design and characterization. 3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns. 4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND. 5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6 tSKD2 is the differential channel-to-channel skew of any event on the same device. 7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. 8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. 9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.

Rev. 0 | Page 6 of 12 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 3. Parameter Rating VCC to GND −0.3 V to +4 V Input Voltage (DINx) to GND −0.3 V to VCC + 0.3 V Output Voltage (DOUTx+, DOUTx−) to GND −0.3 V to VCC + 0.3 V Short-Circuit Duration (DOUTx+, DOUTx−) to GND Continuous Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Power Dissipation (TJ max − TA)/θJA θJA Thermal Impedance 149.5°C/W Reflow Soldering Peak Temperature Pb-Free 260°C ± 5°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 5. Pin Configuration Table 4. Pin Function Descriptions 10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND. 2 D IN1 Driver Channel 1 Logic Input. 3 D IN2 Driver Channel 2 Logic Input. 4 GND Ground reference point for all circuitry on the part.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)] registered trademarks are the prop erty of their respective owners.