DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 25
Technical content
5 kV RMS and 3.75 kV RMS, Dual-Channel LVDS Gigabit Isolators Data Sheet ADN4654/ADN4655/ADN4656 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with
1.1 Gbps PRBS
Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance
APPLICATIONS
Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links FUNCTIONAL BLOCK DIAGRAMS LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DIN2– DIN2+ VDD2 DOUT2+ DOUT2– DOUT1– DOUT1+ ADN4654 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 17011-001 Figure 1. LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DOUT2– DOUT2+ VDD2 DIN2+ DIN2– DOUT1– DOUT1+ ADN4655 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 17011-102 Figure 2. LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DOUT2– DOUT2+ VDD2 DIN2+ DIN2– DOUT1– DOUT1+ ADN4656 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 17011-050 Figure 3. GENERAL DESCRIPTION The ADN4654/ADN4655/ADN46561 are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler® technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain. The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven. For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADN4654/ADN4655/ADN4656 Data Sheet Rev. C | Page 2 of 25 TABLE OF CONTENTS DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
REVISION HISTORY
6/2019—Rev. B to Rev. C 3/2019—Rev. A to Rev. B Changes to Title, Features Section, General Description Section, 1/2019—Rev. 0 to Rev. A Changes to Theory of Operation Section and Truth Table and 11/2018—Revision 0: Initial Version
Data Sheet ADN4654/ADN4655/ADN4656 Rev. C | Page 3 of 25 SPECIFICATIONS For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = −40°C to +125°C, unless otherwise noted. For all typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUTS (RECEIVERS) Input Threshold See Figure 38 and Table 2 High VTH 100 mV Low VTL −100 mV Differential Input Voltage |VID| 100 mV See Figure 38 and Table 2 Input Common-Mode Voltage VIC 0.5|VID| 2.4 − 0.5|VID| V See Figure 38 and Table 2 Input Current, High and Low IIH, IIL −5 +5 µA DINx± = VDDx or 0 V, other input = 1.2 V, VDDx =
2.5 V or 0 V
Differential Input Capacitance1 CINx± 2 pF DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input = 1.2 V2 OUTPUTS (DRIVERS) Differential Output Voltage |VOD| 250 310 450 mV See Figure 36 and Figure 37, load resistance (RL) = 100 Ω VOD Magnitude Change |ΔVOD| 50 mV See Figure 36 and Figure 37, RL = 100 Ω Offset Voltage VOS 1.125 1.17 1.375 V See Figure 36, RL = 100 Ω VOS Magnitude Change ΔVOS 50 mV See Figure 36, RL = 100 Ω VOS, Peak to Peak1 VOS(PP) 150 mV See Figure 36, RL = 100 Ω Output Short-Circuit Current IOS −20 mA DOUTx± = 0 V 12 mA |VOD| = 0 V Differential Output Capacitance1 COUTx± 5 pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
Supply Current IDD1, IIN1, IDD2, or IIN2 ADN4655/ADN4656 only 55 mA No output load, inputs with 100 Ω, no applied |VID| 58 82 mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz ADN4654 only 50 65 mA No output load, inputs with 100 Ω, |VID| = 200 mV 60 80 mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz LDO Input Range VIN1 or VIN2 3.0 3.3 3.6 V No external supply on VDD1 or VDD2 LDO Output Range VDD1 or VDD2 2.375 2.5 2.625 V Power Supply Ripple Rejection, Phase Spur Level PSRR −75 dBc Phase spur level on DOUTx± with 0.55 GHz clock on DINx± and applied ripple of 100 kHz, 100 mV p-p on a 2.5 V supply to VDD1 or VDD2 COMMON-MODE TRANSIENT IMMUNITY3 |CM| 25 50 kV/µs Common-mode voltage (VCM) = 1000 V, transient magnitude = 800 V 1 These specifications are guaranteed by design and characterization. 2 t denotes time. 3 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx− pin (no change in output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Table 2. Test Voltages for Receiver Operation specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted. 1 These specifications are guaranteed by design and characterization. Channel 1 or Channel 2 propagation delay. values of tPHLx within a device, whichever of the two is greater. values of tPHLx across multiple devices, whichever of the two is greater. 5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%). 6 This specification is measured over a population of ~7,000,000 edges. 7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)). 8 This specification is measured over a population of ~3,000,000 edges. 9 Using the formula: tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP). 10 With input phase jitter of 250 fs rms subtracted. 11 With input phase jitter of 100 fs rms subtracted. 12 The fail-safe delay is the delay before DOUTx± is switched high to reflect an idle input to DINx± (|VID| < 100 mV, with open, short, or terminated input condition).
Figure 4. Fail-Safe Timing Diagram For additional information, see www.analog.com/icouplersafety. Table 4. 20-Lead SOIC_W Package Table 5. 20-Lead SSOP Package
ADN4654/ADN4655/ADN4656 Data Sheet Rev. C | Page 6 of 25 PACKAGE CHARACTERISTICS Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 RI-O 1013 Ω Capacitance (Input to Output)1 CI-O 2.2 pF Frequency = 1 MHz Input Capacitance2 CI 3.7 pF 1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross- isolation waveforms and insulation levels. Table 7. UL (Pending) CSA (Pending) VDE (Pending) To Be Recognized Under UL 1577 Component Recognition Program1 To be approved under CSA Component Acceptance Notice 5A To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Single Protection, Isolation Voltage Reinforced insulation, VIORM = 424 VPEAK, VIOSM = 8000 VPEAK 20-Lead SOIC, 5000 V rms 20-Lead SSOP , 3750 V rms File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 6000 V rms (20-lead SOIC_W) or ≥ 4500 V rms (20-lead SSOP) for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each ADN4654/ADN4655/ADN4656 is proof tested by applying an insulation test voltage ≥ 795 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
636 V PEAK
509 V PEAK
1 For information about tM, tINI, and VIO, see DIN V VDE V 0884-10. Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values
resistance measured in a one-cubic foot sealed enclosure. Table 11. Thermal Resistance 1 Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC PCB. Table 12. Maximum Continuous Working Voltage1
Figure 6. ADN4654 Pin Configuration Table 13. ADN4654 Pin Function Descriptions a 2.5 V supply, connect VIN1 directly to VDD1. 5 DIN1+ Noninverted Differential Input 1. 6 DIN1− Inverted Differential Input 1. 7 DIN2+ Noninverted Differential Input 2. 8 DIN2− Inverted Differential Input 2. 13 DOUT2− Inverted Differential Output 2. 14 DOUT2+ Noninverted Differential Output 2. 15 DOUT1− Inverted Differential Output 1. 16 DOUT1+ Noninverted Differential Output 1. a 2.5 V supply, connect VIN2 directly to VDD2.
Figure 7. ADN4655 Pin Configuration Table 14. ADN4655 Pin Function Descriptions a 2.5 V supply, connect VIN1 directly to VDD1. 5 DIN1+ Noninverted Differential Input 1. 6 DIN1− Inverted Differential Input 1. 7 DOUT2+ Noninverted Differential Output 2. 8 DOUT2− Inverted Differential Output 2. 13 DIN2− Inverted Differential Input 2. 14 DIN2+ Noninverted Differential Input 2. 15 DOUT1− Inverted Differential Output 1. 16 DOUT1+ Noninverted Differential Output 1. a 2.5 V supply, connect VIN2 directly to VDD2.
Figure 8. ADN4656 Pin Configuration Table 15. ADN4656 Pin Function Descriptions a 2.5 V supply, connect VIN1 directly to VDD1. 5 DOUT1+ Noninverted Differential Output 1. 6 DOUT1− Inverted Differential Output 1. 7 DIN2+ Noninverted Differential Input 2. 8 DIN2− Inverted Differential Input 2. 13 DOUT2− Inverted Differential Output 2. 14 DOUT2+ Noninverted Differential Output 2. 15 DIN1− Inverted Differential Input 1. 16 DIN1+ Noninverted Differential Input 1. a 2.5 V supply, connect VIN2 directly to VDD2.
allows drop-in isolation of the LVDS signal chains. and an LVDS driver outputs the same state as the input. any DINx± pin, the corresponding DOUTx+ pin sources current. twice the differential voltage magnitude (|VID|). conditions, as implemented by the ADN4655/ADN4656. remains between +100 mV and −100 mV for some nanoseconds. potentially trigger the fail-safe circuit on a high to low crossover. and fall time must be ≤5 ns to avoid triggering a fail-safe state. 100 mV if the fail-safe cannot trigger. Table 16. ADN4654 Input and Output Operation Table 17. ADN4655/ADN4656 Input and Output Operation
Data Sheet ADN4654/ADN4655/ADN4656 Rev. C | Page 19 of 25 ISOLATION In response to any change in the input state detected by the integrated LVDS receiver, an encoder circuit sends narrow (~1 ns) pulses to a decoder circuit using integrated transformer coils. The decoder is bistable and is, therefore, either set or reset by the pulses that indicate input transitions. The decoder state determines the LVDS driver output state in normal operation, which reflects the isolated LVDS buffer input state. In the absence of input transitions for more than approximately 1 µs, a periodic set of refresh pulses, indicative of the correct input state, ensures dc correctness at the output (including the fail-safe output state, if applicable). On power-up, the output state may initially be in the incorrect dc state if there are no input transitions. The output state is corrected within 1 µs by the refresh pulses. If the decoder receives no internal pulses for more than approximately 1 µs, the device assumes that the input side is unpowered or nonfunctional, in which case, the output is set to a positive differential voltage (logic high).
apply best practices for the LVDS trace layout and termination. receiver, across the DINx+ and DINx− pins. crosstalk between adjacent pairs. sufficient margin below Class B emissions limits. cable shield or PCB ground connections to earth or chassis.
9 VDD212
Figure 40. Required PCB Layout When Not Using LDO Regulator (2.5 V Supply) pins (LDO output), as shown in Figure 41. Figure 41. Required PCB Layout When Using LDO Regulator (3.3 V Supply) and clock lanes) and the LVDS levels required by the ADN4654.
- SUPPLY BIASED TERMINATION
Figure 42. Example Isolated Video Interface (HDMI) Using the ADN4654
voltage applicable to tracking is specified in most standards. ac component time varying voltage stress, which causes wear out.
60 Hz sinusoidal stress because this type of waveform reflects
ac rms voltage determines the product lifetime. VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. required by a system standard. specific system level standards. Figure 45. Critical Voltage Example
0.05 MIN
0.65 BSC
2.00 MAX
Figure 46. 20-Lead Shrink Small Outline Package [SSOP] REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]
Data Sheet ADN4654/ADN4655/ADN4656 Rev. C | Page 25 of 25 ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADN4654BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADN4654BRSZ-RL7 −40°C to +125°C 20-Lead Shri nk Small Outline Package [SSOP] RS-20 ADN4654BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4654BRWZ-RL7 −40°C to +125°C 20-Lead Wide Bo dy, Standard Small Outline Package [SOIC_W] RW-20 ADN4655BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4655BRWZ-RL7 −40°C to +125°C 20-Lead Wide Bo dy, Standard Small Outline Package [SOIC_W] RW-20 ADN4656BRWZ −40°C to +125°C 20-Lead Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4656BRWZ-RL7 −40°C to +125°C 20-Lead Wide Bo dy, Standard Small Outline Package [SOIC_W] RW-20 EVAL-ADN4654EB1Z Evaluation Board EVAL-ADN4655EB1Z Evaluation Board EVAL-ADN4656EB1Z Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D17011-0-6/19(C)