ADN4651BRSZ-RL7

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5 kV RMS/3.75 kV RMS, 600 Mbps, Dual-Channel LVDS Isolators Data Sheet ADN4650/ADN4651/ADN4652 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2015–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

5 kV rms/3.75 kV rms LVDS isolator Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Up to 600 Mbps switching with low jitter 4.5 ns maximum propagation delay 151 ps maximum peak-to-peak total jitter at 600 Mbps 100 ps maximum pulse skew 600 ps maximum part to part skew 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection and glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN55022 Class B radiated emissions limits with

600 Mbps PRBS

Safety and regulatory approvals (20-lead SOIC package) UL: 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 V peak Fail-safe output high for open, short, and terminated input conditions (ADN4651/ADN4652) Operating temperature range: −40°C to +125°C Choice of package and isolation options 3.75 kV rms in highly integrated 20-lead SSOP 5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance

APPLICATIONS

Analog front-end (AFE) isolation Data plane isolation Isolated high speed clock and data links Isolated serial peripheral interface (SPI) over LVDS GENERAL DESCRIPTION The ADN4650/ADN4651/ADN46521 are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 600 Mbps with very low jitter. The devices integrate Analog Devices, Inc., iCoupler® technology, enhanced for high speed operation, to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This technology allows drop-in isolation of an LVDS signal chain. Multiple channel configurations are offered, and the LVDS receivers on the ADN4651/ADN4652 include a fail-safe mechanism to FUNCTIONAL BLOCK DIAGRAMS LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DIN2– DIN2+ VDD2 DOUT2+ DOUT2– DOUT1– DOUT1+ ADN4650 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 13677-101 Figure 1. LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DOUT2– DOUT2+ VDD2 DIN2+ DIN2– DOUT1– DOUT1+ ADN4651 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 13677-001 Figure 2. LVDS LVDS GND1 GND2 VDD1 VIN1 VIN2 DIN1+ DIN1– DOUT2– DOUT2+ VDD2 DIN2+ DIN2– DOUT1– DOUT1+ ADN4652 LDO LDO DIGITAL ISOLATOR ISOLATION BARRIER 13677-103 Figure 3. ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated, but not driven. For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout regulator (LDO) can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and are available in a 20-lead, wide body SOIC package with 5 kV rms isolation or a 20-lead SSOP package with 3.75 kV rms isolation. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

ADN4650/ADN4651/ADN4652 Data Sheet Rev. E | Page 2 of 25 TABLE OF CONTENTS DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

REVISION HISTORY

6/2019—Rev. D to Rev. E Changed UL (Pending) Column to UL Column, CSA (Pending) Column to CSA Column, VDE (Pending) Column to VDE Column, Table 7, and DIN V VDE V 0884-10 (VDE V 0884-110) Insulation Characteristics (Pending) Section to DIN V VDE V 1/2017—Rev. C to Rev. D 9/2016—Rev. B to Rev. C Changes to Title, Features Section, and General Description .... 1 4/2016—Rev. A to Rev. B Changes to Skew Parameter and Fail-Safe Delay Parameter, 2/2016—Rev. 0 to Rev. A Changes to Skew Parameter and Fail-Safe Delay Parameter, 11/2015—Revision 0: Initial Version

Data Sheet ADN4650/ADN4651/ADN4652 Rev. E | Page 3 of 25 SPECIFICATIONS For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUTS (RECEIVERS) Input Threshold See Figure 36 and Table 2 High VTH 100 mV Low VTL −100 mV Differential Input Voltage |VID| 100 mV See Figure 36 and Table 2 Input Common-Mode Voltage VIC 0.5|VID| 2.4 − 0.5|VID| V See Figure 36 and Table 2 Input Current IIH, IIL −5 +5 µA DINx± = VDD or 0 V, other input = 1.2 V, VDD = 2.5 V or 0 V Differential Input Capacitance1 CINx± 2 pF DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input = 1.2 V OUTPUTS (DRIVERS) Differential Output Voltage |VOD| 250 310 450 mV See Figure 34 and Figure 35, RL = 100 Ω VOD Magnitude Change |ΔVOD| 50 mV See Figure 34 and Figure 35, RL = 100 Ω Offset Voltage VOS 1.125 1.17 1.375 V See Figure 34, RL = 100 Ω VOS Magnitude Change ΔVOS 50 mV See Figure 34, RL = 100 Ω VOS Peak-to-Peak1 VOS(PP) 150 mV See Figure 34, RL = 100 Ω Output Short-Circuit Current IOS −20 mA DOUTx± = 0 V 12 mA |VOD| = 0 V Differential Output Capacitance1 COUTx± 5 pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =

1.2 V, VDD1 or VDD2 = 0 V

Supply Current IDD1, IIN1, IDD2, or IIN2 ADN4651/ADN4652 Only 55 mA No output load, inputs with 100 Ω, no applied |VID| 58 80 mA All outputs loaded, RL = 100 Ω, f = 300 MHz ADN4650 Only 50 65 mA No output load, inputs with 100 Ω, |VID| = 200 mV 60 72 mA All outputs loaded, RL = 100 Ω, f = 300 MHz LDO Input Range VIN1 or VIN2 3.0 3.3 3.6 V No external supply on VDD1 or VDD2 LDO Output Range VDD1 or VDD2 2.375 2.5 2.625 V Power Supply Ripple Rejection, Phase Spur Level PSRR −75 dBc Phase spur level on DOUTx± with 300 MHz clock on DINx± and applied ripple of 100 kHz, 100 mV p-p on a 2.5 V supply to VDD1 or VDD2 COMMON-MODE TRANSIENT IMMUNITY2 |CM| 25 50 kV/µs VCM = 1000 V, transient magnitude = 800 V 1 These specifications are guaranteed by design and characterization. 2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx− pin (no change on output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Table 2. Test Voltages for Receiver Operation specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C. 1 These specifications are guaranteed by design and characterization. 2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tPHLx|. values of tPHLx within a device, whichever of the two is greater. values of tPHLx across multiple devices, whichever of the two is greater. 5 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. VID = 400 mV p-p, tR = tF = 0.3 ns (20% to 80%). 6 This specification is measured over a population of ~7,000,000 edges. 7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)). 8 This specification is measured over a population of ~3,000,000 edges. 9 Using the formula tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP). 10 With input phase jitter of 250 fs rms subtracted. 11 With input phase jitter of 100 fs rms subtracted. 12 The fail-safe delay is the delay before DOUTx± is switched high to reflect idle input to DINx± (|VID| < 100 mV, open or short/terminated input condition).

Figure 4. Fail-Safe Timing Diagram For additional information, see www.analog.com/icouplersafety. Table 4. 20-Lead SOIC Package Table 5. 20-Lead SSOP Package

ADN4650/ADN4651/ADN4652 Data Sheet Rev. E | Page 6 of 25 PACKAGE CHARACTERISTICS Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 RI-O 1013 Ω Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz Input Capacitance2 CI 3.7 pF IC Junction to Ambient Thermal Resistance θJA Thermal simulation with 4-layer standard JEDEC PCB 20-Lead SOIC 45.7 °C/W 20-Lead SSOP 69.6 °C/W 1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION See Table 12 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross- isolation waveforms and insulation levels. Table 7. UL CSA VDE To Be Recognized Under UL 1577 Component Recognition Program1 To be approved under CSA Component Acceptance Notice 5A To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Single Protection, Isolation Voltage Reinforced insulation, VIORM = 424 V peak, VIOSM = 6000 V peak 20-lead SOIC, 5000 V rms 20-lead SSOP , 3750 V rms Basic insulation, VIORM = 424 V peak, VIOSM = 10,000 V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥6000 V rms (20-lead SOIC) or ≥4500 V rms (20-lead SSOP) for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each ADN4650/ADN4651/ADN4652 is proof tested by applying an insulation test voltage ≥795 V peak for 1 sec (partial discharge detection limit = 5 pC). DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. Table 8. Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 600 V rms I to III Climatic Classification 40/125/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Working Insulation Voltage VIORM 424 V peak Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Vpd (m) 795 V peak Input to Output Test Voltage, Method A Vpd (m) After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC

636 V peak

After Input and/or Safety Test Subgroup 2 and Subgroup 3 VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC

509 V peak

Highest Allowable Overvoltage VIOTM 5000 V peak Surge Isolation Voltage Basic VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 10,000 V peak Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 V peak

Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values

soldered in a circuit board for surface-mount packages. Table 11. Thermal Resistance Table 12. Maximum Continuous Working Voltage1

Figure 6. ADN4650 Pin Configuration Table 13. ADN4650 Pin Function Descriptions 2.5 V supply, connect VIN1 directly to VDD1. 5 D IN1+ Noninverted Differential Input 1. 6 D IN1− Inverted Differential Input 1. 7 D IN2+ Noninverted Differential Input 2. 8 D IN2− Inverted Differential Input 2. 13 D OUT2− Inverted Differential Output 2. 14 D OUT2+ Noninverted Differential Output 2. 15 D OUT1− Inverted Differential Output 1. 16 D OUT1+ Noninverted Differential Output 1. 2.5 V supply, connect VIN2 directly to VDD2.

Figure 7. ADN4651 Pin Configuration Table 14. ADN4651 Pin Function Descriptions 2.5 V supply, connect VIN1 directly to VDD1. 5 D IN1+ Noninverted Differential Input 1. 6 D IN1− Inverted Differential Input 1. 7 D OUT2+ Noninverted Differential Output 2. 8 D OUT2− Inverted Differential Output 2. 13 D IN2− Inverted Differential Input 2. 14 D IN2+ Noninverted Differential Input 2. 15 D OUT1− Inverted Differential Output 1. 16 D OUT1+ Noninverted Differential Output 1. 2.5 V supply, connect VIN2 directly to VDD2.

Figure 8. ADN4652 Pin Configuration Table 15. ADN4652 Pin Function Descriptions 2.5 V supply, connect VIN1 directly to VDD1. 5 D OUT1+ Noninverted Differential Output 1. 6 D OUT1− Inverted Differential Output 1. 7 D IN2+ Noninverted Differential Input 2. 8 D IN2− Inverted Differential Input 2. 13 D OUT2− Inverted Differential Output 2. 14 D OUT2+ Noninverted Differential Output 2. 15 D IN1− Inverted Differential Input 1. 16 D IN1+ Noninverted Differential Input 1. 2.5 V supply, connect VIN2 directly to VDD2.

Figure 33. ADN4651 Eye Diagram for DOUT2±

allows drop-in isolation of LVDS signal chains. and an LVDS driver outputs the same state as the input. is twice the differential voltage magnitude (|VID|). before the output is guaranteed to be high (VOD ≥ 250 mV). rise/fall time must be ≤5 ns to avoid triggering a fail-safe state. rise/fall time of up to 10 ns without triggering a fail-safe state. the fail-safe cannot trigger). Table 16. ADN4650 Input/Output Operation Table 17. ADN4651/ADN4652 Input/Output Operation

pulses to a decoder circuit using integrated transformer coils. and this in turn reflects the isolated LVDS buffer input state. or set the ADN4651/ADN4652 output to the fail-safe state. corrected within 1 µs by the refresh pulses. a positive differential voltage (logic high). possible to the receiver, across the DINx+ and DINx− pins. minimizing electromagnetic interference (EMI) from the PCB. minimize crosstalk between adjacent pairs. frequencies with no extra PCB measures. cable shield or PCB ground connections to earth/chassis. as shown in Figure 38, using the ADN4651 as an example.

9 VDD212

Figure 38. Required PCB Layout When Not Using the LDO (2.5 V Supply) Figure 39. Required PCB Layout When Using the LDO (3.3 V Supply) susceptible mode of operation for this product.

the thickness, material properties, and the voltage stress applied. to tracking that is specified in most standards.

60 Hz sinusoidal stress because this reflects isolation from line

determines the product lifetime. VRMS is the total rms working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. required by a system standard. sine wave, and it is well within the limit for a 50-year service life. can differ for specific system level standards. Figure 42. Critical Voltage Example

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 20-Lead Standard Small Outline Package [SOIC_W]

0.05 MIN

0.65 BSC

2.00 MAX

Figure 48. 20-Lead Shrink Small Outline Package [SSOP]

Data Sheet ADN4650/ADN4651/ADN4652 Rev. E | Page 25 of 25 Model1 Temperature Range Package Description Package Option ADN4651BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADN4651BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADN4651BRWZ −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4651BRWZ-RL7 −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4652BRSZ −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADN4652BRSZ-RL7 −40°C to +125°C 20-Lead Shrink Small Outline Package [SSOP] RS-20 ADN4652BRWZ −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20 ADN4652BRWZ-RL7 −40°C to +125°C 20-Lead, Wide Body, Standard Small Outline Package [SOIC_W] RW-20 EVAL-ADN4650EBZ EVAL-ADN4650EB1Z EVAL-ADN4651EBZ EVAL-ADN4651EB1Z EVAL-ADN4652EBZ ADN4650 SSOP Evaluation Board ADN4650 SOIC_W Evaluation Board ADN4651 SSOP Evaluation Board ADN4651 SOIC_W Evaluation Board ADN4652 SSOP Evaluation Board EVAL-ADN4652EB1Z A DN4652 SOIC_W Evaluation Board 1 Z = RoHS Compliant Part. ©2015–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13677-0-6/19(E)