ADN4624BCPZ-RL

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• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 27

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Data Sheet ADN4622/ADN4624 TABLE OF CONTENTS analog.com Rev. B | 2 of 27 DIN V VDE V 0884-11 (VDE V 0884-11)

REVISION HISTORY

10/2022—Rev. A to Rev. B 10/2021—Rev. 0 to Rev. A

Data Sheet ADN4622/ADN4624 TABLE OF CONTENTS analog.com Rev. B | 3 of 27 4/2021—Revision 0: Initial Version

otherwise noted. For all specifications, REFRESH1 = GND1 and REFRESH2 = GND2, unless otherwise noted. Table 1. Specifications

1.2 V, and VDD1 or VDD2 = 0 V

1 These specifications are guaranteed by design and characterization. transition on the corresponding DINx+ or DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Table 2. Test Voltages for Receiver Operation specifications, VDD1 = VDD2 = 1.8 V and TA = 25°C. For all specifications, REFRESH1 = VDD1 and REFRESH2 = VDD2, unless otherwise noted. Table 3. Timing Specifications

1 These specifications are guaranteed by design and characterization. 2 Duty cycle or pulse skew is the magnitude of the maximum difference between tPLH and tPHL for any Channel x of a device (where x = 1, 2, 3, or 4), that is, |tPLHx – tPHLx|. values of tPHLx within a device, whichever of the two is greater. of tPHLx across multiple devices, whichever of the two is greater. 6 This specification is measured over a population of ~3,000,000 edges. 7 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK(D)). 8 Using the following formula: tTJ(PP) = 14 × tRJ(RMS) + tDJ(PP). 9 With an input phase jitter of 340 fs rms subtracted. 10 With an input phase jitter of 155 fs rms subtracted. For additional information, see www.analog.com/icouplersafety. Table 4. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package Table 5. CP-32-32 Lead Frame Chip-Scale Package [LFCSP]

Table 6. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package and CP-32-32 Lead Frame Chip-Scale Package [LFCSP] (Pin 17 through Pin 32 for LFCSP). 2 Input capacitance is from any input data pin to ground. waveforms and insulation levels. Table 7. RN-28-1 Wide-Body with Finer Pitch [SOIC_W_FP] Package 1 In accordance with UL 1577, each ADN4622/ADN4624 is proof tested by applying an insulation test voltage ≥6840 V rms for 1 sec. 2 Working voltages are quoted for Pollution Degree 2, Material Group III. ADN4622/ADN4624 case material has been evaluated by CSA as Material Group I. Table 8. CP-32-32 Lead Frame Chip-Scale Package [LFCSP] 1 In accordance with UL 1577, each ADN4622/ADN4624 is proof tested by applying an insulation test voltage ≥1800 V rms for 1 sec.

Table 9. RN-28-1 Wide Body with Finer Pitch [SOIC_W_FP] Package

1274 VPEAK

1019 VPEAK

1 For information about tM, tINI, and VIO, see DIN V VDE V 0884-11. Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-11, SOIC_W_FP

Table 10. CP-32-32 Lead Frame Chip-Scale Package [LFCSP]

840 VPEAK

672 VPEAK

1 For information about tM, tINI, and VIO, see DIN V VDE V 0884-11. Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-11, LFCSP Table 11. Recommended Operating Conditions

Table 12. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. Table 13. Maximum Continuous Working Voltage, RN-28-1 Standard Small

1 Maximum continuous working voltage refers to the continuous voltage magni-

tude imposed across the isolation barrier in a Pollution Degree 2 environment. See the Insulation Lifetime section for more details. Table 14. Maximum Continuous Working Voltage, CP-32-32 Lead Frame Chip- tude imposed across the isolation barrier in a Pollution Degree 2 environment. See the Insulation Lifetime section for more details. environment. Close attention to PCB thermal design is required. measured in a one cubic foot sealed enclosure. Table 15. Thermal Resistance

1 Test Condition 1: thermal impedance simulated with 4-layer standard JEDEC

sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. compatibility: Part 4-2 (IEC) per IEC 61000-4-2. Table 16. ADN4622/ADN4624, 28-Lead SOIC_W_FP 1 All pins to respective GNDx, 1.5 kΩ, 100 pF. 2 LVDS pins to isolated GNDx across isolation barrier. Table 17. ADN4622/ADN4624, 32-Lead LFCSP 1 All pins to respective GNDx, 1.5 kΩ, 100 pF. 2 LVDS pins to isolated GNDx across isolation barrier. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 5. ADN4622 SOIC_W_FP Pin Configuration Table 18. ADN4622 SOIC_W_FP Pin Function Descriptions 1, 14 VDD1 1.8 V Power Supply for Side 1. Connect both pins externally and bypass to the adjacent GND1 pins with 0.1 μF capacitors. 3 VIO1 3.3 V Input and Output Power Supply for Side 1. Bypass to the adjacent GND1 pin with a 0.1 μF capacitor. 4 DIN1+ Noninverted Differential Input 1. 5 DIN1− Inverted Differential Input 1. 6 DIN2+ Noninverted Differential Input 2. 7 DIN2− Inverted Differential Input 2. 8 DOUT3− Inverted Differential Output 3. 9 DOUT3+ Noninverted Differential Output 3. 10 DOUT4− Inverted Differential Output 4. 11 DOUT4+ Noninverted Differential Output 4. lower jitter, and quieter operation with refresh disabled. 15, 28 VDD2 1.8 V Power Supply for Side 2. Connect both pins externally and bypass to the adjacent GND2 pins with 0.1 μF capacitors. 17 VIO2 3.3 V Input and Output Power Supply for Side 2. Bypass to the adjacent GND2 pin with a 0.1 μF capacitor. 18 DIN4+ Noninverted Differential Input 4. 19 DIN4− Inverted Differential Input 4. 20 DIN3+ Noninverted Differential Input 3. 21 DIN3− Inverted Differential Input 3. 22 DOUT2− Inverted Differential Output 2. 23 DOUT2+ Noninverted Differential Output 2. 24 DOUT1− Inverted Differential Output 1. 25 DOUT1+ Noninverted Differential Output 1. lower jitter, and quieter operation with refresh disabled.

Figure 6. ADN4624 SOIC_W_FP Pin Configuration Table 19. ADN4624 SOIC_W_FP Pin Function Descriptions 1, 14 VDD1 1.8 V Power Supply for Side 1. Connect both pins externally and bypass to the adjacent GND1 pins with 0.1 μF capacitors. 4 DIN1+ Noninverted Differential Input 1. 5 DIN1− Inverted Differential Input 1. 6 DIN2+ Noninverted Differential Input 2. 7 DIN2− Inverted Differential Input 2. 8 DIN3+ Noninverted Differential Input 3. 9 DIN3− Inverted Differential Input 3. 10 DIN4+ Noninverted Differential Input 4. 11 DIN4− Inverted Differential Input 4. lower jitter, and quieter operation with refresh disabled. 15, 28 VDD2 1.8 V Power Supply for Side 2. Connect both pins externally and bypass to the adjacent GND2 pins with 0.1 μF capacitors. lower jitter, and quieter operation with refresh disabled. 18 DOUT4− Inverted Differential Output 4. 19 DOUT4+ Noninverted Differential Output 4. 20 DOUT3− Inverted Differential Output 3. 21 DOUT3+ Noninverted Differential Output 3. 22 DOUT2− Inverted Differential Output 2. 23 DOUT2+ Noninverted Differential Output 2. 24 DOUT1− Inverted Differential Output 1. 25 DOUT1+ Noninverted Differential Output 1.

Figure 7. ADN4624 LFCSP Pin Configuration Table 20. ADN4624 LFCSP Pin Function Descriptions 1 DIN1+ Noninverted Differential Input 1. 2 DIN1− Inverted Differential Input 1. 3 DIN2+ Noninverted Differential Input 2. 4 DIN2− Inverted Differential Input 2. NIC Not Internally Connected. These pins are not internally connected. 7 DIN3+ Noninverted Differential Input 3. 8 DIN3− Inverted Differential Input 3. 9 DIN4+ Noninverted Differential Input 4. 10 DIN4− Inverted Differential Input 4. lower jitter, and quieter operation with refresh disabled. 13, 30 VDD1 1.8 V Power Supply for Side 1. Connect both pins externally and bypass to the adjacent GND1 pins with 0.1 μF capacitors. 14, 29 VDD2 1.8 V Power Supply for Side 2. Connect both pins externally and bypass to the adjacent GND2 pins with 0.1 μF capacitors. lower jitter, and quieter operation with refresh disabled. 17 DOUT4− Inverted Differential Output 4. 18 DOUT4+ Noninverted Differential Output 4. 19 DOUT3− Inverted Differential Output 3. 20 DOUT3+ Noninverted Differential Output 3. 23 DOUT2− Inverted Differential Output 2. 24 DOUT2+ Noninverted Differential Output 2. 25 DOUT1− Inverted Differential Output 1. 26 DOUT1+ Noninverted Differential Output 1.

signal chains and isolation of other signals such as CML. driver outputs the same state as the input. these input and output combinations. isolated LVDS buffer input state. (including the fail-safe output state, if applicable). within 1 µs by the refresh pulses. differential voltage (logic high). guaranteed common-mode transient immunity specification. state), as shown in Table 21. Table 21. Input and Output Operation

Data Sheet ADN4622/ADN4624 APPLICATIONS INFORMATION analog.com Rev. B | 22 of 27 PCB LAYOUT The ADN4622/ADN4624 can operate with high-speed LVDS signals up to 1.25 GHz clock, or 2.5 Gbps nonreturn to zero (NRZ) data. When operating with such high frequencies, apply best practices for the LVDS trace layout and termination. Place a 100 Ω termination resistor as close as possible to the receiver, across the DINx+ and DINx− pins. Controlled impedance traces (100 Ω differential) are needed on LVDS signal lines for full signal integrity, reduced system jitter, and for minimizing electromagnetic interference (EMI) from the PCB. Trace widths, lateral distance within each pair, and distance to the ground plane underneath all must be chosen appropriately. Via fencing to the PCB ground between pairs is also a best practice to minimize crosstalk between adjacent pairs. The ADN4624 has passed EN 55032 Class B emissions limits with- out extra considerations required for the isolator when operating with up to 2 Gbps PRBS data. When isolating at higher data rates or for high-speed clocks, specific PCB layout measures can be required to reduce dipole antenna effects from the isolation gap and provide sufficient margin below Class B emissions limits. The ADN4622 has passed EN 55032 Class B emissions limits when operating with up to 900 Mbps PRBS data, using a high-speed PCB design with an embedded PCB stitching capacitor (constructed by overlapping internal PCB Layer 2 and Layer 3 under the area of the isolator). The best practice for high-speed PCB design avoids emissions from traces with high-speed LVDS signals. Special care is recom- mended for off board connections, where switching transients from high-speed LVDS signals (and clocks in particular) can conduct onto cabling, resulting in radiated emissions. Use common-mode chokes, ferrites, or other filters as appropriate at LVDS connectors and power supplies, as well as cable shield or PCB ground connec- tions to earth or chassis. The ADN4622/ADN4624 require appropriate decoupling of the VDDx pins with 100 nF capacitors. Power supplies must also have appropriate filtering to avoid possible radiated emissions due to high-frequency switching noise. APPLICATION EXAMPLES High-speed LVDS interfaces for the analog front end (AFE), pro- cessor to processor serial communication, or video and imaging data can be isolated using the ADN4622/ADN4624 between com- ponents, between boards, or at a cable interface. The ADN4622/ADN4624 provides the galvanic isolation required for robust external ports, and the low jitter and high drive strength of the device allow communication along short cable runs of a few meters. High common-mode immunity ensures communication integrity even in harsh, noisy environments, and isolation can pro- tect against electromagnetic compatibility (EMC) transients up to ±8 kVPEAK, such as ESD, electrical fast transient (EFT), and surge. Standard LVDS inputs and outputs allow simple integration into high-speed signal chains using field-programmable gate arrays (FPGAs), redrivers, or coupling networks to interface to CML and other physical layers. Isolated AFE applications provide an example of the ADN4622/ ADN4624 isolating an LVDS interface between components. The ADN4624 can isolate four channels simultaneously, which suits the isolation of high-bandwidth measurement data from analog-to-digi- tal converters (ADCs) with parallel LVDS outputs, and the ADN4622 can isolate two LVDS channels in each direction, which suits the isolation of the ADCs relying on echoed clocks. Both can alter- natively be used with serialization and deserialization (SERDES) applications using FPGAs to aggregate large arrays of CMOS inputs or outputs through the 2.5 Gbps isolation channels. The ADN4622/ADN4624 additive phase jitter is sufficiently low that it does not affect the ADC performance even when isolating the sam- ple clock. In addition, implementing the galvanic isolation improves ADC performance by removing digital and power-supply noise from the FPGA and application-specific IC (ASIC) circuit. PCB to PCB connections and even cable interfaces can leverage LVDS signaling for high bandwidth links with low-latency synchro- nous data transfer. Serialized Gigabit Ethernet connections can be isolated to robustly cascade Ethernet or multiprotocol switches for industrial controller communication modules. The ADN4622 with two LVDS channels in each direction can isolate the 1.25 Gbps transmit and receive signals for two ports at each Gigabit Ethernet switch. The propagation delay of just over a couple of nanoseconds provides the low latency needed for industrial automation and process control. The ADN4624 can isolate a range of video and imaging protocols, including protocols that use CML rather than LVDS for the physical layer. One example is High-Definition Multimedia Interface (HDMI), where AC coupling and biasing and termination resistor networks are used, as shown in Figure 40 to convert between CML (used by the transition minimized differential signaling (TMDS) data and clock lanes) and the LVDS levels required by the ADN4624. Addi- tional Analog Devices isolator components, such as the ADuM2250 and ADuM2251 I2C isolators, can be used to isolate control signals and power (ADuM6421A and ADuM6028 isoPower integrated, iso- lated DC-DC converter). This circuit supports resolutions up to 1080p. Other coupling networks, processing nodes, and translation circuits can use the ADN4624 as part of an overall signal chain to iso- late MIPI CSI-2, DisplayPort, and LVDS-based protocols such as FPD-Link. Use of an FPGA or an application-specific integrated circuit (ASIC) serializer/deserializer (SERDES) expands bandwidth through multiple ADN4624 devices to support 1080p or 4K video resolutions, providing an alternative to short reach fiber links.

Figure 40. Example Isolated Video Interface (HDMI) Using the ADN4624 mode of operation for these products. dβ is the change in magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. external magnetic flux density is calculated as shown in Figure 41.

voltage determines the product lifetime. VRMS is the total RMS working voltage. VAC RMS is the time varying portion of the working voltage. VDC is the DC offset of the working voltage. other side of the isolation barrier. The isolator material is polyimide. required by a system standard. can differ for specific system level standards. Figure 43. Critical Voltage Example

Data Sheet ADN4622/ADN4624 OUTLINE DIMENSIONS ©2021-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. B | 27 of 27 EVALUATION BOARDS Model1 Description EVAL-ADN4622EB1Z ADN4622 SOIC_W_FP Evaluation Board EVAL-ADN4624EB1Z ADN4624 SOIC_W_FP Evaluation Board 1 Z = RoHS Compliant Part.