ADN4612

ADN4612_V01 AD | Alldatasheet

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Technical content

11.3 Gbps, 12 × 12 Digital

Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

DC to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at 10.3125 Gbps Compensates 15 inches of FR408 at 11.3 Gbps 6-tap programmable transmit feedforward equalization (FFE) Compensates 15 inches of FR408 at 10.3125 Gbps Compensates 10 inches of FR408 at 11.3 Gbps Low power 150 mW per channel at 2.5 V (outputs enabled) 12 × 12, fully differential, nonblocking array Double rank connection programming 2-pin selectable connection maps Per lane lost of signal (LOS) detection Flexible output termination supply range (1.8 V to 3.3 V) DC- or ac-coupled differential CML inputs and outputs Programmable CML output levels Load from EEPROM for automatic power-on ready operation Per lane input and output P/N pair inversion for routing ease 50 Ω on-chip input/output termination Supports 64-bit/66-bit, scrambled or not coded NRZ data up to 11.3 Gbps Serial (I2C or SPI slave) control interface 88-lead LFCSP , 12 mm × 12 mm, Pb-free package −40°C to +85°C operating temperature range

APPLICATIONS

Fiber optic network switching 10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap XLAUI/CAUI (802.3ba) SONET OC-192/STM-64x 1×, 2×, 4×, 8×, and 10× Fibre Channel FUNCTIONAL BLOCK DIAGRAM IP11 TO IP0 VCCDVCC VEE VTTIE, VTTIW IN11 TO IN0 OP11 TO OP0 VTTON, VTTOS ON11 TO ON0 12 × 12 SWITCH MATRIX ADN4612 Tx CONTROL 6-TAP FFE OUTPUT LEVEL PRE- EMPHASIS Tx SERIAL INTERFACE CONTROL LOGIC SPI/I2C SCK/SCL SDO/SDA SDI/I2C_A1 RESET MAP1, MAP0 EEPROM UPDATE XPT CONTROL CONNECTIVITY MAP (A/B/C/D) SELECT Rx CONTROL EQUALIZATION SIGNAL DETECT LOS_IRQ CS/I2C_A0 EQ Rx 11020-001 Figure 1. GENERAL DESCRIPTION The ADN4612 is a 12 × 12 asynchronous, protocol agnostic, digital crosspoint switch with 12 differential PECL-/CML-compatible inputs and 12 differential CML outputs. The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling with data rates of up to 11.3 Gbps per port. Each port provides programmable input equalization, loss of signal (LOS) detection, programmable output swing, and output preemphasis/deemphasis. The ADN4612 nonblocking switch core implements a 12 × 12 crossbar and supports independent channel switching through the serial control interface. The ADN4612 has low latency and very low channel-to-channel skew. The ADN4612 is packaged in an 88-lead LFCSP package and operates from −40°C to +85°C.

Rev. C | Page 2 of 76 TABLE OF CONTENTS

Rev. C | Page 3 of 76 Rx 0 to Rx 5 Active and Passive Equalization Control Rx 6 to Rx 11 Active and Passive Equalization Control Rx 11 to Rx 6 LOS Assert and Deassert Level Control

REVISION HISTORY

5/2016—Rev. B. to Rev. C 1/2016—Rev. A to Rev. B 10/2013—Revision A: Initial Version

Rev. C | Page 4 of 76 SPECIFICATIONS VCC = VTTO1 = 2.5 V , VTTI 2 = V1P8 = DVCC = 1.8 V , VEE = 0 V, RL = 50 Ω, data rate = 11.3 Gbps, data pattern = PRBS 15, ac-coupled inputs and outputs, differential input swing = 800 mV p-p, EQ setting = 0x12,3 PE boost = 1.94 dB,4 unless otherwise noted. INPUT/OUTPUT SPECIFICATIONS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Data Rate (NRZ) DC 11.3 Gbps Deterministic Jitter (No Channel) Data rate = 10.3125 Gbps 11 ps p-p Data rate = 11.3 Gbps 14 ps p-p Random Jitter (No Channel) 0.5 ps rms Residual Deterministic Jitter with Receive Equalization Input trace = 25-inch FR408, data rate = 10.3125 Gbps, EQ setting = 0x94 0.25 UI Input trace = 15-inch FR408, data rate = 11.3 Gbps, EQ setting = 0x72 0.25 UI Residual Deterministic Jitter with Transmit Preemphasis Output trace = 15-inch FR408, data rate = 10.3125 Gbps, PE boost = 5.46 dB 0.24 UI Output trace = 10-inch FR408, data rate = 11.3 Gbps, PE boost = 6.02 dB 0.31 UI Propagation Delay 50% input to 50% output (maximum EQ) 520 ps Lane-to-Lane Skew Signal path and switch architecture is balanced and symmetric (maximum EQ) ±40 ps Switching Time 50% logic switching to 50% output data5 10 ns Output Rise/Fall Time 20% to 80%, test pattern = 0000000011111111 44 ps INPUT CHARACTERISTICS Differential Input Voltage Swing VICM6 = 1.8 V, VCC = VMIN to VMAX, TA = TMIN to TMAX <200 2000 mV p-p diff Input Voltage Range Single-ended absolute voltage level, VIL minimum 1.0 V Single-ended absolute voltage level, VIH maximum VCC + 0.3 V Differential Input Return Loss (SDD11) At 2.125 GHz −24 dB At 5.5 GHz −10 dB OUTPUT CHARACTERISTICS Output Voltage Swing Differential; PE boost = 0 dB; default output level, at dc 660 780 936 mV p-p diff Output Voltage Range Single-ended absolute voltage level, VOL VCC − 1.2 V Single-ended absolute voltage level, VOH VTTO1 V Output Voltage Setting Resolution Differential absolute voltage level minimum step size, Tx driver resolution bits = 11b (divide by 8) 12.5 mV p-p diff Per Port Output Current PE boost = 0 dB, default output level 16 mA Differential Output Return Loss (SDD22) At 2.125 GHz −20 dB At 5.5 GHz −9 dB TERMINATION CHARACTERISTICS Resistance Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX 90 100 110 Ω LOS CHARACTERISTICS Assert Level Programmable; LOS_ASSERT = 0x2 74 mV p-p diff Deassert Level Programmable; LOS_DEASSERT = 0x6 133 mV p-p diff LOS-to-Output Squelch Time from active signal to idle 1.1 ns LOS-to-Output Enable Time from idle to active signal 31 ns 1 VTTO is a generic variable that describes both VTTON and VTTOS. VTTON and VTTOS are independent voltages that are not required to equal each other. 2 VTTI is a generic variable that describes both VTTIE and VTTIW. VTTIE and VTTIW are independent voltages that are not required to equal each other. 3 Default EQ setting is used to compensate for loss of test fixture. 4 Default PE setting is used to compensate for loss of test fixture. 5 50% logic level high-to-low transition of the UPDATE toggle pin or 50 % logic level transition of the MAP1 and MAP0 pins while the UPDATE pin is held at logic low. 6 VICM is the input common-mode voltage.

Rev. C | Page 5 of 76 POWER SUPPLY AND THERMAL SPECIFICATIONS Table 2. Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY OPERATING RANGE VEE = 0 V VCC 2.25 2.5 2.75 V DVCC 1.6 1.8 2.0 V VCC1P8 1.6 1.8 2.0 V VTTI 1 1.6 1.8 2.752 V VTTO3 1.64 2.5 3.6 V POWER SUPPLY NOISE TOLERANCE VCC 10 Hz to 6.25 GHz 100 mV p-p DVCC 10 Hz to 100 MHz 100 mV p-p VCC1P8 10 Hz to 100 MHz 25 mV p-p VTTI1 10 Hz to 6.25 GHz 100 mV p-p VTTO3 10 Hz to 6.25 GHz 100 mV p-p SUPPLY CURRENT ICC VCC = 2.5 V Default, all outputs disabled 120 140 mA All outputs and main tap enabled, single driver (D0) enabled 391 430 mA All outputs and main tap enabled, two drivers (D0, D1) enabled 537 590 mA All outputs and main tap enabled, three drivers (D0 to D2) enabled 684 760 mA All outputs and main tap and first post tap (D0 to D3) enabled 829 920 mA All outputs, precursor, main tap, and first post tap (PC, D0 to D3) enabled 944 1070 mA ITTO5 VTTO = 2.5 V Default, all outputs disabled 0 <1 mA All outputs enabled, 8 mA output current per lane 96 106 mA All outputs enabled, 16 mA output current per lane 192 206 mA All outputs enabled, 24 mA output current per lane 287 314 mA All outputs enabled, 32 mA output current per lane 384 416 mA ITTI6 0 mA IDVCC 8 12 mA IVCC1P8 Default, all outputs disabled 7 8 mA All outputs main tap enabled 40 43 mA THERMAL CHARACTERISTICS Operating Temperature Range −40 +85 °C θJA Still air; JEDEC 4-layer test board, exposed pad soldered 24.0 °C/W θJC Still air; thermal resistance through exposed pad 1.7 °C/W Maximum Junction Temperature 125 °C 1 VTTI is a generic variable that describes both VTTIE and VTTIW. VTTIE and VTTIW are independent voltages that are not required to equal each other. 2 It is recommended that VTTI ≤ VCC to meet the input compliance. 3 VTTO is a generic variable that describes both VTTON and VTTOS. VTTON and VTTOS are independent voltages that are not required to equal each other. 4 The single-ended absolute voltage level, VOL, must be ≤VCC − 1.2 V when operating VTTO at the minimum boundary of the supply range. 5 ITTO is a generic variable that describes both ITTON and ITTOS. ITTON and ITTOS are independent currents that are not required to equal each other. 6 ITTI is a generic variable that describes both ITTIE and ITTIW. ITTIE and ITTIW are independent currents that are not required to equal each other.

1 Detailed functionality of the I2C interface is described in the I2C Serial Control Interface section. 2 SCL is the I2C serial clock function of the SCK/SCL pin. 3 SDA is the I2C serial data function of the SDO/SDA pin. Figure 2. I2C Timing Diagram

1 Detailed functionality of the SPI interface is described in the SPI Serial Control Interface section. 2 SCK is the SPI serial clock function of the SCK/SCL pin. 3 SDO is the SPI serial data function of the SDO/SDA pin. 4 SDI is the SPI serial data function of the SDI/I2C_A1 pin. 5 CS is the SPI chip select function of the CS/I2C_A0 pin.

1. SDI IS THE SPI SERIAL DATA FUNCTION OF THE SDI/I2C_A1 PIN.
2. SDO IS THE SPI SERIAL DATA FUNCTION OF THE SDO/SDA PIN.

Figure 3. SPI Timing Diagram

1 Detailed functionality of this interface is described in the Load from Memory section. Figure 4. Load from EEPROM Timing Diagram

Figure 5. RESET Timing Diagram

resistance through the exposed pad. Table 9. Thermal Resistance

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE ELECTRICALLY CONNECTED TO VEE.

59 IP10

60 IN10

61 VEE

62 IP11

63 IN11

64 VTTIE

65 CS/I2C_A0

66 SDI/I2C_A1

79 OP9

80 ON9

81 VCC

82 OP10

83 ON10

84 VEE

85 OP11

86 ON11

87 VTTON

88 VCC1P8

Figure 6. Pin Configuration Table 10. Pin Function Descriptions 88 VCC1P8 Power Analog 1.8 V Reference Supply. 68 DVCC Power Digital Power Supply. 9, 18 VTTIW Power Westside Input Termination Supplies. 55, 64 VTTIE Power Eastside Input Termination Supplies. 69, 87 VTTON Power Northside Output Termination Supplies. 23, 41 VTTOS Power Southside Output Termination Supplies. 19 EEPROM Control Load from EEPROM (Active Low). 20 LOS_IRQ Control Loss of Signal Detect Interrupt Request Output (Active Low). 21 MAP0 Control Map Select LSB. 22 MAP1 Control Map Select MSB. 43 SCK/SCL Control SPI Serial Clock (SCK)/I2C Serial Clock (SCL). This is a multifunction pin. 44 SDO/SDA Control SPI Serial Data Output (SDO)/I2C Serial Data (SDA). This is a multifunction pin. 45 SPI/I2C Control SPI Mode Select (SPI)/I2C Mode Select (I2C). This is a multifunction pin. 46 RESET Control Reset (Active Low). 65 CS/I2C_A0 Control SPI Chip Select, Active Low (CS)/I2C Address LSB (I2C_A0). This is a multifunction pin. 66 SDI/I2C_A1 Control SPI Serial Data Input (SDI)/I2C Address MSB (I2C_A1). This is a multifunction pin. 67 UPDATE Control Switch Configuration Update Strobe (Active Low). 2 IN0 I High Speed Input Complement. 5 IN1 I High Speed Input Complement. 8 IN2 I High Speed Input Complement. 11 IN3 I High Speed Input Complement.

Rev. C | Page 12 of 76 Pin No. Mnemonic Type Description 13 IP4 I High Speed Input. 14 IN4 I High Speed Input Complement. 16 IP5 I High Speed Input. 17 IN5 I High Speed Input Complement. 47 IP6 I High Speed Input. 48 IN6 I High Speed Input Complement. 50 IP7 I High Speed Input. 51 IN7 I High Speed Input Complement. 53 IP8 I High Speed Input. 54 IN8 I High Speed Input Complement. 56 IP9 I High Speed Input. 57 IN9 I High Speed Input Complement. 59 IP10 I High Speed Input. 60 IN10 I High Speed Input Complement. 62 IP11 I High Speed Input. 63 IN11 I High Speed Input Complement. 24 OP0 O High Speed Output. 25 ON0 O High Speed Output Complement. 27 OP1 O High Speed Output. 28 ON1 O High Speed Output Complement. 30 OP2 O High Speed Output. 31 ON2 O High Speed Output Complement. 33 OP3 O High Speed Output. 34 ON3 O High Speed Output Complement. 36 OP4 O High Speed Output. 37 ON4 O High Speed Output Complement. 39 OP5 O High Speed Output. 40 ON5 O High Speed Output Complement. 70 OP6 O High Speed Output. 71 ON6 O High Speed Output Complement. 73 OP7 O High Speed Output. 74 ON7 O High Speed Output Complement. 76 OP8 O High Speed Output. 77 ON8 O High Speed Output Complement. 79 OP9 O High Speed Output. 80 ON9 O High Speed Output Complement. 82 OP10 O High Speed Output. 83 ON10 O High Speed Output Complement. 85 OP11 O High Speed Output. 86 ON11 O High Speed Output Complement. EP Exposed Pad. The exposed pad on the bottom of the package must be electrically connected to VEE.

0 INCHES

10 INCHES

15 INCHES

20 INCHES

25 INCHES

Figure 13. Deterministic Jitter vs. EQ Code in Hexadecimal for Various Input

6 INCHES

Figure 14. S21 Test Traces Figure 15. Rise/Fall Time vs. Temperature Figure 16. Deterministic Jitter vs. EQ Code in Hexadecimal for Various Input Figure 17. Return Loss (SDD11/SDD22) Figure 18. Random Jitter Histogram

Figure 19. Deterministic Jitter vs. Preemphasis for Various Output FR408 Figure 20. Deterministic Jitter vs. Differential Input Swing Figure 21. Deterministic Jitter vs. Output Termination Voltage (VTTO) Figure 22. Deterministic Jitter vs. Preemphasis for Various Output FR408 Figure 23. Deterministic Jitter vs. Input Common-Mode Voltage Figure 24. Propagation Delay vs. Core Supply Voltage (VCC)

Figure 47. Standard Test Circuit

20 INCHES, 25 INCHES

Figure 48. Equalization Test Circuit

15 INCHES, 20 INCHES

Figure 49. Preemphasis Test Circuit

and output level programming capabilities (see Figure 50). Figure 50. Block Diagram and postcursor equalization. coupled input/output configurations. eliminating the need for board level crossovers. protocols, selected by using the SPI/I2C dedicated control pin. and alleviates system controller overhead. Table 11. Serial Interface Pin Control

19 EEPROM Load from EEPROM (active low) Load from EEPROM (active low)

20 LOS_IRQ Loss of signal detect interrupt (active low) Loss of signal detect interrupt (active low)

21 MAP0 XPT map select (LSB) XPT map select (LSB)

22 MAP1 XPT map select (MSB) XPT map select (MSB)

43 SCK/SCL I2C serial clock SPI serial clock

44 SDO/SDA I2C serial data SPI serial data output

45 SPI/I2C I2C mode select SPI mode select

46 RESET Device register reset (active low) Device register reset (active low)

65 CS/I2C_A0 I2C address (LSB) SPI chip select

66 SDI/I2C_A1 I2C address (MSB) SPI serial data input

67 UPDATE XPT update strobe (active low) XPT update strobe (active low)

which is found in the input characteristics section in Table 1. VIH value listed in Table 1. proper input compliance, VICM + VINPP-SE/2 < VCC + 0.3 V. Figure 51. Simplified Input Circuit the equalizer settings for Receiver Input 6 to Receiver Input 11. four MSBs program the passive equalizer (EQP) settings. Figure 52. Sample Test Trace Attenuation Table 12. Recommended Equalizer Settings

5.65 GHz (dB)

• For the Receiver Input 5 to Receiver Input 0 enable control, write to Register Address 0x86.
• For the Receiver Input 11 to Receiver Input 6 enable control, write to Register Address 0x96.
• For the Receiver Input 5 to Receiver Input 0 equalizer enable, write to Register Address 0x87.
• For the Receiver Input 11 to Receiver Input 6 equalizer enable, write to Register Address 0x97. For applications with very short input traces, it may be desirable to disable the equalizer; otherwise, it is recommended that the receiver equalizer circuits be enabled. Offset Calibration Circuit The ADN4612 receivers incorporate an offset calibration circuit to minimize offsets in the receiver architecture, thereby reducing the amount of duty cycle distortion (DCD) contribution to residual deterministic jitter. The offset calibration circuit operates on dc-balanced data streams only. The offset calibration circuit is disabled for all receiver inputs by default. Enable the offset calibration circuit by writing a Logic 1 to the appropriate bit location, as follows:
• For the Receiver Input 5 to Receiver Input 0 offset calibration enable, write to Register Address 0xA0.
• For the Receiver Input 11 to Receiver Input 6 offset calibration enable, write to Register Address 0xA8. Loss of Signal (LOS) Detect Each receiver includes a low power, LOS detector. The loss of signal circuit monitors the received data stream and generates a system interrupt when the received signal amplitude falls below the LOS assert level for an interval that is longer than the LOS delay setting. When the receiver detects a LOS event, it squelches the associated transmitter, lowering the output current to submicro- amps. This prevents the high gain, wide bandwidth signal path from turning low level system noise on an undriven input pair into a source of hostile crosstalk at the transmitter. The squelch feature is disabled by default and can be enabled by writing a Logic 1 to the LSB (Bit 0) of Register Address 0x05. The LOS detector circuits are also disabled by default and can be enabled on a per input basis by writing a Logic 1 to the appropriate bit locations, as follows:
• For the Receiver Input 5 to Receiver Input 0 LOS detector enable, write to Register Address 0x88.
• For the Receiver Input 11 to Receiver Input 6 LOS detector enable, write to Register Address 0x98. When the received signal amplitude exceeds the LOS deassert level, the lane is enabled. The LOS assert and deassert levels are configured for two groups of six inputs each. The LOS assert and deassert levels for Receiver Input 5 to Receiver Input 0 are programmable using Register Address 0x8E, and Receiver Input 11 to Receiver Input 6 are programmable using Register Address 0x9E. To ensure proper LOS operation, the LOS deassert threshold level cannot be set lower than the LOS assert threshold level. The LOS delay settings are programmable on a per input basis, using the Rx LOS time control registers (Register Address 0x89, Register Address 0x8A, Register Address 0x8B, Register Address 0x99, Register Address 0x9A, and Register Address 0x9B). The LOS delay time settings, together with the assert and deassert threshold levels, are listed in Table 13.

Table 13. LOS Assert/Deassert Levels and Delay Settings low output that allows multiple LOS_IRQ signals to be wire-O R’e d. logical NOR of all LOS sticky status bits for all enabled receivers. Input 11 to Receiver Input 6, using Register Address 0x9F. accessed using Register Address 0x8D and Register Address 0x9D. sticky bit register addresses.

the crosspoint, and the first rank registers contain the next state. indicate which of the 12 inputs are connected to a given output. UPDATE pin low causes the second rank to become transparent. located from Register Address 0xB8 to Register Address 0xBD. register (Register Address 0xDE). Table 14. Map Select Pin Control the first rank of latches in Map A, Map B, Map C, or Map D. Transmitter Output 0 to Transmitter Output 11.

11 INPUTS

Figure 53. Crosspoint Connection Map Block Diagram

pull to VTTO. All transmitters are disabled by default. Table 16. Transmitter Disable/Enable Control

0 Disable (default)

1 Enable

Table 17. Signal Path Polarity (Swap Sign) Control

0 Noninverting (default)

1 Inverting

driver elements are enabled by default. a bit setting of 11b to the appropriate Tx driver enable register. a bit setting of 00b to the appropriate Tx driver enable register. Table 18. Driver Enable/Disable Control

00 Full disable; both driver and predriver are off

11 Full enable; both driver and predriver are on

Table 19. Output Level Settings

of the corresponding values of the channel impulse response. values shown at each sample point.

1. Choose a main Tap 0 value (D0 + D1). For this example,

a main tap value of 16 mA is selected (a0).

1. Normalize the tap coefficient weights to the main tap

driver tap value setting of −0.25 mA = (16 mA × −0.01562).

1. Repeat this process for each postcursor tap that is required

to cancel out the effects of the channel. The theoretical example results are summarized in Table 21. Table 21. Summary of Tap Coefficient Example

Table 23. Preemphasis Settings1 2 Preemphasis settings are applicable to both ac-coupled and dc-coupled applications. 4 Preemphasis settings require the VTTON or VTTOS supply of 3.3 V to meet output compliance (see the Output Compliance section). Table 24. Deemphasis Settings1 2 Deemphasis settings are applicable to both ac-coupled and dc-coupled applications.

Figure 62. Transmit Gain vs. Frequency for Alternate First Postcursor Taps Table 25. Alternate First Postcursor Tap Table the output termination resistors. single-ended absolute output low voltage, as specified in Table 1.

2.5 V to illustrate practical challenges of reducing the supply

Table 26. Output Compliance 1 A blank column heading indicates that the values listed are independent of the VTTO level. 2 See Table 22 for symbol definitions.

greater than the minimum VOL limit of 1.3 V (VOL = VCC − 1.2 V).

3.3 V shifts the swing levels above the minimum VOL limit by the

voltage range specification. automatically loaded using the I2C bus. Figure 63. Load from Memory Block Diagram the RESET pin settles to a logic high. device address to ensure proper device communication. The ADN4612 reads only the first 225 bytes of the EEPROM. reads back and compares it to the checksum in the EEPROM. EEPROM status register (Register Address 0xEF). to the device (see Table 6 for EEPROM timing specifications). initiation of a SPI read/write command (see Table 5).

given ADN4612 device (see Table 28). Table 28. I2C Device and EEPROM Page Address memory to configure four ADN4612 devices. Table 29. EEPROM Memory Allocation for Multiple ADN4612 Devices

001 ADN4612 Device 1 register data for Register Address 0x1

225 EEPROM checksum for ADN4612 Device 1

001 ADN4612 Device 2 register data for Register Address 0x1

225 EEPROM checksum for ADN4612 Device 2

001 ADN4612 Device 3 register data for Register Address 0x1

225 EEPROM checksum for ADN4612 Device 3

001 ADN4612 Device 4 register data for Register Address 0x1

225 EEPROM checksum for ADN4612 Device 4

• To indicate the beginning or continuation of a transfer, the SDA pin is driven low while the SCL pin is high.
• To indicate the end of a transfer, the SDA line is driven high while the SCL line is high. Therefore, it is important to control the SCL clock to toggle only when the SDA line is stable unless indicating a start, repeated start, or stop condition. To establish I2C communication with the ADN4612, the I2C address lines (I2C_A1 and I2C_A0) must be configured to the user assigned I2C device address, as shown in Table 30.

Table 30. Example of I2C Device Address Assignment

1. Send a start condition (while holding the SCL line high

and pulling the SDA line low).

1. Send the ADN4612 device address (seven bits), whose bits

(SDI/I2C_A1 and CS/I2C_A0 pins). This transfer is MSB first.

1. Send the write indicator bit, which is set to 0.
2. Wait for the ADN4612 to acknowledge (ACK) the request.
3. Send the register address (eight bits) to which the data is to

be written. This transfer is MSB first.

1. Wait for the ADN4612 to acknowledge (ACK) the request.
2. Send the data (eight bits) to be written to the register address

that was set in Step 5. This transfer is MSB first.

1. Wait for the ADN4612 to acknowledge (ACK) the request.
2. Perform one or more of the following steps:

I2C Data Write section) to perform a write. a read from another address. sequential register address. start condition (Step 1 and Step 9 in this example). Figure 66. I2C Write Diagram

1. Send a start condition (while holding the SCL line high

and pulling the SDA line low).

1. Send the ADN4612 device address (seven bits), whose bits
2. Send the write indicator bit, which is set to 0.
3. Wait for the ADN4612 to acknowledge (A) the request.
4. Send the register address (eight bits) from which data is to
5. Wait for the ADN4612 to acknowledge (A) the request.
6. Send a repeated start condition (while holding the SCL line

high and pulling the SDA line low).

1. Send the ADN4612 device address (seven bits) whose bits
2. Send the read indicator bit, which is set to 1.
3. Wait for the ADN4612 to acknowledge (A) the request.
4. The ADN4612 then serially transfers the data (eight bits)

held in the register indicated by the address set in Step 5.

1. Acknowledge (A) the data.
2. Perform one or more of the following:

2C Data Write section) to perform a write. a read from another address. sequential register address. then SDA is dropped while SCL is still high. Figure 67. I2C Read Diagram

source of the ADN4612 output circuit and then out through VEE. and the output current source dissipate power in the ADN4612. the formulas listed in the Output Compliance section. the ADN4612 termination resistors. conditions can yield still greater power savings. the ADN4612 transmit squelch feature. device has good sensitivity, a lower output current can be used. To lower the power dissipation, the voltage on VTTO can be lowered. that is operating at the highest programmed output current.

• VCC > DVCC
• VCC ≥ VTTI
• DVCC = VCC1P8 In applications where alternate termination voltages at VTTI and VTTO are used, adhere to these sequence guidelines. However, in a typical ac-coupled application where VCC = VTTO = 2.5 V and DVCC = VCC1P8 = VTTI = 1.8 V, the recommended power-up sequence is 2.5 V first and 1.8 V second. During power down, power down 1.8 V first, and then power down 2.5 V. Reset On initial power-up, or at any point during operation, the ADN4612 registers can be restored to the default values by strobing the RESET pin low according to the control logic timing specification in Table 7. During normal operation, the RESET pin must be pulled up to DVCC. A software reset is also available by writing 0x01 to the reset register at Register Address 0x00. This is a write only register. PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES Route the high speed differential inputs and outputs with 100 Ω controlled impedance differential transmission lines. Reference the transmission lines, either microstrip or stripline, to a solid low impedance reference plane. An example of a PCB cross-section is shown in Figure 75. The trace width (W), differential spacing (S), height above reference plane (H), and dielectric constant of the PCB material determine the characteristic impedance. To minimize crosstalk, keep adjacent channels apart by a distance that is greater than three trace widths (3W). PCB DIELECTRIC SIGNAL (MICROSTRIP) SOLDERMASK PCB DIELECTRIC PCB DIELECTRIC PCB DIELECTRIC REFERENCE PLANE REFERENCE PLANE SIGNAL (STRIPLINE) WSW H WSW 11020-278

Figure 75. Example of a PCB Cross-Section

Table 32. Register Summary

Rev. C | Page 45 of 76 Reg (Hex) Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x50 Tx6DrvCtrl0 [7:0] TX6_D0_SIGN TX6_D0_OLEV TX6_PC_SIGN TX6_PC_OLEV 0x30 RW 0x51 Tx6DrvCtrl1 [7:0] TX6_D2_SIGN TX6_D2_OLEV TX6_D1_SIGN TX6_D1_OLEV 0x33 RW 0x52 Tx6DrvCtrl2 [7:0] TX6_D4_SIGN TX6_D4_OLEV TX6_D3_SIGN TX6_D3_OLEV 0x0B RW 0x53 Tx6DrvCtrl3 [7:0] TX6_D6_SIGN TX6_D6_OLEV TX6_D5_SIGN TX6_D5_OLEV 0x00 RW 0x54 Tx6DrvEn0 [7:0] TX6_D2_DRV_EN TX6_D1_DRV_EN TX6_D0_DRV_EN TX6_PC_DRV_EN 0x3C RW 0x55 Tx6DrvEn1 [7:0] TX6_D6_DRV_EN TX6_D5_DRV_EN TX6_D4_DRV_EN TX6_D3_DRV_EN 0x00 RW 0x56 Tx6DrvRes0 [7:0] TX6_D2_RES TX6_D1_RES TX6_D0_RES TX6_PC_RES 0x00 RW 0x57 Tx6DrvRes1 [7:0] TX6_D6_RES TX6_D5_RES TX6_D4_RES TX6_D3_RES 0x54 RW 0x58 Tx7DrvCtrl0 [7:0] TX7_D0_SIGN TX7_D0_OLEV TX7_PC_SIGN TX7_PC_OLEV 0x30 RW 0x59 Tx7DrvCtrl1 [7:0] TX7_D2_SIGN TX7_D2_OLEV TX7_D1_SIGN TX7_D1_OLEV 0x33 RW 0x5A Tx7DrvCtrl2 [7:0] TX7_D4_SIGN TX7_D4_OLEV TX7_D3_SIGN TX7_D3_OLEV 0x0B RW 0x5B Tx7DrvCtrl3 [7:0] TX7_D6_SIGN TX7_D6_OLEV TX7_D5_SIGN TX7_D5_OLEV 0x00 RW 0x5C Tx7DrvEn0 [7:0] TX7_D2_DRV_EN TX7_D1_DRV_EN TX7_D0_DRV_EN TX7_PC_DRV_EN 0x3C RW 0x5D Tx7DrvEn1 [7:0] TX7_D6_DRV_EN TX7_D5_DRV_EN TX7_D4_DRV_EN TX7_D3_DRV_EN 0x00 RW 0x5E Tx7DrvRes0 [7:0] TX7_D2_RES TX7_D1_RES TX7_D0_RES TX7_PC_RES 0x00 RW 0x5F Tx7DrvRes1 [7:0] TX7_D6_RES TX7_D5_RES TX7_D4_RES TX7_D3_RES 0x54 RW 0x60 Tx8DrvCtrl0 [7:0] TX8_D0_SIGN TX8_D0_OLEV TX8_PC_SIGN TX8_PC_OLEV 0x30 RW 0x61 Tx8DrvCtrl1 [7:0] TX8_D2_SIGN TX8_D2_OLEV TX8_D1_SIGN TX8_D1_OLEV 0x33 RW 0x62 Tx8DrvCtrl2 [7:0] TX8_D4_SIGN TX8_D4_OLEV TX8_D3_SIGN TX8_D3_OLEV 0x0B RW 0x63 Tx8DrvCtrl3 [7:0] TX8_D6_SIGN TX8_D6_OLEV TX8_D5_SIGN TX8_D5_OLEV 0x00 RW 0x64 Tx8DrvEn0 [7:0] TX8_D2_DRV_EN TX8_D1_DRV_EN TX8_D0_DRV_EN TX8_PC_DRV_EN 0x3C RW 0x65 Tx8DrvEn1 [7:0] TX8_D6_DRV_EN TX8_D5_DRV_EN TX8_D4_DRV_EN TX8_D3_DRV_EN 0x00 RW 0x66 Tx8DrvRes0 [7:0] TX8_D2_RES TX8_D1_RES TX8_D0_RES TX8_PC_RES 0x00 RW 0x67 Tx8DrvRes1 [7:0] TX8_D6_RES TX8_D5_RES TX8_D4_RES TX8_D3_RES 0x54 RW 0x68 Tx9DrvCtrl0 [7:0] TX9_D0_SIGN TX9_D0_OLEV TX9_PC_SIGN TX9_PC_OLEV 0x30 RW 0x69 Tx9DrvCtrl1 [7:0] TX9_D2_SIGN TX9_D2_OLEV TX9_D1_SIGN TX9_D1_OLEV 0x33 RW 0x6A Tx9DrvCtrl2 [7:0] TX9_D4_SIGN TX9_D4_OLEV TX9_D3_SIGN TX9_D3_OLEV 0x0B RW 0x6B Tx9DrvCtrl3 [7:0] TX9_D6_SIGN TX9_D6_OLEV TX9_D5_SIGN TX9_D5_OLEV 0x00 RW 0x6C Tx9DrvEn0 [7:0] TX9_D2_DRV_EN TX9_D1_DRV_EN TX9_D0_DRV_EN TX9_PC_DRV_EN 0x3C RW 0x6D Tx9DrvEn1 [7:0] TX9_D6_DRV_EN TX9_D5_DRV_EN TX9_D4_DRV_EN TX9_D3_DRV_EN 0x00 RW 0x6E Tx9DrvRes0 [7:0] TX9_D2_RES TX9_D1_RES TX9_D0_RES TX9_PC_RES 0x00 RW 0x6F Tx9DrvRes1 [7:0] TX9_D6_RES TX9_D5_RES TX9_D4_RES TX9_D3_RES 0x54 RW 0x70 Tx10DrvCtrl0 [7:0] TX10_D0_SIGN TX10_D0_OLEV TX10_PC_SIGN TX10_PC_OLEV 0x30 RW 0x71 Tx10DrvCtrl1 [7:0] TX10_D2_SIGN TX10_D2_OLEV TX10_D1_SIGN TX10_D1_OLEV 0x33 RW 0x72 Tx10DrvCtrl2 [7:0] TX10_D4_SIGN TX10_D4_OLEV TX10_D3_SIGN TX10_D3_OLEV 0x0B RW 0x73 Tx10DrvCtrl3 [7:0] TX10_D6_SIGN TX10_D6_OLEV TX10_D5_SIGN TX10_D5_OLEV 0x00 RW 0x74 Tx10DrvEn0 [7:0] TX10_D2_DRV_EN TX10_D1_DRV_EN TX10_D0_DRV_EN TX10_PC_DRV_EN 0x3C RW 0x75 Tx10DrvEn1 [7:0] TX10_D6_DRV_EN TX10_D5_DRV_EN TX10_D4_DRV_EN TX10_D3_DRV_EN 0x00 RW 0x76 Tx10DrvRes0 [7:0] TX10_D2_RES TX10_D1_RES TX10_D0_RES TX10_PC_RES 0x00 RW 0x77 Tx10DrvRes1 [7:0] TX10_D6_RES TX10_D5_RES TX10_D4_RES TX10_D3_RES 0x54 RW 0x78 Tx11DrvCtrl0 [7:0] TX11_D0_SIGN TX11_D0_OLEV TX11_PC_SIGN TX11_PC_OLEV 0x30 RW 0x79 Tx11DrvCtrl1 [7:0] TX11_D2_SIGN TX11_D2_OLEV TX11_D1_SIGN TX11_D1_OLEV 0x33 RW 0x7A Tx11DrvCtrl2 [7:0] TX11_D4_SIGN TX11_D4_OLEV TX11_D3_SIGN TX11_D3_OLEV 0x0B RW 0x7B Tx11DrvCtrl3 [7:0] TX11_D6_SIGN TX11_D6_OLEV TX11_D5_SIGN TX11_D5_OLEV 0x00 RW 0x7C Tx11DrvEn0 [7:0] TX11_D2_DRV_EN TX11_D1_DRV_EN TX11_D0_DRV_EN TX11_PC_DRV_EN 0x3C RW 0x7D Tx11DrvEn1 [7:0] TX11_D6_DRV_EN TX11_D5_DRV_EN TX11_D4_DRV_EN TX11_D3_DRV_EN 0x00 RW 0x7E Tx11DrvRes0 [7:0] TX11_D2_RES TX11_D1_RES TX11_D0_RES TX11_PC_RES 0x00 RW 0x7F Tx11DrvRes1 [7:0] TX11_D6_RES TX11_D5_RES TX11_D4_RES TX11_D3_RES 0x54 RW 0x80 Rx0EqCtrl [7:0] RX0_EQP RX0_EQA 0x85 RW 0x81 Rx1EqCtrl [7:0] RX1_EQP RX1_EQA 0x85 RW 0x82 Rx2EqCtrl [7:0] RX2_EQP RX2_EQA 0x85 RW 0x83 Rx3EqCtrl [7:0] RX3_EQP RX3_EQA 0x85 RW 0x84 Rx4EqCtrl [7:0] RX4_EQP RX4_EQA 0x85 RW 0x85 Rx5EqCtrl [7:0] RX5_EQP RX5_EQA 0x85 RW 0x86 Rx5to0En [7:0] UNUSED_86 RX5EN RX4EN RX3EN RX2EN RX1EN RX0EN 0x00 RW 0x87 Rx5to0EqEn [7:0] UNUSED_87 RX5EQEN RX4EQEN RX3EQEN RX2EQEN RX1EQEN RX0EQEN 0x00 RW 0x88 Rx5to0LOSEn [7:0] UNUSED_88 RX5TO0LOSREFEN RX5LOSEN RX4LOSEN RX3LOSEN RX2LOSEN RX1LOSEN RX0LOSEN 0x40 RW 0x89 Rx1to0LOSTimeCtrl [7:0] RX1_LOS_TIME RX0_LOS_TIME 0x99 RW 0x8A Rx3to2LOSTimeCtrl [7:0] RX3_LOS_TIME RX2_LOS_TIME 0x99 RW 0x8B Rx5to4LOSTimeCtrl [7:0] RX5_LOS_TIME RX4_LOS_TIME 0x99 RW 0x8C Rx5to0LOSSta [7:0] UNUSED_8C RESERVED LOS5TO0STA 0x00 R 0x8D Rx5to0LOSStkySta [7:0] UNUSED_8D RESERVED LOS5TO0STKYSTA 0x00 R 0x8E Rx5to0LOSLvlCtrl [7:0] LOS_DEASSERT LOS_ASSERT 0x62 RW

Rev. C | Page 46 of 76 Reg (Hex) Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x8F Rx5to0LOSIRQEn [7:0] UNUSED_8F RX5LOSIRQEN RX4LOSIRQEN RX3LOSIRQEN RX2LOSIRQEN RX1LOSIRQEN RX0LOSIRQEN 0x00 RW 0x90 RX6EqCtrl [7:0] RX6_EQP RX6_EQA 0x85 RW 0x91 Rx7EqCtrl [7:0] RX7_EQP RX7_EQA 0x85 RW 0x92 Rx8EqCtrl [7:0] RX8_EQP RX8_EQA 0x85 RW 0x93 Rx9EqCtrl [7:0] RX9_EQP RX9_EQA 0x85 RW 0x94 Rx10EqCtrl [7:0] RX10_EQP RX10_EQA 0x85 RW 0x95 Rx11EqCtrl [7:0] RX11_EQP RX11_EQA 0x85 RW 0x96 Rx11to6En [7:0] UNUSED_96 RX11EN RX10EN RX9EN RX8EN RX7EN RX6EN 0x00 RW 0x97 Rx11to6EqEn [7:0] UNUSED_97 RX11EQEN RX10EQEN RX9EQEN RX8EQEN RX7EQEN RX6EQEN 0x00 RW 0x98 Rx11to6LOSEn [7:0] UNUSED_98 RX11TO6LOSREFEN RX11LOSEN RX10LOSEN RX9LOSEN RX8LOSEN RX7LOSEN RX6LOSEN 0x40 RW 0x99 Rx7to6LOSTimeCtrl [7:0] RX7_LOS_TIME RX6_LOS_TIME 0x99 RW 0x9A Rx9to8LOSTimeCtrl [7:0] RX9_LOS_TIME RX8_LOS_TIME 0x99 RW 0x9B Rx11to10LOSTimeCtrl [7:0] RX11_LOS_TIME RX10_LOS_TIME 0x99 RW 0x9C Rx11to6LOSSta [7:0] UNUSED_9C RESERVED LOS11TO6STA 0x00 RW 0x9D Rx11to6LOSStkySta [7:0] UNUSED_9D RESERVED LOS11TO6STKYSTA 0x00 RW 0x9E Rx11to6LOSLvlCtrl [7:0] LOS_DEASSERT LOS_ASSERT 0x62 RW 0x9F Rx11to6LOSIRQEn [7:0] UNUSED_8F RX11LOSIRQEN RX10LOSIRQEN RX9LOSIRQEN RX8LOSIRQEN RX7LOSIRQEN RX6LOSIRQEN 0x00 RW 0xA0 Rx5to0OffsetCal [7:0] UNUSED_A0 RX5OCAL RX4OCAL RX3OCAL RX2OCAL RX1OCAL RX0OCAL 0x00 RW 0xA8 Rx11to6OffsetCal [7:0] UNUSED_A8 RX11OCAL RX10OCAL RX9OCAL RX8OCAL RX7OCAL RX6OCAL 0x00 RW 0xB0 XPT_MapA_Out_1_0 [7:0] XPT_MAPA_OUT1 XPT_MAPA_OUT0 0x10 RW 0xB1 XPT_MapA_Out_3_2 [7:0] XPT_MAPA_OUT3 XPT_MAPA_OUT2 0x32 RW 0xB2 XPT_MapA_Out_5_4 [7:0] XPT_MAPA_OUT5 XPT_MAPA_OUT4 0x54 RW 0xB3 XPT_MapA_Out_7_6 [7:0] XPT_MAPA_OUT7 XPT_MAPA_OUT6 0x76 RW 0xB4 XPT_MapA_Out_9_8 [7:0] XPT_MAPA_OUT9 XPT_MAPA_OUT8 0x98 RW 0xB5 XPT_MapA_Out_11_10 [7:0] XPT_MAPA_OUT11 XPT_MAPA_OUT10 0xBA RW 0xB8 XPT_MapB_Out_1_0 [7:0] XPT_MAPB_OUT1 XPT_MAPB_OUT0 0x23 RW 0xB9 XPT_MapB_Out_3_2 [7:0] XPT_MAPB_OUT3 XPT_MAPB_OUT2 0x23 RW 0xBA XPT_MapB_Out_5_4 [7:0] XPT_MAPB_OUT5 XPT_MAPB_OUT4 0x01 RW 0xBB XPT_MapB_Out_7_6 [7:0] XPT_MAPB_OUT7 XPT_MAPB_OUT6 0x01 RW 0xBC XPT_MapB_Out_9_8 [7:0] XPT_MAPB_OUT9 XPT_MAPB_OUT8 0xAB RW 0xBD XPT_MapB_Out_11_10 [7:0] XPT_MAPB_OUT11 XPT_MAPB_OUT10 0x54 RW 0xC0 XPT_MapC_Out_1_0 [7:0] XPT_MAPC_OUT1 XPT_MAPC_OUT0 0x23 RW 0xC1 XPT_MapC_Out_3_2 [7:0] XPT_MAPC_OUT3 XPT_MAPC_OUT2 0x23 RW 0xC2 XPT_MapC_Out_5_4 [7:0] XPT_MAPC_OUT5 XPT_MAPC_OUT4 0x01 RW 0xC3 XPT_MapC_Out_7_6 [7:0] XPT_MAPC_OUT7 XPT_MAPC_OUT6 0x01 RW 0xC4 XPT_MapC_Out_9_8 [7:0] XPT_MAPC_OUT9 XPT_MAPC_OUT8 0x89 RW 0xC5 XPT_MapC_Out_11_10 [7:0] XPT_MAPC_OUT11 XPT_MAPC_OUT10 0x67 RW 0xC8 XPT_MapD_Out_1_0 [7:0] XPT_MAPD_OUT1 XPT_MAPD_OUT0 0x76 RW 0xC9 XPT_MapD_Out_3_2 [7:0] XPT_MAPD_OUT3 XPT_MAPD_OUT2 0x45 RW 0xCA XPT_MapD_Out_5_4 [7:0] XPT_MAPD_OUT5 XPT_MAPD_OUT4 0xBA RW 0xCB XPT_MapD_Out_7_6 [7:0] XPT_MAPD_OUT7 XPT_MAPD_OUT6 0x98 RW 0xCC XPT_MapD_Out_9_8 [7:0] XPT_MAPD_OUT9 XPT_MAPD_OUT8 0xAB RW 0xCD XPT_MapD_Out_11_10 [7:0] XPT_MAPD_OUT11 XPT_MAPD_OUT10 0x54 RW 0xD0 XPT_Map_Status_1_0 [7:0] XPT_MAP_STATUS1 XPT_MAP_STATUS0 R 0xD1 XPT_Map_Status_3_2 [7:0] XPT_MAP_STATUS3 XPT_MAP_STATUS2 R 0xD2 XPT_Map_Status_5_4 [7:0] XPT_MAP_STATUS5 XPT_MAP_STATUS4 R 0xD3 XPT_Map_Status_7_6 [7:0] XPT_MAP_STATUS7 XPT_MAP_STATUS6 R 0xD4 XPT_Map_Status_9_8 [7:0] XPT_MAP_STATUS9 XPT_MAP_STATUS8 R 0xD5 XPT_Map_Status_11_10 [7:0] XPT_MAP_STATUS11 XPT_MAP_STATUS10 R 0xDD Boot_from_EEPROM_ Control [7:0] UNUSED_DD IGNORE_ EEPROMB 0x00 RW 0xDE XPT_Table_Map [7:0] UNUSED_DE_1 XPT_TABLE_ SELECT_EN UNUSED_DE_0 XPT_TABLE_SELECT 0x00 RW 0xDF XPT_Update [7:0] UNUSED_DF UPDATE_XPT 0x00 W 0xEE EEPROMChecksum [7:0] BOOTCHK[7:0] 0x00 RW 0xEF EEPROMStatus [7:0] UNUSED_EF CHKSUM_ PASS CHKSUM_ FAIL EEPROM_ DONE R 0xFE RevID [7:0] REVID 0x00 R 0xFF ChipID [7:0] CHIPID 0x12 R

Software reset register. Write a Logic 1 to reset the device registers to the default state. This register is write only. Table 33. Bit Descriptions for Soft_Reset Tx 7 to Tx 0 enable control register. Write a Logic 1 to enable the transmitter output. Write a Logic 0 to disable the transmitter output. Table 34. Bit Descriptions for Tx_Enable_7to0

0 Disabled

1 Enabled

Tx 11 to Tx 8 enable control register. Write a Logic 1 to enable the transmitter output. Write a Logic 0 to disable the transmitter output. Table 35. Bit Descriptions for Tx_Enable_11to8

Tx reference enable register. Disable the unused Tx pair reference circuits to achieve further power savings. Table 36. Bit Descriptions for Tx_Ref_En Squelch control register. Enable and configure squelch mode on LOS event. Table 37. Bit Descriptions for Tx_Squelch_Control Swap sign of Rx 7 to Rx 0 inputs register. Write a Logic 1 to invert P/N lanes. Write a Logic 0 to noninvert P/N lanes. Table 38. Bit Descriptions for Rx7to0_Sign

0 Noninverting

Swap sign of Rx 11 to Rx 8 inputs register. Write a Logic 1 to invert P/N lanes. Write a Logic 0 to noninvert P/N lanes. Table 39. Bit Descriptions for Rx11to8_Sign Swap sign of Tx 7 to Tx 0 outputs register. Write a Logic 1 to invert P/N lanes. Write a Logic 0 to noninvert P/N lanes. Table 40. Bit Descriptions for Tx7to0_Sign Swap sign of Tx 11 to Tx 8 inputs register. Write a Logic 1 to invert P/N lanes. Write a Logic 0 to noninvert P/N lanes. Table 41. Bit Descriptions for Tx11to8_Sign

XPT broadcast register. Connect a single input to all outputs. Table 42. Bit Descriptions for XPT_Broadcast

0000 Connect Input 0 to All Outputs

0001 Connect Input 1 to All Outputs

0010 Connect Input 2 to All Outputs

0011 Connect Input 3 to All Outputs

0100 Connect Input 4 to All Outputs

0101 Connect Input 5 to All Outputs

0110 Connect Input 6 to All Outputs

0111 Connect Input 7 to All Outputs

1000 Connect Input 8 to All Outputs

1001 Connect Input 9 to All Outputs

1010 Connect Input 10 to All Outputs

1011 Connect Input 11 to All Outputs

Tx 0 Driver Control 0 register. Configure precursor tap (PC) and main tap (D0) output level and sign. Table 43. Bit Descriptions for Tx0DrvCtrl0

0 Positive Tap Coefficient

1 Negative Tap Coefficient

Tx0 Driver Control 1 register. Configure main tap (D1) and main tap (D2) output level and sign. Table 44. Bit Descriptions for Tx0DrvCtrl1 Tx 0 Driver Control 2 register. Configure post tap (D3) and post tap (D4) output level and sign. Table 45. Bit Descriptions for Tx0DrvCtrl2

Tx 0 Driver Control 3 register. Configure post tap (D5) and post tap (D6) output level and sign. Table 46. Bit Descriptions for Tx0DrvCtrl3 Tx 0 Driver Enable 0 register. Enable/disable driver for PC, D0, D1, and D2 taps. Write 0x3 to enable tap. Write 0x0 to disable tap. Table 47. Bit Descriptions for Tx0DrvEn0

00 Disabled

01 Not Used

10 Not Used

11 Enabled

Tx 0 Driver Enable 1 register. Enable/disable driver for D3, D4, D5, and D6 taps. Write 0x3 to enable tap. Write 0x0 to disable tap. Table 48. Bit Descriptions for Tx0DrvEn1

Tx 0 Driver Resolution 0 register. Resolution bit scales the Tx tap output level. Table 49. Bit Descriptions for Tx0DrvRes0 Tx 0 Driver Resolution 1 register. Resolution bit scales the Tx tap output level. Table 50. Bit Descriptions for Tx0DrvRes1 Refer to the Tx 0 Driver Control 0 Register section. Refer to the Tx 0 Driver Control 1 Register section. Refer to the Tx 0 Driver Control 2 Register section. Refer to the Tx 0 Driver Control 3 Register section. Refer to the Tx 0 Driver Enable 0 Register section. Refer to the Tx 0 Driver Enable 1 Register section. Refer to the Tx 0 Driver Resolution 0 Register section. Refer to the Tx 0 Driver Resolution 1 Register section.

Rev. C | Page 54 of 76 Tx 2 DRIVER CONTROL REGISTERS Tx 2 Driver Control 0 Register Address: 0x30, Reset: 0x30, Name: Tx2DrvCtrl0 Refer to the Tx 0 Driver Control 0 Register section. Tx 2 Driver Control 1 Register Address: 0x31, Reset: 0x33, Name: Tx2DrvCtrl1 Refer to the Tx 0 Driver Control 1 Register section. Tx 2 Driver Control 2 Register Address: 0x32, Reset: 0x0B, Name: Tx2DrvCtrl2 Refer to the Tx 0 Driver Control 2 Register section. Tx 2 Driver Control 3 Register Address: 0x33, Reset: 0x00, Name: Tx2DrvCtrl3 Refer to the Tx 0 Driver Control 3 Register section. Tx 2 DRIVER ENABLE REGISTERS Tx 2 Driver Enable 0 Register Address: 0x34, Reset: 0x3C, Name: Tx2DrvEn0 Refer to the Tx 0 Driver Enable 0 Register section. Tx 2 Driver Enable 1 Register Address: 0x35, Reset: 0x00, Name: Tx2DrvEn1 Refer to the Tx 0 Driver Enable 1 Register section. Tx 2 DRIVER RESOLUTION REGISTERS Tx 2 Driver Resolution 0 Register Address: 0x36, Reset: 0x00, Name: Tx2DrvRes0 Refer to the Tx 0 Driver Resolution 0 Register section. Tx 2 Driver Resolution 1 Register Address: 0x37, Reset: 0x54, Name: Tx2DrvRes1 Refer to the Tx 0 Driver Resolution 1 Register section. Tx 3 DRIVER CONTROL REGISTERS Tx 3 Driver Control 0 Register Address: 0x38, Reset: 0x30, Name: Tx3DrvCtrl0 Refer to the Tx 0 Driver Control 0 Register section. Tx 3 Driver Control 1 Register Address: 0x39, Reset: 0x33, Name: Tx3DrvCtrl1 Refer to the Tx 0 Driver Control 1 Register section. Tx 3 Driver Control 2 Register Address: 0x3A, Reset: 0x0B, Name: Tx3DrvCtrl2 Refer to the Tx 0 Driver Control 2 Register section. Tx 3 Driver Control 3 Register Address: 0x3B, Reset: 0x00, Name: Tx3DrvCtrl3 Refer to the Tx 0 Driver Control 3 Register section. Tx 3 DRIVER ENABLE REGISTERS Tx 3 Driver Enable 0 Register Address: 0x3C, Reset: 0x3C, Name: Tx3DrvEn0 Refer to the Tx 0 Driver Enable 0 Register section. Tx 3 Driver Enable 1 Register Address: 0x3D, Reset: 0x00, Name: Tx3DrvEn1 Refer to the Tx 0 Driver Enable 1 Register section. Tx 3 DRIVER RESOLUTION REGISTERS Tx 3 Driver Resolution 0 Register Address: 0x3E, Reset: 0x00, Name: Tx3DrvRes0 Refer to the Tx 0 Driver Resolution 0 Register section. Tx 3 Driver Resolution 1 Register Address: 0x3F, Reset: 0x54, Name: Tx3DrvRes1 Refer to the Tx 0 Driver Resolution 1 Register section. Tx 4 DRIVER CONTROL REGISTERS Tx 4 Driver Control 0 Register Address: 0x40, Reset: 0x30, Name: Tx4DrvCtrl0 Refer to the Tx 0 Driver Control 0 Register section. Tx 4 Driver Control 1 Register Address: 0x41, Reset: 0x33, Name: Tx4DrvCtrl1 Refer to the Tx 0 Driver Control 1 Register section. Tx 4 Driver Control 2 Register Address: 0x42, Reset: 0x0B, Name: Tx4DrvCtrl2 Refer to the Tx 0 Driver Control 2 Register section. Tx 4 Driver Control 3 Register Address: 0x43, Reset: 0x00, Name: Tx4DrvCtrl3 Refer to the Tx 0 Driver Control 3 Register section. Tx 4 DRIVER ENABLE REGISTERS Tx 4 Driver Enable 0 Register Address: 0x44, Reset: 0x3C, Name: Tx4DrvEn0 Refer to the Tx 0 Driver Enable 0 Register section. Tx 4 Driver Enable 1 Register Address: 0x45, Reset: 0x00, Name: Tx4DrvEn1 Refer to the Tx 0 Driver Enable 1 Register section.

Rev. C | Page 55 of 76 Tx 4 DRIVER RESOLUTION REGISTERS Tx 4 Driver Resolution 0 Register Address: 0x46, Reset: 0x00, Name: Tx4DrvRes0 Refer to the Tx 0 Driver Resolution 0 Register section. Tx 4 Driver Resolution 1 Register Address: 0x47, Reset: 0x54, Name: Tx4DrvRes1 Refer to the Tx 0 Driver Resolution 1 Register section. Tx 5 DRIVER CONTROL REGISTERS Tx 5 Driver Control 0 Register Address: 0x48, Reset: 0x30, Name: Tx5DrvCtrl0 Refer to the Tx 0 Driver Control 0 Register section. Tx 5 Driver Control 1 Register Address: 0x49, Reset: 0x33, Name: Tx5DrvCtrl1 Refer to the Tx 0 Driver Control 1 Register section. Tx 5 Driver Control 2 Register Address: 0x4A, Reset: 0x0B, Name: Tx5DrvCtrl2 Refer to the Tx 0 Driver Control 2 Register section. Tx 5 Driver Control 3 Register Address: 0x4B, Reset: 0x00, Name: Tx5DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 5 DRIVER ENABLE REGISTERS Tx 5 Driver Enable 0 Register Address: 0x4C, Reset: 0x3C, Name: Tx5DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 5 Driver Enable 1 Register Address: 0x4D, Reset: 0x00, Name: Tx5DrvEn1 Refer to Tx 0 Driver Enable 1 Register section. Tx 5 DRIVER RESOLUTION REGISTERS Tx 5 Driver Resolution 0 Register Address: 0x4E, Reset: 0x00, Name: Tx5DrvRes0 Refer to Tx 0 Driver Resolution 0 Register section. Tx 5 Driver Resolution 1 Register Address: 0x4F, Reset: 0x54, Name: Tx5DrvRes1 Refer to Tx 0 Driver Resolution 1 Register section. Tx 6 DRIVER CONTROL REGISTERS Tx 6 Driver Control 0 Register Address: 0x50, Reset: 0x30, Name: Tx6DrvCtrl0 Refer to Tx 0 Driver Control 0 Register section. Tx 6 Driver Control 1 Register Address: 0x51, Reset: 0x33, Name: Tx6DrvCtrl1 Refer to Tx 0 Driver Control 1 Register section. Tx 6 Driver Control 2 Register Address: 0x52, Reset: 0x0B, Name: Tx6DrvCtrl2 Refer to Tx 0 Driver Control 2 Register section. Tx 6 Driver Control 3 Register Address: 0x53, Reset: 0x00, Name: Tx6DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 6 DRIVER ENABLE REGISTERS Tx 6 Driver Enable 0 Register Address: 0x54, Reset: 0x3C, Name: Tx6DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 6 Driver Enable 1 Register Address: 0x55, Reset: 0x00, Name: Tx6DrvEn1 Refer to Tx 0 Driver Enable 1 Register section. Tx 6 DRIVER RESOLUTION REGISTERS Tx 6 Driver Resolution 0 Register Address: 0x56, Reset: 0x00, Name: Tx6DrvRes0 Refer to Tx 0 Driver Resolution 0 Register section. Tx 6 Driver Resolution 1 Register Address: 0x57, Reset: 0x54, Name: Tx6DrvRes1 Refer to Tx 0 Driver Resolution 1 Register section. Tx 7 DRIVER CONTROL REGISTERS Tx 7 Driver Control 0 Register Address: 0x58, Reset: 0x30, Name: Tx7DrvCtrl0 Refer to Tx 0 Driver Control 0 Register section. Tx 7 Driver Control 1 Register Address: 0x59, Reset: 0x33, Name: Tx7DrvCtrl1 Refer to Tx 0 Driver Control 1 Register section. Tx 7 Driver Control 2 Register Address: 0x5A, Reset: 0x0B, Name: Tx7DrvCtrl2 Refer to Tx 0 Driver Control 2 Register section. Tx 7 Driver Control 3 Register Address: 0x5B, Reset: 0x00, Name: Tx7DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 7 DRIVER ENABLE REGISTERS Tx 7 Driver Enable 0 Register Address: 0x5C, Reset: 0x3C, Name: Tx7DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 7 Driver Enable 1 Register Address: 0x5D, Reset: 0x00, Name: Tx7DrvEn1 Refer to Tx 0 Driver Enable 1 Register section.

Rev. C | Page 56 of 76 Tx 7 DRIVER RESOLUTION REGISTERS Tx 7 Driver Resolution 0 Register Address: 0x5E, Reset: 0x00, Name: Tx7DrvRes0 Refer to Tx 0 Driver Resolution 0 Register section. Tx 7 Driver Resolution 1 Register Address: 0x5F, Reset: 0x54, Name: Tx7DrvRes1 Refer to Tx 0 Driver Resolution 1 Register section. Tx 8 DRIVER CONTROL REGISTERS Tx 8 Driver Control 0 Register Address: 0x60, Reset: 0x30, Name: Tx8DrvCtrl0 Refer to Tx 0 Driver Control 0 Register section. Tx 8 Driver Control 1 Register Address: 0x61, Reset: 0x33, Name: Tx8DrvCtrl1 Refer to Tx 0 Driver Control 1 Register section. Tx 8 Driver Control 2 Register Address: 0x62, Reset: 0x0B, Name: Tx8DrvCtrl2 Refer to Tx 0 Driver Control 2 Register section. Tx 8 Driver Control 3 Register Address: 0x63, Reset: 0x00, Name: Tx8DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 8 DRIVER ENABLE REGISTERS Tx 8 Driver Enable 0 Register Address: 0x64, Reset: 0x3C, Name: Tx8DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 8 Driver Enable 1 Register Address: 0x65, Reset: 0x00, Name: Tx8DrvEn1 Refer to Tx 0 Driver Enable 1 Register section. Tx 8 DRIVER RESOLUTION REGISTERS Tx 8 Driver Resolution 0 Register Address: 0x66, Reset: 0x00, Name: Tx8DrvRes0 Refer to Tx 0 Driver Resolution 0 Register section. Tx 8 Driver Resolution 1 Register Address: 0x67, Reset: 0x54, Name: Tx8DrvRes1 Refer to Tx 0 Driver Resolution 1 Register section. Tx 9 DRIVER CONTROL REGISTERS Tx 9 Driver Control 0 Register Address: 0x68, Reset: 0x30, Name: Tx9DrvCtrl0 Refer to Tx 0 Driver Control 0 Register section. Tx 9 Driver Control 1 Register Address: 0x69, Reset: 0x33, Name: Tx9DrvCtrl1 Refer to Tx 0 Driver Control 1 Register section. Tx 9 Driver Control 2 Register Address: 0x6A, Reset: 0x0B, Name: Tx9DrvCtrl2 Refer to Tx 0 Driver Control 2 Register section. Tx 9 Driver Control 3 Register Address: 0x6B, Reset: 0x00, Name: Tx9DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 9 DRIVER ENABLE REGISTERS Tx 9 Driver Enable 0 Register Address: 0x6C, Reset: 0x3C, Name: Tx9DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 9 Driver Enable 1 Register Address: 0x6D, Reset: 0x00, Name: Tx9DrvEn1 Refer to Tx 0 Driver Enable 1 Register section. Tx 9 DRIVER RESOLUTION REGISTERS Tx 9 Driver Resolution 0 Register Address: 0x6E, Reset: 0x00, Name: Tx9DrvRes0 Refer to Tx 0 Driver Resolution 0 Register section. Tx 9 Driver Resolution 1 Register Address: 0x6F, Reset: 0x54, Name: Tx9DrvRes1 Refer to Tx 0 Driver Resolution 1 Register section. Tx 10 DRIVER CONTROL REGISTERS Tx 10 Driver Control 0 Register Address: 0x70, Reset: 0x30, Name: Tx10DrvCtrl0 Refer to Tx 0 Driver Control 0 Register section. Tx 10 Driver Control 1 Register Address: 0x71, Reset: 0x33, Name: Tx10DrvCtrl1 Refer to Tx 0 Driver Control 1 Register section. Tx 10 Driver Control 2 Register Address: 0x72, Reset: 0x0B, Name: Tx10DrvCtrl2 Refer to Tx 0 Driver Control 2 Register section. Tx 10 Driver Control 3 Register Address: 0x73, Reset: 0x00, Name: Tx10DrvCtrl3 Refer to Tx 0 Driver Control 3 Register section. Tx 10 DRIVER ENABLE REGISTERS Tx 10 Driver Enable 0 Register Address: 0x74, Reset: 0x3C, Name: Tx10DrvEn0 Refer to Tx 0 Driver Enable 0 Register section. Tx 10 Driver Enable 1 Register Address: 0x75, Reset: 0x00, Name: Tx10DrvEn1 Refer to Tx 0 Driver Enable 1 Register section.

Refer to Tx 0 Driver Resolution 0 Register section. Refer to Tx 0 Driver Resolution 1 Register section. Refer to Tx 0 Driver Control 0 Register section. Refer to Tx 0 Driver Control 1 Register section. Refer to Tx 0 Driver Control 2 Register section. Refer to Tx 0 Driver Control 3 Register section. Refer to Tx 0 Driver Enable 0 Register section. Refer to Tx 0 Driver Enable 1 Register section. Refer to Tx 0 Driver Resolution 0 Register section. Refer to Tx 0 Driver Resolution 1 Register section. boost is the addition of the boost of the two stages. Table 51. Bit Descriptions for Rx0EqCtrl

boost is the addition of the boost of the two stages. Table 52. Bit Descriptions for Rx1EqCtrl boost is the addition of the boost of the two stages. Table 53. Bit Descriptions for Rx2EqCtrl boost is the addition of the boost of the two stages. Table 54. Bit Descriptions for Rx3EqCtrl boost is the addition of the boost of the two stages. Table 55. Bit Descriptions for Rx4EqCtrl boost is the addition of the boost of the two stages. Table 56. Bit Descriptions for Rx5EqCtrl

Rx 5 to Rx 0 enable control register. Write a Logic 1 to enable the receiver input. Write a Logic 0 to disable the receiver input. Table 57. Bit Descriptions for Rx5to0En Table 58. Bit Descriptions for Rx5to0EqEn

0 Disabled (Bypassed)

Table 59. Bit Descriptions for Rx5to0LOSEn

Rx 1 and Rx 0 LOS event time control register. Controls the time delay of transmitter squelch when an LOS event is detected. Table 60. Bit Descriptions for Rx1to0LOSTimeCtrl Rx 3 and Rx 2 LOS event time control register. Controls the time delay of the transmitter squelch when an LOS event is detected. Table 61. Bit Descriptions for Rx3to2LOSTimeCtrl Rx 5 and Rx 4 LOS event time control register. Controls the time delay of the transmitter squelch when an LOS event is detected. Table 62. Bit Descriptions for Rx5to4LOSTimeCtrl

Rx 5 to Rx 0 LOS status register. Read register to determine if an active signal is detected on Rx 5 to Rx 0. Table 63. Bit Descriptions for Rx5to0LOSSta

0 LOS Deasserted; Active Signal Detected

1 LOS Asserted; Signal Not Detected

Rx 5 to Rx 0 LOS sticky status register. Read register to determine if an LOS event has been detected on Rx 5 to Rx 0. Table 64. Bit Descriptions for Rx5to0LOSStkySta

0 LOS Event Has Not Occurred

1 LOS Event Has Occurred

LOS detect programmable assert and deassert levels. Recommended setting: deassert = 6; assert = 2 (0x62). Table 65. Bit Descriptions for Rx5to0LOSLvlCtrl peak-to-peak. Always set the deassert level higher than the assert level. 300 mV in 25 mV increments. Voltage levels are differential peak-to-peak. Always set the assert level lower than the deassert level.

Rx 5 to Rx 0. The LOS IRQ control pin status is determined by the wire-O R’e d value of the Rx LOS event status of Rx 11 to Rx 0. Table 66. Bit Descriptions for Rx5to0LOSIREQEn boost is the addition of the boost of the two stages. Table 67. Bit Descriptions for RX6EqCtrl boost is the addition of the boost of the two stages. Table 68. Bit Descriptions for RX7EqCtrl boost is the addition of the boost of the two stages. Table 69. Bit Descriptions for Rx8EqCtrl

boost is the addition of the boost of the two stages. Table 70. Bit Descriptions for Rx9EqCtrl boost is the addition of the boost of the two stages. Table 71. Bit Descriptions for Rx10EqCtrl boost is the addition of the boost of the two stages. Table 72. Bit Descriptions for Rx11EqCtrl Rx 11 to Rx 6 enable control register. Write a Logic 1 to enable receiver input. Write a Logic 0 to disable receiver input. Table 73. Bit Descriptions for Rx11to6En

Rx 11 to Rx 6 receiver equalizer enable. Write a Logic 1 to enable the receiver equalizer. Write a Logic 0 to bypass the receiver equalizer. Table 74. Bit Descriptions for Rx11to6EqEn Table 75. Bit Descriptions for Rx11to6LOSEn

Rx 7 and Rx 6 LOS event time control register. Controls the time delay of transmitter squelch when an LOS event is detected. Table 76. Bit Descriptions for Rx7to6LOSTimeCtrl Rx 9 and Rx 8 LOS event time control register. Controls the time delay of transmitter squelch when an LOS event is detected. Table 77. Bit Descriptions for Rx9to8LOSTimeCtrl Rx 11 and Rx 10 LOS event time control register. Controls the time delay of transmitter squelch when an LOS event is detected. Table 78. Bit Descriptions for Rx11to10LOSTimeCtrl

Rx 11 to Rx 6 LOS status register. Read register to determine if an active signal is detected on Rx 11 to Rx 6. Table 79. Bit Descriptions for Rx11to6LOSSta when input signal is above the deassert level. Rx 11 to Rx 6 LOS sticky status register. Read register to determine if an LOS event has been detected on Rx 11 to Rx 6. Table 80. Bit Descriptions for Rx11to6LOSStkySta LOS detect programmable assert and deassert levels. Recommended setting: deassert = 6, assert = 2 (0x62). Table 81. Bit Descriptions for Rx11to6LOSLvlCtrl peak-to-peak. Always set the deassert level higher than the assert level. 300 mV in 25 mV increments. Voltage levels are differential peak-to-peak. Always set the assert level lower than the deassert level.

Rx 11 to Rx 6. The LOS IRQ control pin status is determined by the wire-OR’d value of the receiver LOS event status of Rx 11 to Rx 6. Table 82. Bit Descriptions for Rx11to6LOSIRQEn DCD calibration circuit on Rx 5 to Rx 0. Table 83. Bit Descriptions for Rx5to0OffsetCal DCD calibration circuit on Rx 11 to Rx 6. Table 84. Bit Descriptions for Rx11to6OffsetCal

XPT Map A Tx 1and XPT Map A Tx 0 lane select register. Programs the input lane connection to the Tx 1 and Tx 0 lanes. Table 85. Bit Descriptions for XPT_MapA_Out_1_0

0000 OUT[n] = Input 0

0001 OUT[n] = Input 1

0010 OUT[n] = Input 2

0011 OUT[n] = Input 3

0100 OUT[n] = Input 4

0101 OUT[n] = Input 5

0110 OUT[n] = Input 6

0111 OUT[n] = Input 7

1000 OUT[n] = Input 8

1001 OUT[n] = Input 9

1010 OUT[n] = Input 10

1011 OUT[n] = Input 11

XPT Map A Tx 3 and XPT Map A Tx 2 lane select register. Programs the input lane connection to the Tx 3 and Tx 2 lanes. Table 86. Bit Descriptions for XPT_MapA_Out_3_2 XPT Map A Tx 5 and XPT Map A Tx 4 lane select register. Programs the input lane connection to the Tx 5 and Tx 4 lanes. Table 87. Bit Descriptions for XPT_MapA_Out_5_4 XPT Map A Tx 7 and XPT Map A Tx 6 lane select register. Programs the input lane connection to the Tx 7 and Tx 6 lanes. Table 88. Bit Descriptions for XPT_MapA_Out_7_6

XPT Map A Tx 9 and XPT Map A Tx 8 lane select register. Programs the input lane connection to the Tx 9 and Tx 8 lanes. Table 89. Bit Descriptions for XPT_MapA_Out_9_8 XPT Map A Tx 11 and XPT Map A Tx 10 lane select register. Programs the input lane connection to the Tx 11 and Tx 10 lanes. Table 90. Bit Descriptions for XPT_MapA_Out_11_10 XPT Map B Tx 1 and XPT Map B Tx 0 lane select register. Programs the input lane connection to the Tx 1 and Tx 0 lanes. Table 91. Bit Descriptions for XPT_MapB_Out_1_0 XPT Map B Tx 3 and XPT Map B Tx 2 lane select register. Program input lane connection to Tx 3 and Tx 2 lanes. Table 92. Bit Descriptions for XPT_MapB_Out_3_2 XPT Map B Tx 5 and XPT Map B Tx 4 lane select register. Programs the input lane connection to the Tx 5 and Tx 4 lanes. Table 93. Bit Descriptions for XPT_MapB_Out_5_4

XPT Map B Tx 7 and XPT Map B Tx 6 lane select register. Programs the input lane connection to the Tx 7 and Tx 6 lanes. Table 94. Bit Descriptions for XPT_MapB_Out_7_6 XPT Map B Tx 9 and XPT Map B Tx 8 lane select register. Programs the input lane connection to the Tx 9 and Tx 8 lanes. Table 95. Bit Descriptions for XPT_MapB_Out_9_8 XPT Map B Tx 11 and XPT Map B Tx 10 lane select register. Programs the input lane connection to the Tx 11 and Tx 10 lanes. Table 96. Bit Descriptions for XPT_MapB_Out_11_10 XPT Map C Tx 1 and XPT Map C Tx 0 lane select register. Programs the input lane connection to the Tx 1 and Tx 0 lanes. Table 97. Bit Descriptions for XPT_MapC_Out_1_0 XPT Map C Tx 3 and XPT Map C Tx 2 lane select register. Programs the input lane connection to the Tx 3 and Tx 2 lanes. Table 98. Bit Descriptions for XPT_MapC_Out_3_2

XPT Map C Tx 5 and XPT Map C Tx 4 lane select register. Programs the input lane connection to the Tx 5 and Tx 4 lanes. Table 99. Bit Descriptions for XPT_MapC_Out_4_5 XPT Map C Tx 7 and XPT Map C Tx 6 lane select register. Programs the input lane connection to the Tx 7 and Tx 6 lanes. Table 100. Bit Descriptions for XPT_MapC_Out_7_6 XPT Map C Tx 9 and XPT Map C Tx 8 lane select register. Programs the input lane connection to the Tx 9 and Tx 8 lanes. Table 101. Bit Descriptions for XPT_MapC_Out_9_8 XPT Map C Tx 11 and XPT Map C Tx 10 lane select register. Programs the input lane connection to the Tx 11 and Tx 10 lanes. Table 102. Bit Descriptions for XPT_MapC_Out_11_10 XPT Map D Tx 1 and XPT Map D Tx 0 lane select register. Programs the input lane connection to the Tx 1 and Tx 0 lanes. Table 103. Bit Descriptions for XPT_MapD_Out_1_0

XPT Map D Tx 3 and XPT Map D Tx 2 lane select register. Programs the input lane connection to the Tx 3 and Tx 2 lanes. Table 104. Bit Descriptions for XPT_MapD_Out_3_2 XPT Map D Tx 5 and XPT Map D Tx 4 lane select register. Programs the input lane connection to the Tx 5 and Tx 4 lanes. Table 105. Bit Descriptions for XPT_MapD_Out_5_4 XPT Map D Tx 7 and XPT Map D Tx 6 lane select register. Programs the input lane connection to the Tx 7 and Tx 6 lanes. Table 106. Bit Descriptions for XPT_MapD_Out_7_6 XPT Map D Tx 9 and XPT Map D Tx 8 lane select register. Programs the input lane connection to the Tx 9 and Tx 8 lanes. Table 107. Bit Descriptions for XPT_MapD_Out_9_8 XPT Map D Tx 11 and XPT Map D Tx 10 lane select register. Programs the input lane connection to the Tx 11 and Tx 10 lanes. Table 108. Bit Descriptions for XPT_MapD_Out_11_10

XPT Map Tx 1 and XPT Map Tx 0 lane status register. Reads the current state of the XPT connectivity for the Tx 1 and Tx 0 lanes. Table 109. Bit Descriptions for XPT_Map_Status_1_0 XPT Map Tx 3 and XPT Map Tx 2 lane status register. Reads the current state of the XPT connectivity for the Tx 3 and Tx 2 lanes. Table 110. Bit Descriptions for XPT_Map_Status_3_2 XPT Map Tx 5 and XPT Map Tx 4 lane status register. Reads the current state of the XPT connectivity for the Tx 5 and Tx 4 lanes. Table 111. Bit Descriptions for XPT_Map_Status_5_4 XPT Map Tx 7 and XPT Map Tx 6 lane status register. Reads the current state of the XPT connectivity for the Tx 7 and Tx 6 lanes. Table 112. Bit Descriptions for XPT_Map_Status_7_6 XPT Map Tx 9 and XPT Map Tx 8 lane status register. Reads the current state of the XPT connectivity for the Tx 9 and Tx 8 lanes. Table 113. Bit Descriptions for XPT_Map_Status_9_8

XPT Map Tx 11 and XPT Map Tx 10 lane status register. Reads the current state of the XPT connectivity for the Tx 11 and Tx 10 lanes. Table 114. Bit Descriptions for XPT_Map_Status_11_10 Boot from EEPROM control register. Write a Logic 1 to disable the EEPROM control pin. Write a Logic 0 to enable the EEPROM control pin. Table 115. Bit Descriptions for Boot_from_EEPROM_Control 0 IGNORE_EEPROM EEPROM control pin.

0 Enable

1 Disable

XPT table selection control register. Select active XPT table map. Table 116. Bit Descriptions for XPT_Table_Map 4 XPT_TABLE_SELECT_EN XPT table select pins enable.

0 Program XPT table map from MAP1 and MAP0 control pins

1 Program XPT table map from software register

00 Map A Selected

01 Map B Selected

10 Map C Selected

11 Map D Selected

Table 117. Bit Descriptions for XPT_Update

EEPROM checksum register. Reads the computed checksum value after a load from the EEPROM cycle. Table 118. Bit Descriptions for EEPROMChecksum EEPROM status register. Checks the load from the EEPROM pass, fail, or completion status. Table 119. Bit Descriptions for EEPROMStatus Table 120. Bit Descriptions for RevID Table 121. Bit Descriptions for ChipID

0.60 MAX

Figure 79. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). registered trademarks are the property of their respective owners.