ADN4604

ADN4604 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 40

Technical content

4.25 Gbps,

16 × 16, Digital Crosspoint Switch Data Sheet ADN4604 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

DC to 4.25 Gbps per port NRZ data rate Programmable receive equalization 12 dB boost at 2 GHz Compensates 40 inches of FR4 at 4.25 Gbps Programmable transmit preemphasis/deemphasis Up to 12 dB boost at 4.25 Gbps Compensates 40 inches of FR4 at 4.25 Gbps Low power: 130 mW per channel at 3.3 V (outputs enabled) 16 × 16, fully differential, nonblocking array Double rank connection programming with dual connection maps Low jitter, typically 20 ps Flexible I/O supply range DC- or ac-coupled differential CML inputs Programmable CML output levels Per-lane input P/N pair inversion for routing ease 50 Ω on-chip I/O termination Supports 8b/10b, scrambled or uncoded NRZ data Serial (I2C slave or SPI) control interface 100-lead TQFP, Pb-free package

APPLICATIONS

Fiber optic network switching High speed serial backplane routing to OC-48 with FEC XAUI: 10GBASE-KX4 Gigabit Ethernet over backplane: 1000BASE-KX 1×, 2×, and 4× Fibre Channel InfiniBand® Digital video (HDMI, DVI, DisplayPort, 3G-/HD-/SD-SDI) Data storage networks FUNCTIONAL BLOCK DIAGRAM EQ RX TX PRE- EMPHASIS 16 × 16 SWITCH MATRIX CONNECTION MAP 0 CONNECTION MAP 1 SERIAL INTERFACE CONTROL LOGIC PER-PORT OUTPUT LEVEL SETTINGS OUTPUT LEVEL HOOKUP TABLE ADN4604 VCC VEE DVCC OP[15:0] VTTON, VTTOS ON[15:0] IP[15:0] VTTIE, VTTIW IN[15:0] I2C/SPI ADDR1/SDI SDA/SDO SCL/SCK RESET UPDATE ADDR0/CS 07934-001 Figure 1. GENERAL DESCRIPTION The ADN4604 is a 16 × 16 asynchronous, protocol agnostic, digital crosspoint switch, with 16 differential PECL-/CML- compatible inputs and 16 differential CML outputs. The ADN4604 is optimized for nonreturn-to-zero (NRZ) sig- naling with data rates of up to 4.25 Gbps per port. Each port offers a fixed level of input equalization and programmable output swing and output preemphasis. The ADN4604 nonblocking switch core implements a 16 × 16 crossbar and supports independent channel switching through the serial control interface. The ADN4604 has low latency and very low channel-to-channel skew. An I2C® or SPI interface is used to control the device and pro- vide access to advanced features, such as additional levels of preemphasis and output disable. The ADN4604 is packaged in a 100-lead TQFP package and operates from −40°C to +85°C.

Rev. A | Page 2 of 40 TABLE OF CONTENTS

REVISION HISTORY

3/13—Rev. 0 to Rev. A Changes to Switching Time Parameter and Operating Range 10/09—Revision 0: Initial Version

Rev. A | Page 3 of 40 SPECIFICATIONS ELECTRICAL SPECIFICATIONS input swing = 800 mV p-p, TA = 27°C, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Data Rate (DR) per Channel (NRZ) DC 4.25 Gbps Deterministic Jitter Data rate = 4.25 Gbps, no channel 20 ps p-p Random Jitter RMS, no channel 1 ps rms Residual Deterministic Jitter with Receive Equalization Data rate = 4.25 Gbps, 20 in. FR4, EQ boost = 12 dB 27 ps p-p Data rate = 4.25 Gbps, 30 in. FR4, EQ boost = 12 dB 43 ps p-p Data rate = 4.25 Gbps, 40 in. FR4, EQ boost = 12 dB 70 ps p-p Residual Deterministic Jitter with Transmit Preemphasis Data rate = 4.25 Gbps, 20 in. FR4, PE boost = 4.2 dB 23 ps p-p Data rate = 4.25 Gbps, 30 in. FR4, PE boost = 6 dB 25 ps p-p Data rate = 4.25 Gbps, 40 in. FR4, PE boost = 6 dB 35 ps p-p Propagation Delay Input to output, EQ boost = 12 dB 800 ps Channel-to-Channel Skew ±50 ps Switching Time Measured from VIL level of falling edge of update to 50% of output signal transition 100 ns Output Rise/Fall Time 20% to 80% 75 ps INPUT CHARACTERISTICS Differential Input Voltage Swing VICM 1 = VCC − 0.6 V; VCC = VMIN to VMAX, TA = TMIN to TMAX 200 2000 mV p-p diff Input Voltage Range Single-ended absolute voltage level, VL VEE + 1.1 V Single-ended absolute voltage level, VH VCC + 0.3 V OUTPUT CHARACTERISTICS Output Voltage Swing Differential, PE boost = 0 dB, default output level, at dc 600 800 900 mV p-p diff Output Voltage Range Single-ended absolute voltage level, VL VCC – 1.3 V Single-ended absolute voltage level, VH VCC + 0.2 V Per-Port Output Current PE boost = 0 dB, default output level 16 mA PE boost = 6 dB, default output level 32 mA TERMINATION CHARACTERISTICS Resistance Single-ended, VCC = 2.7 V to 3.6 V, VTTI = 2.2 V to 3.6 V, VTTO = 2.2 V to 3.6 V, TA = TMIN to TMAX; 44 50 56 Ω Temperature Coefficient 0.025 Ω/°C POWER SUPPLY Operating Range VCC VEE = 0 V 2.7 3.3 3.6 V DVCC VEE = 0 V 2.7 3.3 3.6 V VTTIE, VTTIW VEE = 0 V, VCC = 3.3 V 1.3 3.3 VCC + 0.3 V VTTON, VTTOS VEE = 0 V, VCC = 3.3 V 2.22 3.3 VCC + 0.3 V Supply Current Outputs disabled ICC 95 110 mA IDVCC 20 35 mA ITTIE + ITTIW + ITTON + ITTOS 0 10 mA Supply Current All outputs enabled, ac-coupled I/O, 400 mV I/O swings (800 mV p-p differential), PE boost = 0 dB, 50 Ω far-end terminations ICC 342 370 mA IDVCC 20 35 mA ITTIE + ITTIW + ITTON + ITTOS 256 280 mA Supply Current All outputs enabled, ac-coupled I/O, 400 mV I/O swings (800 mV p-p differential), PE boost = 6 dB, 50 Ω far-end terminations ICC 486 540 mA IDVCC 20 35 mA ITTIE + ITTIW + ITTON + ITTOS 512 540 mA

1 VICM is the input common-mode voltage. 2 Minimum VTTO is only applicable for a limited range of output current settings. Refer to the Power Dissipation section. Figure 2. I2C Timing Diagram Table 2. I2C Timing Specifications

Rev. A | Page 6 of 40 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VCC to VEE 3.7 V DVCC to VEE 3.7 V VTTIE, VTTIW VCC + 0.6 V VTTON, VTTOS VCC + 0.6 V Internal Power Dissipation1 4.9 W Differential Input Voltage 2.0 V Logic Input Voltage VEE – 0.3 V < VIN < VCC + 0.6 V Storage Temperature Range −65°C to +125°C Lead Temperature Range 300°C Junction Temperature 150°C 1 Internal power dissipation is for the device in free air. TA = 27°C; θJA = 24.9°C/W in still air. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

76 SCL/SCK

77 OP8

78 ON8

79 VEE

80 OP9

81 ON9

82 VTTON

83 OP10

84 ON10

85 VCC

86 OP11

87 ON11

88 VEE

89 OP12

90 ON12

91 VCC

92 OP13

93 ON13

94 VTTON

95 OP14

96 ON14

97 VEE

98 OP15

99 ON15

100 DVCC

51 ADDR0/CS

52 IP8

53 IN8

54 VCC

55 IP9

56 IN9

57 VTTIE

58 IP10

59 IN10

60 VEE

61 IP11

62 IN11

63 VCC

64 IP12

65 IN12

66 VEE

67 IP13

68 IN13

69 VTTIE

70 IP14

71 IN14

72 VCC

73 IP15

74 IN15

75 SDA/SDO

1. THE ADN4604 TQFP HAS AN EXPOSED PADDLE (EPAD) ON THE UNDERSIDE OF THE PACKAGE THAT AIDS

TO MEET THERMAL SPECIFICATIONS.

1. SDA/SCL/ADDR1/0 FOR I2C OPERATION.

SCK/SDO/SDI/CS FOR SPI OPERATION. Figure 5. Pin Configuration

Table 5. Pin Function Descriptions 2 IP0 Input High Speed Input. 3 IN0 Input High Speed Input Complement. 5 IP1 Input High Speed Input. 6 IN1 Input High Speed Input Complement. 8 IP2 Input High Speed Input. 9 IN2 Input High Speed Input Complement. 11 IP3 Input High Speed Input. 12 IN3 Input High Speed Input Complement. 14 IP4 Input High Speed Input. 15 IN4 Input High Speed Input Complement. 17 IP5 Input High Speed Input. 18 IN5 Input High Speed Input Complement. 20 IP6 Input High Speed Input. 21 IN6 Input High Speed Input Complement. 23 IP7 Input High Speed Input. 24 IN7 Input High Speed Input Complement. 26 I2C/SPI Control I2C/SPI Control Interface Selection, I2C Active Low. 27 OP0 Output High Speed Output. 28 ON0 Output High Speed Output Complement. 30 OP1 Output High Speed Output. 31 ON1 Output High Speed Output Complement. 32, 44 VTTOS Power Output Termination Supply (South). These pins are normally tied to the VTTON pins. 33 OP2 Output High Speed Output. 34 ON2 Output High Speed Output Complement. 36 OP3 Output High Speed Output. 37 ON3 Output High Speed Output Complement. 39 OP4 Output High Speed Output. 40 ON4 Output High Speed Output Complement. 42 OP5 Output High Speed Output. 43 ON5 Output High Speed Output Complement. 45 OP6 Output High Speed Output. 46 ON6 Output High Speed Output Complement. 48 OP7 Output High Speed Output. 49 ON7 Output High Speed Output Complement. 50 ADDR1/SDI Control I2C Slave Address Bit 1 (MSB) or SPI Data Input. 51 ADDR0/CS Control I2C Slave Address Bit 0 (LSB) or SPI Chip Select (Active Low). 52 IP8 Input High Speed Input. 53 IN8 Input High Speed Input Complement. 55 IP9 Input High Speed Input. 56 IN9 Input High Speed Input Complement.

Rev. A | Page 9 of 40 Pin No. Mnemonic Type Description 57, 69 VTTIE Power Input Termination Supply (East). These pins are normally tied to the VTTIW pins. 58 IP10 Input High Speed Input. 59 IN10 Input High Speed Input Complement. 61 IP11 Input High Speed Input. 62 IN11 Input High Speed Input Complement. 64 IP12 Input High Speed Input. 65 IN12 Input High Speed Input Complement. 67 IP13 Input High Speed Input. 68 IN13 Input High Speed Input Complement. 70 IP14 Input High Speed Input. 71 IN14 Input High Speed Input Complement. 73 IP15 Input High Speed Input. 74 IN15 Input High Speed Input Complement. 75 SDA/SDO Control I2C Data or SPI Data Output. 76 SCL/SCK Control I2C Clock or SPI Clock. 77 OP8 Output High Speed Output. 78 ON8 Output High Speed Output Complement. 80 OP9 Output High Speed Output. 81 ON9 Output High Speed Output Complement. 82, 94 VTTON Power Output Termination Supply (North). These pins are normally tied to the VTTOS pins. 83 OP10 Output High Speed Output. 84 ON10 Output High Speed Output Complement. 86 OP11 Output High Speed Output. 87 ON11 Output High Speed Output Complement. 89 OP12 Output High Speed Output. 90 ON12 Output High Speed Output Complement. 92 OP13 Output High Speed Output. 93 ON13 Output High Speed Output Complement. 95 OP14 Output High Speed Output. 96 ON14 Output High Speed Output Complement. 98 OP15 Output High Speed Output. 99 ON15 Output High Speed Output Complement. 100 DVCC Power Digital Positive Supply.

30 INCHES, 40 INCHES

Figure 11. Equalization Test Circuit Figure 12. 4.25 Gbps Input Eye, 20 Inch FR4 Input Channel Figure 13. 4.25 Gbps Input Eye, 40-Inch FR4 Input Channel Figure 14. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, EQ = 12 dB Figure 15. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, EQ = 12 dB

Figure 16. Preemphasis Test Circuit Figure 17. 4.25 Gbps Output Eye, 20-Inch FR4 Output Channel, PE = 0 dB Figure 18. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 0 dB Figure 19. 4.25 Gbps Output Eye, 20-Inch FR4 Input Channel, PE = 4.2 dB Figure 20. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel, PE = 6 dB

Figure 39. Block Diagram Table 6. Serial Interface Control Modes

50 ADDR1 I2C Address

51 ADDR0 I2C Address

75 SDA I2C Data SDO SPI Data

76 SCL I2C Clock SCK SPI Clock

need for board-level crossovers in the receiver channel. Figure 40. Simplified Input Circuit control bit. By default, the programmable boost is set to 12 dB. respective register bit for the corresponding channel. Table 7. Equalization Control Registers attention when switching connectivity. Table 8. Signal Path Polarity Control

0 Noninverting (default)

1 Inverting

Figure 41. The second rank registers contain the current state of the crosspoint. The first rank registers contain the next state. the XPT table select register (Address 0x81). each of the desired connections is programmed. select register (Address 0x81). map is provided in Table 18.

15 INPUTS

Figure 41. Crosspoint Connection Map Block Diagram

Table 9. XPT Control Registers

broadcast register at Address 0x18 as shown in Table 11. Note that this overwrites any data previously stored in Addresses 0x20 to 0x2F. Table 11. TX Basic Control Register 3 Reserved Reserved. Set to 0. 1 The broadcast register, Address 0x18, is write-only. and the corresponding TX Drive 0 and TX Drive 1 codes. Table 12. TX Lookup Table Registers

7 DRV EN1 0: Driver 1 disabled

7 DRV END 0: Driver D disabled

advanced settings register map is shown in Table 15. The preemphasis boost equation follows. Figure 44. Signal Level Definitions Table 13. TX Preemphasis and Output Swing Advanced 1 Symbol definitions are shown in Table 14. Table 14. Symbol Definitions

preemphasis boost settings and the corresponding TX Drive 0 and TX Drive 1 codes. Table 15. TX Advanced Control Registers

3 DRV EN0 0: Driver 0 disabled

3 DRV EN2 0: Driver 2 disabled

can reduce the overall performance. terminations are enabled by default. Figure 45. 75 Ω to 50 Ω Impedance Translator. Table 16. Termination Control Register

2 TXS_TERM Output[7:0] (South) termination control

1 RXE_TERM Input[15:8] (East) termination control

0 RXW_TERM Input[7:0] (West) termination control

repeated start, or stop condition. Table 17. I RESET pin to low according to the specification in Table 2.

1. Send a start condition (while holding the SCL line high,
2. Send the ADN4604 part address (seven bits) whose upper

transfer should be MSB first.

1. Send the write indicator bit (0).
2. Wait for the ADN4604 to acknowledge the request.
3. Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

1. Wait for the ADN4604 to acknowledge the request.
2. Send the data (eight bits) to be written to the register
3. Wait for the ADN4604 to acknowledge the request.
4. Do one or more of the following:

pull the SDA line high) and release control of the bus. with Step 2 of the write procedure to perform a write. Address 0x6D of an ADN4604 part with a part address of 0x4B. repeated start condition, Step 1 and Step 9 in this case. Figure 46. I2C Write Diagram

specified. A diagram of the procedure is shown in Figure 47.

1. Send a start condition (while holding the SCL line high,
2. Send the ADN4604 part address (seven bits) whose upper

bits are controlled by the input pins ADDR1 and ADDR0. This transfer should be MSB first.

1. Send the write indicator bit (0).
2. Wait for the ADN4604 to acknowledge the request.
3. Send the register address (eight bits) from which data is to

procedure (Step 1 to Step 6).

1. Wait for the ADN4604 to acknowledge the request.
2. Send a repeated start condition (while holding the SCL line

high, pull the SDA line low).

1. Send the ADN4604 part address (seven bits) whose upper

bits are controlled by the input pins ADDR1 and ADDR0. This transfer should be MSB first.

1. Send the read indicator bit (1).
2. Wait for the ADN4604 to acknowledge the request.
3. The ADN4604 then serially transfers the data (eight bits)

held in the register indicated by the address set in Step 5.

1. Do one or more of the following:

pull the SDA line high) and release control of the bus. Write section) to perform a write. Address 0x6D of an ADN4604 part with a part address of 0x4B. phase case shown is that of 13a. start where the SDA line is brought high before SCL is raised. SDA is then dropped while SCL is still high. Figure 47. I2C Read Diagram

Registers repeated per port or per table entry are grouped together. Register address mapping is shown in the first column. Table 18. Register Map 0x00 N/A RESET 0 Reset Software reset. Write only.

6 EQ[6] Equalizer boost control for Input 6

5 EQ[5] Equalizer boost control for Input 5

4 EQ[4] Equalizer boost control for Input 4

3 EQ[3] Equalizer boost control for Input 3

2 EQ[2] Equalizer boost control for Input 2

1 EQ[1] Equalizer boost control for Input 1

0 EQ[0] Equalizer boost control for Input 0

14 EQ[14] Equalizer boost control for Input 14

13 EQ[13] Equalizer boost control for Input 13

12 EQ[12] Equalizer boost control for Input 12

11 EQ[11] Equalizer boost control for Input 11

10 EQ[10] Equalizer boost control for Input 10

9 EQ[9] Equalizer boost control for Input 9

8 EQ[8] Equalizer boost control for Input 8

6 SIGN[6] Signal path polarity inversion for Input 6

5 SIGN[5] Signal path polarity inversion for Input 5

4 SIGN[4] Signal path polarity inversion for Input 4

3 SIGN[3] Signal path polarity inversion for Input 3

2 SIGN[2] Signal path polarity inversion for Input 2

1 SIGN[1] Signal path polarity inversion for Input 1

0 SIGN[0] Signal path polarity inversion for Input 0

14 SIGN[14] Signal path polarity inversion for Input 14

13 SIGN[13] Signal path polarity inversion for Input 13

12 SIGN[12] Signal path polarity inversion for Input 12

11 SIGN[11] Signal path polarity inversion for Input 11

10 SIGN[10] Signal path polarity inversion for Input 10

9 SIGN[9] Signal path polarity inversion for Input 9

8 SIGN[8] Signal path polarity inversion for Input 8

Rev. A | Page 29 of 40 Address: Channel Default Register Name Bit Bit Name Description 0x18: Broadcast1, 0x20: Output 0, 0x21: Output 1, 0x22: Output 2, 0x23: Output 3, 0x24: Output 4, 0x25: Output 5, 0x26: Output 6, 0x27: Output 7, 0x28: Output 8, 0x29: Output 9, 0x2A: Output 10, 0x2B: Output 11, 0x2C: Output 12, 0x2D: Output 13, 0x2E: Output 14, 0x2F: Output 15 0x00 TX basic control 6 TX CTL SELECT 0: PE and output level control is derived from common lookup table 1: PE and output level control is derived from per port drive control registers 5:4 TX EN[1:0] 00: TX disabled, lowest power state 01: TX standby 10: TX squelched 11: TX enabled 3 Reserved Reserved. Set to 0. 2:0 PE[2:0] If TX CTL SELECT = 0, see Table 10 Selected table entry = decimal(PE[2:0]) If TX CTL SELECT = 1, PE[2:0] are ignored 0x30: Output 0, 0x32: Output 1, 0x34: Output 2, 0x36: Output 3, 0x38: Output 4, 0x3A: Output 5, 0x3C: Output 6, 0x3E: Output 7, 0x40: Output 8, 0x42: Output 9, 0x44: Output 10, 0x46: Output 11, 0x48: Output 12, 0x4A: Output 13, 0x4C: Output 14, 0x4E: Output 15 0xFF TX Drive 0 control 1: Driver 1 enabled 6:4 DRV LV1[2:0] Driver 1 current = decimal(DRV LV1[2:0]) + 1 1: Driver 0 enabled 2:0 DRV LV0[2:0] Driver 0 current = decimal(DRV LV0[2:0]) + 1 0x31: Output 0, 0x33: Output 1, 0x35: Output 2, 0x37: Output 3, 0x39: Output 4, 0x3B: Output 5, 0x3D: Output 6, 0x3F: Output 7, 0x41: Output 8, 0x43: Output 9, 0x45: Output 10, 0x47: Output 11, 0x49: Output 12, 0x4B: Output 13, 0x4D: Output 14, 0x4F: Output 15 0x00 TX Drive 1 control 1: Driver D enabled 6:4 DRV LVD[2:0] Driver D current = decimal(DRV LVD[2:0]) + 1 1: Driver 2 enabled 2:0 DRV LV2[2:0] Driver 2 current = decimal(DRV LV2[2:0]) + 1 0x60: Table Entry 0 0xFF TX Lookup Table 0 1: Driver 1 enabled 0x62: Table Entry 1 0xFF 0x64: Table Entry 2 0xFF 6:4 DRV LV1[2:0] Driver 1 current = decimal(DRV LV1[2:0]) + 1 0x66: Table Entry 3 0xFF 0x68: Table Entry 4 0xDC 3 DRV EN0 0: Driver 0 disabled 1: Driver 0 enabled 0x6A: Table Entry 5 0xBB 0x6C: Table Entry 6 0x99 2:0 DRV LV0[2:0] Driver 0 current = decimal(DRV LV0[2:0]) + 1 0x6E: Table Entry 7 0x99

Rev. A | Page 30 of 40 Address: Channel Default Register Name Bit Bit Name Description 0x61: Table Entry 0 0x00 TX Lookup Table 1 1: Driver D enabled 0x63: Table Entry 1 0x99 0x65: Table Entry 2 0xCC 6:4 DRV LVD[2:0] Driver D current = decimal(DRV LVD[2:0]) + 1 0x67: Table Entry 3 0xFF 0x69: Table Entry 4 0xFF 3 DRV EN2 0: Driver 2 disabled 1: Driver 2 enabled 0x6B: Table Entry 5 0xFF 0x6D: Table Entry 6 0xDD 2:0 DRV LV2[2:0] Driver 2 current = decimal(DRV LV2[2:0]) + 1 0x6F: Table Entry 7 0xDD 0x80 Write only Update 0 UPDATE Updates XPT switch core (active high, write only) 0x81 0x00 Map table select 0 MAP TABLE SELECT 0: Map 0 is selected 1: Map 1 is selected 0x82 Write only XPT broadcast 3:0 BROADCAST[3:0] All outputs connection assignment 0x90 0xEF XPT Map 0 Control 0 7:4 OUT1[3:0] Output 1 connection assignment 3:0 OUT0[3:0] Output 0 connection assignment 0x91 0xCD XPT Map 0 Control 1 7:4 OUT3[3:0] Output 3 connection assignment 3:0 OUT2[3:0] Output 2 connection assignment 0x92 0xAB XPT Map 0 Control 2 7:4 OUT5[3:0] Output 5 connection assignment 3:0 OUT4[3:0] Output 4 connection assignment 0x93 0x89 XPT Map 0 Control 3 7:4 OUT7[3:0] Output 7 connection assignment 3:0 OUT6[3:0] Output 6 connection assignment 0x94 0x67 XPT Map 0 Control 4 7:4 OUT9[3:0] Output 9 connection assignment 3:0 OUT8[3:0] Output 8 connection assignment 0x95 0x45 XPT Map 0 Control 5 7:4 OUT11[3:0] Output 11 connection assignment 3:0 OUT10[3:0] Output 10 connection assignment 0x96 0x23 XPT Map 0 Control 6 7:4 OUT13[3:0] Output 13 connection assignment 3:0 OUT12[3:0] Output 12 connection assignment 0x97 0x01 XPT Map 0 Control 7 7:4 OUT15[3:0] Output 15 connection assignment 3:0 OUT14[3:0] Output 14 connection assignment 0x98 0x10 XPT Map 1 Control 0 7:4 OUT1[3:0] Output 1 connection assignment 3:0 OUT0[3:0] Output 0 connection assignment 0x99 0x32 XPT Map 1 Control 1 7:4 OUT3[3:0] Output 3 connection assignment 3:0 OUT2[3:0] Output 2 connection assignment 0x9A 0x54 XPT Map 1 Control 2 7:4 OUT5[3:0] Output 5 connection assignment 3:0 OUT4[3:0] Output 4 connection assignment 0x9B 0x76 XPT Map 1 Control 3 7:4 OUT7[3:0] Output 7 connection assignment 3:0 OUT6[3:0] Output 6 connection assignment 0x9C 0x98 XPT Map 1 Control 4 7:4 OUT9[3:0] Output 9 connection assignment 3:0 OUT8[3:0] Output 8 connection assignment 0x9D 0xBA XPT Map 1 Control 5 7:4 OUT11[3:0] Output 11 connection assignment 3:0 OUT10[3:0] Output 10 connection assignment 0x9E 0xDC XPT Map 1 Control 6 7:4 OUT13[3:0] Output 13 connection assignment 3:0 OUT12[3:0] Output 12 connection assignment 0x9F 0xFE XPT Map 1 Control 7 7:4 OUT15[3:0] Output 15 connection assignment 3:0 OUT14[3:0] Output 14 connection assignment

Rev. A | Page 31 of 40 Address: Channel Default Register Name Bit Bit Name Description 0xB0 0xEF XPT Status 0 7:4 OUT1[3:0] Output 1 connection status 3:0 OUT0[3:0] Output 0 connection status 0xB1 0xCD XPT Status 1 7:4 OUT3[3:0] Output 3 connection status 3:0 OUT2[3:0] Output 2 connection status 0xB2 0xAB XPT Status 2 7:4 OUT5[3:0] Output 5 connection status 3:0 OUT4[3:0] Output 4 connection status 0xB3 0x89 XPT Status 3 7:4 OUT7[3:0] Output 7 connection status 3:0 OUT6[3:0] Output 6 connection status 0xB4 0x67 XPT Status 4 7:4 OUT9[3:0] Output 9 connection status 3:0 OUT8[3:0] Output 8 connection status 0xB5 0x45 XPT Status 5 7:4 OUT11[3:0] Output 11 connection status 3:0 OUT10[3:0] Output 10 connection status 0xB6 0x23 XPT Status 6 7:4 OUT13[3:0] Output 13 connection status 3:0 OUT12[3:0] Output 12 connection status 0xB7 0x01 XPT Status 7 7:4 OUT15[3:0] Output 15 connection status 3:0 OUT14[3:0] Output 14 connection status 0xF0 0x00 Termination control

3 TXN_TERM Output[15:8] (North) termination control

0: Terminations enabled 1: Terminations disabled 0xFE Revision 7:0 REV[7:0] Read-only 0xFF 0x04 Device ID 7:0 ID[7:0] Read-only 1 Broadcast register, Address 0x18, is write-only.

Figure 52. ADN4604 Networking Switch Application Block Diagram

8 LANE UPLINK PATH

8 LANE DOWNLINK PATH

Figure 53. Multi-Lane Signal Conditioning Application Diagram

should be powered off before VCC.

• Peak current from V TTIx or VTTOx to VCC < 200 mA
• Sustained current from VTTIx or VTTOx to VCC < 100 mA POWER DISSIPATION The power dissipation of the ADN4604 depends on the supply voltages, I/O coupling type, and device configuration. The input termination resistors dissipate power depending on the differential input swing and common-mode voltage. When ac- coupled, the common-mode voltage is equal to the termination supply voltage (VTTIE or VTTIW). While the current drawn from the input termination supply is effectively zero, there is still power and heat dissipated in the termination resistors as a result of the differential signal swing. The core supply current and output termination current are strongly dependent on device configuration, such as the number of channels enabled, output level setting, and output preemphasis setting. In high ambient temperature operating conditions, it is impor- tant to avoid exceeding the maximum junction temperature of the device. Limiting the total power dissipation can be achieved by the following:
• Reducing the output swing
• Reducing the preemphasis level
• Decreasing the supply voltages within the allowable ranges defined in Table 1
• Disabling unused channels Alternatively, the thermal resistance can be reduced by
• Adding an external heat-sink
• Increasing the airflow Refer to the Printed Circuit Board (PCB) Layout Guidelines section for recommendations for proper thermal stencil layout and fabrication. OUTPUT COMPLIANCE In low voltage applications, users must pay careful attention to both the differential and common-mode signal level. The choice of output voltage swing, preemphasis setting, supply voltages (VCC and VTTO), and output coupling (ac or dc) affect peak and settled single-ended voltage swings and the common- mode shift measured across the output termination resistors. These choices also affect output current and, consequently, power consumption. Table 19 shows the change in output common mode (ΔVOCM = VCC − VOCM) with output level and preemphasis setting. Single-ended output levels are calculated for VTTO supplies of 3.3 V and 2.5 V to illustrate practical challenges of reducing the supply voltage. The minimum VL (min VL) cannot be below the absolute minimum level specified in

Table 1. The combinations of output level, preemphasis, supply specification is violated are listed as N/A in Table 1. Figure 54. DC-Coupled Level Translator Application Circuit

Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting 1 Symbol definitions are shown in Table 14. 2 This setting is not allowed when ac-coupled with VCC = 2.7 V and VTTON = 2.5 V or VTTOS = 2.5 V.

(LPI) solder mask from the bottom side; or via encroaching. Figure 58. Solder Mask Options for Thermal Vias: (A) Via Tenting from the

14.00 BSC SQ

16.00 BSC SQ

0.50 BSC

Figure 59. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. A | Page 39 of 40 NOTES

Rev. A | Page 40 of 40 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D07934-0-3/13(A)