ADN2818ACPZ-RL

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Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs Data Sheet ADN2817/ADN2818 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate Bit error rate monitor (BERMON) or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates Fibre Channel, 2× Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment GENERAL DESCRIPTION The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver. The ADN2817/ADN2818 have many optional features available through an I 2C interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER. The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package. FUNCTIONAL BLOCK DIAGRAM LOOP FILTER PHASE DET SLICE ADJUST (ADN2817 ONLY) LOS DETECT (ADN2817 ONLY) DATA RETIMING I2C REGISTERS LOOP FILTER FREQ/ LOCK DET VCC VEE ADN2817/ADN2818 CF1 CF2LOL REFCLKP/REFCLKN (OPTIONAL) SLICEP/ SLICEN PIN NIN VREF THRADJ LOS DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN SCK SDA VCO 06001-001 BERMON VBER BERMODE PHASE SHIFTER ΔФ Figure 1.

ADN2817/ADN2818 Data Sheet Rev. E | Page 2 of 40 TABLE OF CONTENTS

Data Sheet ADN2817/ADN2818 Rev. E | Page 3 of 40

REVISION HISTORY

1/13 Rev. D to Rev. E 1/12—Rev. C to Rev. D 3/10—Rev. B to Rev. C Changes to Initiate Frequency Acquisition, Rate Selectivity, Double Data Rate Mode, and PRBS Generator/Detector 2/09—Rev. A to Rev. B 8/08—Rev. 0 to Rev. A Changes to Features Section, General Description Section, and Added Bit Rate Monitor Specifications Section and Table 4; Added Sample Phase Adjust Section and Bit Error Rate (BER) 7/07—Revision 0: Initial Version

ADN2817/ADN2818 Data Sheet Rev. E | Page 4 of 40 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit QUANTIZER—DC CHARACTERISTICS Input Voltage Range At PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 2.0 V Input Common-Mode Level DC-coupled (see Figure 40, Figure 41, and Figure 42) 2.3 2.5 2.8 V Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10−10 ADN2817 10 5 mV p-p ADN2818 200 mV p-p QUANTIZER—AC CHARACTERISTICS Data Rate 10 2700 Mbps S11 At 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF QUANTIZER—SLICE ADJUSTMENT ADN2817 only Gain SLICEP − SLICEN = ±0.5 V 0.10 0.11 0.13 V/V Differential Control Voltage Input SLICEP − SLICEN −0.95 +0.95 V Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V Slice Threshold Offset ±1 mV LOSS OF SIGNAL DETECT (LOS) ADN2817 only Loss of Signal Detect Range (See Figure 6) RThresh = 0 Ω 14.2 20.0 mV RThresh = 100 kΩ 2.1 5.0 mV Hysteresis (Electrical) OC-48 RThresh = 0 Ω 6.2 8.2 dB RThresh = 100 kΩ 4.7 7.7 dB OC-1 RThresh = 0 Ω 4.9 7.5 dB RThresh = 10 kΩ 3.0 7.3 dB LOS Assert Time DC-coupled2 450 ns LOS Deassert Time DC-coupled2 500 ns LOSS OF LOCK DETECT (LOL) VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time OC-48 1.0 µs OC-12 1.0 µs

10 Mbps 500 µs

OC-48 1.3 ms OC-12 2.0 ms OC-3 3.4 ms OC-1 9.8 ms 10 Mbps 40.0 ms Optional Lock to REFCLK Mode 10.0 ms DATA RATE READBACK ACCURACY Coarse Readback See Table 19 10 % Fine Readback In addition to REFCLK accuracy 100 ppm

Data Sheet ADN2817/ADN2818 Rev. E | Page 5 of 40 Parameter Conditions Min Typ Max Unit POWER SUPPLY Voltage 3.0 3.3 3.6 V Current ADN2817 210 247 mA ADN2818 180 217 mA OPERATING TEMPERATURE RANGE −40 +85 °C 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817 input stage. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth OC-48 548 839 kHz OC-12 93 137 kHz OC-3 30 40 kHz Jitter Peaking OC-48 0 0.03 dB OC-12 0 0.03 dB OC-3 0 0.03 dB Jitter Generation OC-48 12 kHz to 20 MHz 0.001 0.003 UI rms 0.02 0.046 UI p-p OC-12 12 kHz to 5 MHz 0.001 0.004 UI rms 0.01 0.036 UI p-p OC-3 12 kHz to 1.3 MHz 0.001 0.004 UI rms 0.01 0.023 UI p-p Jitter Tolerance 223 − 1 PRBS OC-48 600 Hz1 92.0 UI p-p 6 kHz1 20.0 UI p-p 100 kHz 7.0 UI p-p 1 MHz1 1.00 UI p-p 20 MHz 0.53 UI p-p OC-12 30 Hz1 100.0 UI p-p 300 Hz1 44.0 UI p-p 25 kHz 7.35 UI p-p 250 kHz1 1.00 UI p-p 5 MHz 0.52 UI p-p OC-3 30 Hz1 50.0 UI p-p 300 Hz1 23.5 UI p-p 6500 Hz 6.71 UI p-p 65 kHz1 1.00 UI p-p 130 kHz 0.54 UI p-p 1 Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.

ADN2817/ADN2818 Data Sheet Rev. E | Page 6 of 40 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Single-Ended Output Swing, VSE See Figure 3 300 350 600 mV Differential Output Swing, VDIFF See Figure 3 600 700 1200 mV Output Voltage High, VOH VCC V Low, VOL VCC − 0.6 VCC − 0.35 VCC − 0.3 V CML Outputs Timing Rise Time 20% to 80% 80 112 ps Fall Time 80% to 20% 80 123 ps Setup Time, tS See Figure 2, OC-48 150 200 250 ps Hold Time, tH See Figure 2, OC-48 150 200 250 ps Setup Time, tDDRS See Figure 4, OC-48 140 170 200 ps Hold Time, tDDRH See Figure 4, OC-48 200 230 260 ps I2C INTERFACE DC CHARACTERISTICS LVCMOS Input Voltage High, VIH 0.7 VCC V Low, VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 22 SCK Clock Frequency 400 kHz SCK Pulse Width High High, tHIGH 600 ns Low, tLOW 1300 ns Start Condition Hold Time, tHD;STA 600 ns Setup Time, tSU;STA 600 ns Data Setup Time, tSU;DAT 100 ns Hold Time, tHD;DAT 300 ns SCK/SDA Rise/Fall Time, tR/tF 20 + 0.1 Cb 300 ns Stop Condition Setup Time, tSU;STO 600 ns Bus Free Time Between a Stop and a Start, tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range At REFCLKP or REFCLKN VIL 0 V VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 200 MHz Required Accuracy 100 ppm

Data Sheet ADN2817/ADN2818 Rev. E | Page 7 of 40 Parameter Conditions Min Typ Max Unit LVTTL DC INPUT CHARACTERISTICS Input Voltage High, VIH 2.0 V Low, VIL 0.8 V Input Current High IIH, VIN = 2.4 V +5 µA Low IIL, VIN = 0.4 V −5 µA LVTTL DC OUTPUT CHARACTERISTICS Output Voltage High VOH, IOH = −2.0 mA 2.4 V Low VOL, IOL = +2.0 mA 0.4 V

ADN2817/ADN2818 Data Sheet Rev. E | Page 8 of 40 BIT ERROR RATE MONITOR SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 4. Parameter Conditions Min Typ Max Unit BERMON Extrapolation Mode I2C-controlled eye profiling Final Computed BER Accuracy Input BER range 1 × 10−3 to 1 × 10−12, input deterministic jitter (DJ) < 0.4 UI, DJ ceiling > 1 × 10−2; asymmetry < 0.1 UI; requires external data processing algorithms to implement Q factor extrapolation ±1 Decades Number of Bits (NUMBITS) Number of data bits to collect pseudo errors; user programmable in increment factors of 23 over the range 218 to 239 218 239 UI Pseudo BER (PBER) Measurement Time NUMBITS/ data rate sec BER Range 5 × 10−2 BER Sample Phase Adjust Resolution 6 Degrees Sample Phase Adjust Accuracy <6 Degrees Sample Phase Adjust Range With respect to normal sampling instant −0.5 +0.5 UI Minimum Input Signal Level Differential peak to peak 4 mV Power Increase BER enabled 160 mW BER standby 77 mW BERMON Voltage Output Mode Analog voltage output BER Accuracy Input BER range 1 × 10−3 to 1 × 10−9, input DJ = 0 UI, DJ ceiling > 1 × 10−2; asymmetry = 0 UI; BER is read as a voltage on the VBER pin, when the BER mode pin = VEE ±1 Decades Input BER range 1 × 10−3 to 1 × 10−9, input DJ = 0.2 UI, DJ ceiling > 1 × 10−2; asymmetry = 0 UI; BER is read as a voltage on the VBER pin, when the BER mode pin = VEE +1/−2 Decades NUMBITS Number of data bits to collect pseudo errors 227 UI Measurement Time 2.5 Gbps 0.054 sec 1 Gbps 0.134 sec 155 Mbps 0.865 sec 10 Mbps 1.34 sec VBER Voltage Range Via 3 kΩ resistor to VEE 0.1 0.9 V Minimum Input Signal Level Differential peak to peak 4 mV Power Increase BER voltage mode 160 mW Sample Phase Adjust Mode Sample Phase Adjust Step Size Monotonic 6 Degrees Sample Phase Adjust Accuracy <6 Degrees Sample Phase Adjust Range With respect to normal sampling instant −0.5 +0.5 UI Power Increase 160 mW

CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted. 4-layer board with the exposed paddle soldered to VEE. Table 6. Thermal Resistance

1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE

Figure 5. Pin Configuration Table 7. Pin Function Descriptions 1 BERMODE DI Set this pin to logic low to enable analog voltage output mode for BER monitor. 2 VCC P Power for Input Stage, LOS. 3 VREF AO Internal VREF Voltage. Decouple to ground with a 0.1 µF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 SLICEP AI Differential Slice Level Adjust Input. 7 SLICEN AI Differential Slice Level Adjust Input. 8 VEE P GND for the Limiting Amplifier, LOS. 9 THRADJ AI LOS Threshold Setting Resistor. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 200 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 200 MHz. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss of Lock Indicator. Active high, LVTTL. 17 VEE P FLL Detector Ground. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 22 LOS DO Loss of Signal Detect Output. Active high, LVTTL. 23 VEE P Output Buffer, I2C Ground. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. CML. 26 CLKOUTP DO Differential Recovered Clock Output. CML. 27 SQUELCH DI Disable Clock and Data Outputs. Active high, LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. CML. 29 DATAOUTP DO Differential Recovered Data Output. CML. 30 VEE P Phase Detector, Phase Shifter Ground. 31 VCC P Phase Detector, Phase Shifter Power. 32 VBER AO This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE. 1 P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

1 A 5 00000 X

Figure 18. Slave Address Configuration Figure 19. I2C Write Data Transfer Figure 20. I2C Read Data Transfer Figure 21. I2C Data Transfer Timing Figure 22. I2C Port Timing Diagram

Table 8. Internal Register Map1

0 Reset

0 Initiate

0 PRBS/DDR enable and output mode

0 CLK

2 Both CTRLE and BERCTLB registers are used, depending on the application. Table 9. Miscellaneous Register, MISC

Table 10. Control Register, CTRLA Table 11. Control Register, CTRLB Table 12. Control Register, CTRLC Table 13. Control Register, CTRLD Table 14. Control Registers, CTRLE/BERCTLB 1 See AN-941 Application Note, BER Monitor User Guide.

Table 15. Mode Select Register, SEL_MODE Table 16. BER Control Register, BERCTLA

Data Sheet ADN2817/ADN2818 Rev. E | Page 21 of 40 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed-loop bandwidth of the delay-locked loop, which is roughly 3 MHz at OC-48.

ADN2817/ADN2818 Data Sheet Rev. E | Page 24 of 40 SAMPLE PHASE ADJUST If the user is not using the BER monitoring function, sample phase adjustment can be used to optimize the horizontal samp- ling point of the incoming data eye. The ADN2817 automatically centers the sampling point to the best of its ability. However, sample phase adjustment can be used to compensate for any static phase offset of the CDR and data eye jitter profile asymmetry. Sample phase adjustment is applied to the incoming eye via the phase register. The sampling phase can be adjusted by ±0.5 UI, in 6 degree steps, relative to the normal CDR data sampling instant. Using the sample phase adjustment capability uses an additional 160 mW of power. The AN-941 application note gives additional information on the use of this feature. BIT ERROR RATE (BER) MONITOR The ADN2817 has a BER measurement feature that estimates the actual bit error rate of the IC. This feature also allows data eye jitter profiling and Q-factor estimation. By knowing the BER at a sampling phase offset from the ideal sampling phase (known as pseudo BER [PBER] values), it is possible to extrapolate to obtain an estimate of the BER at the actual sampling instant. This extrapolation relies on the assumption that the input jitter is composed of deterministic and random (Gaussian) components. The implementation requires off-chip control and data processing to estimate the actual BER. A lower accuracy voltage output mode is also supported that requires no data processing or I 2C control. Brief Overview of Modes of Operation The following two modes of operation are available for the BER feature: the BER extrapolation mode and the voltage output mode. Only one mode can be operational at a time. The BER extra- polation mode scans the input eye in the range of ±0.5 UI of the data center and reads the measured PBER over the I2C. The user then applies a data processing algorithm to determine the BER. Using the BER feature in this way provides for the greatest accuracy in BER estimation as the magnitude of both random (Gaussian) jitter and deterministic jitter can be estimated and used to predict the actual BER. In the voltage output mode, the part autonomously samples the PBER at 0.1 UI offset and decodes this value to provide an estimate of the input BER. This estimate is output via a DAC as an analog current output. The AN-941 application note gives detailed information on the use of the BER monitor features. BER Extrapolation Mode Power Saving The following three power settings are available in BER extrapolation mode: BER off, BER on, and BER standby. In BER off mode (BERCTLB[5] = 0), the BER circuitry is powered down with the ADN2817 providing normal CDR operation. In BER on mode (BERCTLB[5] = 1), the internal BER circuitry is powered up. The user can perform pseudo BER measurements through the I2C. In BER standby mode (BERCTLB[5:4] = 11b), the BER is placed into a lower power mode. This setting can only be set after applying the BER on setting. These modes are defined to allow optimal power saving opportunities. It is not possible to switch between the BER off setting and the BER on setting without losing lock. Switching between the BER standby setting and the BER on setting is achieved without interrupting data recovery. The incremental power between the BER off setting and the BER standby setting is 77 mW and between the BER off setting and the BER on setting it is 160 mW . BER On Mode The BER on mode allows the user to scan the incoming data eye in the time dimension and build up a profile of the BER statistics. The following is a brief overview of user protocol:

• The user powers up BER circuitry through the I2C.
• The user initiates the PBER measurement. Sample phase offset and number of data bits to be counted (NUMBITS is a choice among 2 18, 221, 224, 227, 230, 233, 236, and 239) are supplied by the user through the I2C.
• The user initiates the pseudo BER measurement by writing a 1-to-0 transition on BERCTLA[3].
• BER logic indicates the end of the BER measurement with an EOBM signal and updates the number of counted errors on NUMERRORS[39:0]. The user must poll the I 2C to determine if the EOBM bit, BERSTS[0], has been asserted.
• The user reads back NUMERRORS[39:0] through the I2C. NUMERRORS[39:0] is read back through the 8-bit register BER_RES at Address 0x21. The user sets BERCTLA[2:0] to address one of the five NUMERRORS bytes and then reads the selected byte from BER_RES.
• PBER for programmed sample phase is calculated as NUMERRORS/NUMBITS.
• The user initiates another PBER measurement.
• The user sweeps the phase over −0.5 UI to +0.5 UI with respect to the normal sampling instant to obtain the BER profile required. The ADN2817 does not output the BER at the normal decision instant. It outputs PBER measurements to the left and right of the normal decision instants from which the user must calculate what the BER is at the normal decision instant. A microprocessor is required to parse the data and to use the remaining data for BER estimation. Suitable algorithms are suggested in the AN-941 Application Note, BER Monitor User Guide.

Figure 32. VBER vs. Bit Error Rate where the recovered clock may not be needed. operation and Logic 0 corresponds to a write operation. master reads information from the peripheral. register on a one-by-one basis without updating all registers. do not issue an acknowledge and return to the idle condition.

Data Sheet ADN2817/ADN2818 Rev. E | Page 27 of 40 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF and DIV_FREF represents the divided-down reference referred to the 10 MHz to 25 MHz band. For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mbps, then CTRLA[7:6] is set to 01 to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] is set to 0101, that is, 5, because 622.08 Mbps/19.44 MHz = 25 When the CTRLA[7:2] value is correct and CTRLA[0] has been written to a Logic 1, it is recommended that a 1-to-0 transition be written to CTRLB[5] to initiate a new frequency acquisition with respect to the reference clock. In this mode, if the ADN2817/ADN2818 lose lock for any reason, they relock onto the reference clock and continue to output a stable clock. Though the ADN2817/ADN2818 operate in LTR mode, if the user ever changes the reference frequency, the fREF range (CTRLA[7:6]), or the DIV_FREF ratio (CTRLA[5:2]), this must be followed by writing a 1-to-0 transition into the CTRLB[5] bit to initiate a new frequency acquisition. A frequency acquisition can also be initiated in LTR mode by writing a 0-to-1 transition into CTRLA[0]; however, it is rec- ommended that a frequency acquisition be initiated by writing a 1-to-0 transition into CTRLB[5], as explained previously. Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2817/ADN2818 compare the frequency of the incoming data to the incoming reference clock and return a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy of the ADN2817/ADN2818 data rate measurement. For example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. The reference clock can range from 10 MHz to 200 MHz. The ADN2817/ADN2818 expects a reference clock between 10 MHz and 25 MHz by default. If it is between 25 MHz and 50 MHz,

50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user

needs to configure the ADN2817/ADN2818 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: 1. Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2817/ADN2818. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. 2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. 3. Read back MISC[2]. If it is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. 4. Read back the data rate from the FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0] registers. Use the following equation to determine the data rate: f DATARATE = (FREQ[22..0] × fREFCLK)/2(14 + SEL_RATE) (1) where: FREQ[22:0] is the reading from FREQ2[6:0] (most significant byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See Table 18. f DATARATE is the data rate (Mbps). fREFCLK is the REFCLK frequency (MHz). SEL_RATE is the setting from CTRLA[7:6]. Table 18. D22 D21:D17 D16 D15 D14:D9 D8 D7 D6:D1 D0 FREQ2[6:0] FREQ1[7:0] FREQ0[7:0] For example, if the reference clock frequency is 32 MHz, it falls within the 25 MHz to 50 MHz range; therefore, the CTRLA[7:6] setting is 01 resulting in SEL_RATE = 1. For this example, the input data rate is 2.488 Gbps (OC-48). After following Step 1 through Step 4, the value that is read back on FREQ[22:0] = 0x26E010, which is equal to 2.5477 × 106. Plugging this value into Equation 1 yields If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measure- ment process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Step 2 through Step 4 to read back the new data rate. Note that a data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid.

ADN2817/ADN2818 Data Sheet Rev. E | Page 28 of 40 ADDITIONAL FEATURES AVAILABLE VIA THE I2C INTERFACE Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately ±10% without needing an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The eight MSBs of this register are the contents of the Rate[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table 19 is a look-up table (LUT) that provides coarse data rate readback values to within ±10%. LOS Configuration The LOS detector output, Pin 22 (LOS), can be configured as either active high or active low. If CTRLC[2] is set to Logic 0 (default), the LOS pin is active high when a loss of signal condition is detected. Writing a 1 to CTRLC[2] configures the LOS pin to be active low when a loss of signal condition is detected. Initiate Frequency Acquisition A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2817/ADN2818 in the operating mode that was previously programmed in the CTRLA, CTRLB, CTRLC, CTRLD, and CTRLE registers. Rate Selectivity The ADN2817/ADN2818 can operate in a limited range mode in situations where the user wants to restrict the data rates to which the device can lock. In this mode, the frequency acquisition range of the device is limited to a specific range of data rates. The acquisition range is determined by programming an upper and lower 9-bit code into the HI_CODE[8:1], LO_CODE[8:1], and CODE_LSB[1:0] I2C registers. See Table 20 for a look-up table (LUT) showing the correct register settings for each data rate. Table 20 has three columns: code, high limit, and low limit. The user programs the code value for the high limit data rate into HI_CODE and the code value for the low limit data rate into LO_CODE to set the appropriate range. For example, if the user wants to limit the acquisition range of the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps, the following steps must be taken: 1. Find the first code in Table 20 that corresponds to a data rate below 1.0 Gbps in the low limit column, that is, Code 236 or 011101100b. Set LO_CODE[8:1] = 01110110b (LO_CODE[0] is set in Register Bit CODE_LSB[0].) 2. Find the first code in Table 20 that corresponds to a data rate above 1.25 Gbps in the high limit column, that is, Code 258 or 100000010b. Set HI_CODE[8:1] = 10000001b (HI_CODE[0] is set in Register Bit CODE_LSB[1].) 3. Set CODE_LSB = 00000000b given that the HI_CODE[0] = 0 and LO_CODE[0] = 0. 4. Set SEL_MODE[3] = 1. 5. When there is a valid input to the device between 1.0 Gbps and 1.25 Gbps, write a 1-to-0 transition into CTRLB[5] to initiate a new frequency acquisition. Double Data Rate Mode Setting CTRLE = 0x02 puts the ADN2817/ADN2818 clock output through divide-by-two circuitry allowing direct interfacing to FPGAs that support data clocking on both rising and falling edges. PRBS Generator/Detector The ADN2817/ADN2818 have an integrated PRBS generator/ detector for system testing purposes. The devices are configurable as either a PRBS detector or a PRBS generator. The two functions cannot be used at the same time. The following steps configure the PRBS detector (PRBS 7 only): 1. Set CTRLE[2:0] = 0x5. 2. Set CTRLD[2:0] = 0x4 to enable the PRBS detector. The PRBS error signal outputs on the DATAOUTP/DATAOUTN pins. Every time the PRBS detector detects an error, the DATAOUTP/DATAOUTN outputs pulse twice to a Logic 1, that is, DATAOUTP = 1, DATAOUTN = 0. The following steps configure the PRBS generator (PRBS 7 only): 1. Set CTRLE[2:0] = 0x5. 2. Set CTRLD[2:0] = 0x1 to enable the PRBS generator. 3. Write a 1-to-0 transition into CTRLD[3] to initiate a PRBS 7 pattern. Note that the PRBS generator is clocked by the VCO; therefore, the user needs to feed in a clock at half the desired frequency. For example, for an OC-48 PRBS pattern, input a 1.244 GHz clock to PIN/NIN. This appears as a 2.488 Gbps NRZ data pattern to the ADN2817/ADN2818. The recovered clock is

2.488 GHz, which clocks the PRBS generator to produce an

OC-48 PRBS pattern on the outputs.

Data Sheet ADN2817/ADN2818 Rev. E | Page 29 of 40 CLK Holdover Mode This mode of operation is available in LTD mode. In CLK holdover mode, the output clock frequency remains within ±5% if the input data is removed or changed. To operate in this mode, the user writes to the I2C to put the part into CLK holdover mode by setting SEL_MODE[1] = 1. The user must then initiate a frequency acquisition by writing a 1-to-0 transi- tion into CTRLB[5], at which time the device locks onto the input data rate. At this point, the output frequency remains within ±5% of the initial acquired value regardless of whether the input data is removed or the data rate changes. It is important to note that all frequency acquisitions in this mode must be initiated by writing a 1-to-0 transition into CTRLB[5]. In this mode, the device does not automatically initiate a new frequency acquisition when the input is momen- tarily interrupted or if the input data rate changes. CDR Bypass Mode The CDR on the ADN2817/ADN2818 can be bypassed by setting Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed the input directly through the input amplifiers to the output buffer, completely bypassing the CDR. Disable Output Buffers The ADN2817/ADN2818 provide the option of disabling the output buffers for power savings. The clock output buffers can be disabled by setting Bit CTRLD[5] = 1. This reduces the total power consumption of the device by ~100 mW . For an additional 100 mW power savings, such as in low power standby mode, the data output buffers can also be disabled by setting Bit CTRLD[6] = 1.

as close as possible to the ADN2817/ADN2818 VCC pins. εr is the dielectric constant of the PCB material. A is the area of the overlap of power and ground planes (cm2). d is the separation between planes (mm). Figure 36. Typical ADN2817/ADN2818 Applications Circuit

Code is the 9-bit value read back from COARSE_RD[8:0]. Table 19. Coarse Data Rate Readback Look-Up Table

ADN2817/ADN2818 Data Sheet Rev. E | Page 34 of 40 Code fMID (Hz) 196 363.1019 × 106 197 371.7531 × 106 198 381.0083 × 106 199 390.9568 × 106 200 401.7362 × 106 201 414.1826 × 106 202 426.8911 × 106 203 440.8554 × 106 204 456.1247 × 106 205 472.8887 × 106 206 491.4474 × 106 207 511.9351 × 106 208 488.0916 × 106 209 488.0824 × 106 210 498.5126 × 106 211 509.7584 × 106 212 521.8480 × 106 213 534.8244 × 106 214 548.7933 × 106 215 563.8571 × 106 216 580.1596 × 106 217 598.9401 × 106 218 618.2792 × 106 Code fMID (Hz) 219 639.3962 × 106 220 662.4874 × 106 221 687.8404 × 106 222 715.6537 × 106 223 746.0568 × 106 224 681.0188 × 106 225 680.9806 × 106 226 694.9652 × 106 227 710.0511 × 106 228 726.2037 × 106 229 743.5062 × 106 230 762.0166 × 106 231 781.9136 × 106 232 803.4724 × 106 233 828.3653 × 106 234 853.7822 × 106 235 881.7109 × 106 236 912.2494 × 106 237 945.7774 × 106 238 982.8948 × 106 239 1.0239 × 109 240 976.1832 × 106 241 976.1648 × 106 Code fMID (Hz) 242 997.0253 × 106 243 1.0195 × 109 244 1.0437 × 109 245 1.0696 × 109 246 1.0976 × 109 247 1.1277 × 109 248 1.1603 × 109 249 1.1979 × 109 250 1.2366 × 109 251 1.2788 × 109 252 1.3250 × 109 253 1.3757 × 109 254 1.4313 × 109 255 1.4921 × 109 256 1.3620 × 109 257 1.3620 × 109 258 1.3899 × 109 259 1.4201 × 109 260 1.4524 × 109 261 1.4870 × 109 262 1.5240 × 109 263 1.5638 × 109 264 1.6069 × 109 Code fMID (Hz) 265 1.6567 × 109 266 1.7076 × 109 267 1.7634 × 109 268 1.8245 × 109 269 1.8916 × 109 270 1.9658 × 109 271 2.0477 × 109 272 1.9524 × 109 273 1.9523 × 109 274 1.9941 × 109 275 2.0390 × 109 276 2.0874 × 109 277 2.1393 × 109 278 2.1952 × 109 279 2.2554 × 109 280 2.3206 × 109 281 2.3958 × 109 282 2.4731 × 109 283 2.5576 × 109 284 2.6499 × 109 285 2.7514 × 109 286 2.8626 × 109 287 2.9842 × 109

Data Sheet ADN2817/ADN2818 Rev. E | Page 35 of 40 HI_CODE AND LO_CODE LOOK-UP TABLE Code is the 9-bit value to be written into HI_CODE[8:0] and LO_CODE[8:0]. Use the high limit code for HI_CODE and the low limit code for LO_CODE. Table 20. Code Low Limit High Limit 0 5.7633 × 106 4.8677 × 106 1 5.7631 × 106 4.8674 × 106 2 5.8777 × 106 4.9708 × 106 3 6.0011 × 106 5.0827 × 106 4 6.1328 × 106 5.2027 × 106 5 6.2738 × 106 5.3312 × 106 6 6.4245 × 106 5.4692 × 106 7 6.5859 × 106 5.6188 × 106 8 6.7593 × 106 5.7807 × 106 9 6.9599 × 106 5.9680 × 106 10 7.1641 × 106 6.1614 × 106 11 7.3860 × 106 6.3740 × 106 12 7.6292 × 106 6.6070 × 106 13 7.8947 × 106 6.8660 × 106 14 8.1855 × 106 7.1541 × 106 15 8.5061 × 106 7.4742 × 106 16 8.2705 × 106 6.9705 × 106 17 8.2701 × 106 6.9703 × 106 18 8.4414 × 106 7.1241 × 106 19 8.6260 × 106 7.2904 × 106 20 8.8239 × 106 7.4696 × 106 21 9.0356 × 106 7.6624 × 106 22 9.2629 × 106 7.8705 × 106 23 9.5073 × 106 8.0958 × 106 24 9.7707 × 106 8.3404 × 106 25 10.0733 × 106 8.6236 × 106 26 10.3832 × 106 8.9165 × 106 27 10.7202 × 106 9.2377 × 106 28 11.0869 × 106 9.5915 × 106 29 11.4873 × 106 9.9825 × 106 30 11.9244 × 106 10.4145 × 106 31 12.3996 × 106 10.8902 × 106 32 11.5265 × 106 9.7355 × 106 33 11.5261 × 106 9.7347 × 106 34 11.7554 × 106 9.9415 × 106 35 12.0022 × 106 10.1654 × 106 36 12.2655 × 106 10.4053 × 106 37 12.5475 × 106 10.6624 × 106 38 12.8490 × 106 10.9384 × 106 39 13.1718 × 106 11.2376 × 106 40 13.5186 × 106 11.5615 × 106 41 13.9198 × 106 11.9360 × 106 42 14.3282 × 106 12.3228 × 106 43 14.7719 × 106 12.7480 × 106 44 15.2584 × 106 13.2140 × 106 45 15.7894 × 106 13.7321 × 106 46 16.3711 × 106 14.3081 × 106 47 17.0122 × 106 14.9484 × 106 Code Low Limit High Limit 48 16.5410 × 106 13.9411 × 106 49 16.5402 × 106 13.9407 × 106 50 16.8827 × 106 14.2483 × 106 51 17.2521 × 106 14.5807 × 106 52 17.6479 × 106 14.9392 × 106 53 18.0712 × 106 15.3247 × 106 54 18.5258 × 106 15.7411 × 106 55 19.0145 × 106 16.1915 × 106 56 19.5415 × 106 16.6807 × 106 57 20.1465 × 106 17.2471 × 106 58 20.7665 × 106 17.8330 × 106 59 21.4403 × 106 18.4754 × 106 60 22.1738 × 106 19.1829 × 106 61 22.9747 × 106 19.9651 × 106 62 23.8487 × 106 20.8291 × 106 63 24.7993 × 106 21.7805 × 106 64 23.0530 × 106 19.4710 × 106 65 23.0523 × 106 19.4695 × 106 66 23.5108 × 106 19.8831 × 106 67 24.0044 × 106 20.3308 × 106 68 24.5310 × 106 20.8107 × 106 69 25.0951 × 106 21.3248 × 106 70 25.6980 × 106 21.8768 × 106 71 26.3436 × 106 22.4751 × 106 72 27.0373 × 106 23.1230 × 106 73 27.8396 × 106 23.8720 × 106 74 28.6564 × 106 24.6457 × 106 75 29.5438 × 106 25.4960 × 106 76 30.5167 × 106 26.4281 × 106 77 31.5787 × 106 27.4641 × 106 78 32.7422 × 106 28.6162 × 106 79 34.0244 × 106 29.8968 × 106 80 33.0819 × 106 27.8821 × 106 81 33.0805 × 106 27.8813 × 106 82 33.7655 × 106 28.4965 × 106 83 34.5041 × 106 29.1615 × 106 84 35.2957 × 106 29.8783 × 106 85 36.1424 × 106 30.6494 × 106 86 37.0517 × 106 31.4822 × 106 87 38.0290 × 106 32.3831 × 106 88 39.0830 × 106 33.3615 × 106 89 40.2930 × 106 34.4942 × 106 90 41.5329 × 106 35.6659 × 106 91 42.8807 × 106 36.9508 × 106 92 44.3477 × 106 38.3658 × 106 93 45.9493 × 106 39.9301 × 106 94 47.6975 × 106 41.6582 × 106 95 49.5986 × 106 43.5610 × 106

ADN2817/ADN2818 Data Sheet Rev. E | Page 36 of 40 Code Low Limit High Limit 96 46.1061 × 106 38.9419 × 106 97 46.1045 × 106 38.9390 × 106 98 47.0217 × 106 39.7661 × 106 99 48.0087 × 106 40.6617 × 106 100 49.0620 × 106 41.6214 × 106 101 50.1902 × 106 42.6496 × 106 102 51.3960 × 106 43.7535 × 106 103 52.6872 × 106 44.9502 × 106 104 54.0746 × 106 46.2459 × 106 105 55.6792 × 106 47.7440 × 106 106 57.3128 × 106 49.2913 × 106 107 59.0876 × 106 50.9920 × 106 108 61.0334 × 106 52.8561 × 106 109 63.1575 × 106 54.9282 × 106 110 65.4843 × 106 57.2324 × 106 111 68.0487 × 106 59.7936 × 106 112 66.1639 × 106 55.7643 × 106 113 66.1609 × 106 55.7626 × 106 114 67.5309 × 106 56.9931 × 106 115 69.0082 × 106 58.3229 × 106 116 70.5914 × 106 59.7566 × 106 117 72.2848 × 106 61.2989 × 106 118 74.1034 × 106 62.9643 × 106 119 76.0580 × 106 64.7662 × 106 120 78.1660 × 106 66.7230 × 106 121 80.5861 × 106 68.9885 × 106 122 83.0658 × 106 71.3318 × 106 123 85.7613 × 106 73.9016 × 106 124 88.6953 × 106 76.7317 × 106 125 91.8987 × 106 79.8603 × 106 126 95.3950 × 106 83.3164 × 106 127 99.1972 × 106 87.1220 × 106 128 92.2121 × 106 77.8839 × 106 129 92.2090 × 106 77.8780 × 106 130 94.0434 × 106 79.5323 × 106 131 96.0174 × 106 81.3234 × 106 132 98.1240 × 106 83.2427 × 106 133 100.3804 × 106 85.2993 × 106 134 102.7920 × 106 87.5071 × 106 135 105.3744 × 106 89.9004 × 106 136 108.1491 × 106 92.4919 × 106 137 111.3583 × 106 95.4879 × 106 138 114.6257 × 106 98.5827 × 106 139 118.1753 × 106 101.9841 × 106 140 122.0668 × 106 105.7122 × 106 141 126.3150 × 106 109.8565 × 106 142 130.9686 × 106 114.4648 × 106 143 136.0974 × 106 119.5872 × 106 144 132.3278 × 106 111.5286 × 106 145 132.3218 × 106 111.5252 × 106 146 135.0619 × 106 113.9862 × 106 147 138.0164 × 106 116.6459 × 106 148 141.1829 × 106 119.5132 × 106 Code Low Limit High Limit 149 144.5697 × 106 122.5977 × 106 150 148.2068 × 106 125.9286 × 106 151 152.1160 × 106 129.5324 × 106 152 156.3320 × 106 133.4459 × 106 153 161.1721 × 106 137.9770 × 106 154 166.1317 × 106 142.6637 × 106 155 171.5227 × 106 147.8032 × 106 156 177.3906 × 106 153.4634 × 106 157 183.7974 × 106 159.7205 × 106 158 190.7899 × 106 166.6328 × 106 159 198.3944 × 106 174.2440 × 106 160 184.4242 × 106 155.7678 × 106 161 184.4181 × 106 155.7560 × 106 162 188.0868 × 106 159.0645 × 106 163 192.0348 × 106 162.6467 × 106 164 196.2480 × 106 166.4855 × 106 165 200.7608 × 106 170.5985 × 106 166 205.5841 × 106 175.0142 × 106 167 210.7488 × 106 179.8008 × 106 168 216.2983 × 106 184.9838 × 106 169 222.7166 × 106 190.9759 × 106 170 229.2514 × 106 197.1654 × 106 171 236.3506 × 106 203.9681 × 106 172 244.1336 × 106 211.4245 × 106 173 252.6300 × 106 219.7129 × 106 174 261.9373 × 106 228.9296 × 106 175 272.1948 × 106 239.1744 × 106 176 264.6556 × 106 223.0571 × 106 177 264.6437 × 106 223.0505 × 106 178 270.1237 × 106 227.9723 × 106 179 276.0329 × 106 233.2917 × 106 180 282.3657 × 106 239.0265 × 106 181 289.1393 × 106 245.1954 × 106 182 296.4136 × 106 251.8572 × 106 183 304.2321 × 106 259.0647 × 106 184 312.6640 × 106 266.8919 × 106 185 322.3443 × 106 275.9539 × 106 186 332.2633 × 106 285.3273 × 106 187 343.0453 × 106 295.6065 × 106 188 354.7812 × 106 306.9268 × 106 189 367.5947 × 106 319.4411 × 106 190 381.5798 × 106 333.2656 × 106 191 396.7887 × 106 348.4879 × 106 192 368.8485 × 106 311.5355 × 106 193 368.8362 × 106 311.5120 × 106 194 376.1735 × 106 318.1291 × 106 195 384.0696 × 106 325.2934 × 106 196 392.4961 × 106 332.9710 × 106 197 401.5216 × 106 341.1971 × 106 198 411.1681 × 106 350.0283 × 106 199 421.4977 × 106 359.6016 × 106 200 432.5966 × 106 369.9675 × 106 201 445.4332 × 106 381.9518 × 106

Data Sheet ADN2817/ADN2818 Rev. E | Page 37 of 40 Code Low Limit High Limit 202 458.5027 × 106 394.3307 × 106 203 472.7012 × 106 407.9363 × 106 204 488.2673 × 106 422.8489 × 106 205 505.2599 × 106 439.4259 × 106 206 523.8745 × 106 457.8593 × 106 207 544.3897 × 106 478.3487 × 106 208 529.3112 × 106 446.1142 × 106 209 529.2874 × 106 446.1009 × 106 210 540.2475 × 106 455.9446 × 106 211 552.0658 × 106 466.5834 × 106 212 564.7314 × 106 478.0529 × 106 213 578.2786 × 106 490.3908 × 106 214 592.8272 × 106 503.7145 × 106 215 608.4642 × 106 518.1295 × 106 216 625.3279 × 106 533.7838 × 106 217 644.6885 × 106 551.9079 × 106 218 664.5266 × 106 570.6547 × 106 219 686.0907 × 106 591.2129 × 106 220 709.5624 × 106 613.8536 × 106 221 735.1895 × 106 638.8822 × 106 222 763.1596 × 106 666.5311 × 106 223 793.5774 × 106 696.9759 × 106 224 737.6969 × 106 623.0711 × 106 225 737.6724 × 106 623.0240 × 106 226 752.3471 × 106 636.2582 × 106 227 768.1392 × 106 650.5869 × 106 228 784.9921 × 106 665.9419 × 106 229 803.0432 × 106 682.3941 × 106 230 822.3363 × 106 700.0567 × 106 231 842.9953 × 106 719.2032 × 106 232 865.1931 × 106 739.9350 × 106 233 890.8664 × 106 763.9035 × 106 234 917.0055 × 106 788.6615 × 106 235 945.4024 × 106 815.8726 × 106 236 976.5346 × 106 845.6979 × 106 237 1.0105 × 109 878.8518 × 106 238 1.0477 × 109 915.7186 × 106 239 1.0888 × 109 956.6975 × 106 240 1.0586 × 109 892.2284 × 106 241 1.0586 × 109 892.2018 × 106 242 1.0805 × 109 911.8893 × 106 243 1.1041 × 109 933.1668 × 106 244 1.1295 × 109 956.1059 × 106 245 1.1566 × 109 980.7817 × 106 246 1.1857 × 109 1.0074 × 109 Code Low Limit High Limit 247 1.2169 × 109 1.0363 × 109 248 1.2507 × 109 1.0676 × 109 249 1.2894 × 109 1.1038 × 109 250 1.3291 × 109 1.1413 × 109 251 1.3722 × 109 1.1824 × 109 252 1.4191 × 109 1.2277 × 109 253 1.4704 × 109 1.2778 × 109 254 1.5263 × 109 1.3331 × 109 255 1.5872 × 109 1.3940 × 109 256 1.4754 × 109 1.2461 × 109 257 1.4753 × 109 1.2460 × 109 258 1.5047 × 109 1.2725 × 109 259 1.5363 × 109 1.3012 × 109 260 1.5700 × 109 1.3319 × 109 261 1.6061 × 109 1.3648 × 109 262 1.6447 × 109v 1.4001 × 109 263 1.6860 × 109 1.4384 × 109 264 1.7304 × 109 1.4799 × 109 265 1.7817 × 109 1.5278 × 109 266 1.8340 × 109 1.5773 × 109 267 1.8908 × 109 1.6317 × 109 268 1.9531 × 109 1.6914 × 109 269 2.0210 × 109 1.7577 × 109 270 2.0955 × 109 1.8314 × 109 271 2.1776 × 109 1.9134 × 109 272 2.1172 × 109 1.7845 × 109 273 2.1171 × 109 1.7844 × 109 274 2.1610 × 109 1.8238 × 109 275 2.2083 × 109 1.8663 × 109 276 2.2589 × 109 1.9122 × 109 277 2.3131 × 109 1.9616 × 109 278 2.3713 × 109 2.0149 × 109 279 2.4339 × 109 2.0725 × 109 280 2.5013 × 109 2.1351 × 109 281 2.5788 × 109 2.2076 × 109 282 2.6581 × 109 2.2826 × 109 283 2.7444 × 109 2.3649 × 109 284 2.8382 × 109 2.4554 × 109 285 2.9408 × 109 2.5555 × 109 286 3.0526 × 109 2.6661 × 109 287 3.1743 × 109 2.7879 × 109

3.50 REF

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.25 MIN

Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Data Sheet ADN2817/ADN2818 Rev. E | Page 39 of 40 NOTES

ADN2817/ADN2818 Data Sheet Rev. E | Page 40 of 40 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06001-0-1/13(E)