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Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC Preliminary Technical Data ADN2816 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Serial data input: 12.3 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss of lock indicator I 2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 300 mW typical 5 mm × 5 mm 32-lead LFCSP, Pb Free
APPLICATIONS
SONET OC-1/3/12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI, etc. WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers PRODUCT DESCRIPTION The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 12.3 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2816 is available in a compact 5 mm × 5 mm 32-lead chip scale package. FUNCTIONAL BLOCK DIAGRAM 04948-0-001 LOL DATAOUTP/N DRVEE DVCCDRVCC DVEECLKOUTP/N VCC VEECF1 CF2 PIN NIN VREF BUFFER VCOPHASE SHIFTER PHASE DETECT FREQUENCY DETECT DATA RE-TIMING LOOP FILTER LOOP FILTER REFCLKP/N (OPTIONAL) Figure 1.
ADN2816 Preliminary Technical Data Rev. PrA | Page 2 of 27 TABLE OF CONTENTS
REVISION HISTORY
6/04—Revision PrA: Initial Version
Preliminary Technical Data ADN2816 Rev. PrA | Page 3 of 27 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit QUANTIZER—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN – NIN 0.2 2.0 V Input Common Mode Level DC-coupled 2.3 2.5 2.8 V QUANTIZER—AC CHARACTERISTICS Data Rate 12.3 675 Mb/s S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF LOSS OF LOCK DETECT (LOL) VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL De-Assert With respect to nominal 250 ppm LOL Response Time 12.3 Mb/s 4 ms OC-12 1.0 µs ACQUISITION TIME Lock to Data Mode OC-12 2.0 ms OC-3 3.4 ms OC-1 9.8 ms 12.3 Mb/s 40.0 ms Optional Lock to REFCLK Mode 10.0 ms DATA RATE READBACK ACCURACY Coarse Readback (See Table 13) 10 % Fine Readback In addition to REFCLK accuracy Data rate < 20 Mb/s 200 ppm Data rate > 20 Mb/s 100 ppm POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V POWER SUPPLY CURRENT 90 mA OPERATING TEMPERATURE RANGE –40 +85 °C
ADN2816 Preliminary Technical Data Rev. PrA | Page 4 of 27 JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW OC-12 71 108 kHz OC-3 23 35 kHz Jitter Peaking OC-12 0 0.03 dB OC-3 0 0.03 dB Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.002 UI rms 0.01 0.019 UI p-p OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms 0.01 0.011 UI p-p Jitter Tolerance OC-12, 2 23 − 1 PRBS
30 Hz 1 100 UI p-p
300 Hz 1 44 UI p-p
25 kHz 2.5 UI p-p 250 kHz 1 1.0 UI p-p OC-3, 2 23 − 1 PRBS
30 Hz 1 50 UI p-p
300 Hz 1 24 UI p-p
6500 Hz 3.5 UI p-p 65 kHz 1.0 UI p-p 1 Jitter tolerance of the ADN2816 at these jitter frequencies is better than what the test equipment is able to measure.
Preliminary Technical Data ADN2816 Rev. PrA | Page 5 of 27 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit LVDS OUPUT CHARACTERISTICS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing V SE (see Figure 3) 250 400 mV Differential Output Swing V DIFF (see Figure 3) 500 800 mV Output Offset Voltage 1125 1200 1275 mV Output Impedance Differential 100 Ω LVDS Ouputs Timing Rise Time 20% to 80% 100 ps Fall Time 80% to 20% 100 ps Setup Time T S (see Figure 2), OC12 800 ps Hold Time T H (see Figure 2), OC12 800 ps I2C INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage V IH 0.7 VCC V Input Low Voltage V IL 0.3 VCC V Input Current V IN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA Output Low Voltage V OL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING (See Figure 9) SCK Clock Frequency 400 kHz SCK Pulse Width High t HIGH 600 ns SCK Pulse Width Low t LOW 1300 ns Start Condition Hold Time t HD;STA 600 ns Start Condition Setup Time t SU;STA 600 ns Data Setup Time t SU;DAT 100 ns Data Hold Time t HD;DAT 300 ns SCK/SDA Rise/Fall Time T R/TF 20 + 0.1 Cb 1 300 ns Stop Condition Setup Time t SU;STO 600 ns Bus Free Time between a Stop and a Start t BUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN V IL 0 V V IH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 12.3 200 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage V IH 2.0 V Input Low Voltage V IL 0.8 V Input High Current I IH, VIN = 2.4 V 5 µA Input Low Current I IL, VIN = 0.4 V −5 µA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage V OH, IOH = −2.0 mA 2.4 V Output Low Voltage V OL, IOL = 2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
ADN2816 Preliminary Technical Data Rev. PrA | Page 6 of 27 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Rating Supply Voltage (VCC) 4.2 V Minimum Input Voltage (All Inputs) VEE − 0.4 V Maximum Input Voltage (All Inputs) VCC + 0.4 V Maximum Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering 10 s) 300°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-LFCSP , 4-layer board with exposed paddle soldered to VEE θJA = 28°C/W . ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
24 VCC
23 VEE
21 SDA
32 TEST2
20 SCK
19 SADDR5
18 VCC
17 VEE
31 VCC
30 VEE
29 DATAOUTP
28 DATAOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 4. Pin Configuration Table 5. Pin Function Descriptions 2 VCC P Power for Limamp, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 8 VEE P GND for Limamp, LOS.
9 NC No Connect
10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss of Lock Indicator. LVTTL active high. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I
22 NC No Connect
23 VEE P Output Buffer, I
24 VCC P Output Buffer, I 2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Preliminary Technical Data ADN2816 Rev. PrA | Page 9 of 27 TYPICAL PERFORMANCE CHARACTERISTICS
1 A 5 00000 X
Figure 5. Slave Address Configuration Figure 6. I2C Write Data Transfer Figure 7. I2C Read Data Transfer Figure 8. I2C Data Transfer Timing Figure 9. I2C Port Timing Diagram
Table 6. Internal Register Map1 1 All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC Table 8. Control Register, CTRLA1 1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Table 10. Control Register, CTRLC
ADN2816 Preliminary Technical Data Rev. PrA | Page 14 of 27 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accom- modation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.0 MHz at 675 Mb/s.
ADN2816 Preliminary Technical Data Rev. PrA | Page 16 of 27 the ADN2816 is in acquisition mode and de-asserts when the ADN2816 has re-acquired lock. HARMONIC DETECTOR The ADN2816 provides a harmonic detector, which detects whether or not the input data has changed to a lower harmonic of the data rate that the VCO is currently locked onto. For example, if the input data instantaneously changes from OC-12, 622.08Mb/s, to an OC-3, 155.52 Mb/s bit stream, this could be perceived as a valid OC-12 bit stream, because the OC-3 data pattern is exactly 4× slower than the OC-12 pattern. So, if the change in data rate is instantaneous, a 101 pattern at OC-3 would be perceived by the ADN2816 as a 111100001111 pattern at OC-12. If the change to a lower harmonic is instantaneous, a typical CDR could remain locked at the higher data rate. The ADN2816 implements a harmonic detector that automati- cally identifies whether or not the input data has switched to a lower harmonic of the data rate that the VCO is currently locked onto. When a harmonic is identified, the LOL pin is asserted and a new frequency acquisition is initiated. The ADN2816 automatically locks onto the new data rate, and the LOL pin is de-asserted. However, the harmonic detector does not detect higher harmonics of the data rate. If the input data rate switches to a higher harmonic of the data rate the VCO is currently locked onto, the VCO loses lock, the LOL pin is asserted, and a new frequency acquisition is initiated. The ADN2816 automatically locks onto the new data rate. The time to detect lock to harmonic is 16,384 × (T d/ρ) where: 1/Td is the new data rate. For example, if the data rate is switched from OC-12 to OC-3, then Td = 1/155.52 MHz. ρ is the data transition density. Most coding schemes seek to ensure that ρ = 0.5, for example, PRBS, 8B/10B. When the ADN2816 is placed in lock to reference mode, the harmonic detector is disabled. SQUELCH MODE Two squelch modes are available with the ADN2816. Squelch DATAOUT AND CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the squelch input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the squelch function is not required, Pin 27 should be tied to VEE. Squelch DATAOUT OR CLKOUT mode is selected when CTRLC[1] is 1. In this mode, when the squelch input is driven to a high state, the DATAOUT pins are squelched. When the squelch input is driven to a low state, the CLKOUT pins are squelched. This is especially useful in repeater applications, where the recovered clock may not be needed. I2C INTERFACE The ADN2816 supports a 2-wire, I2C compatible, serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADN2816 has two possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address is factory programmed to 1. B5 of the slave address is set by Pin 19, SADDR5. Slave address bits [4:0] are defaulted to all 0s. The slave address consists of the 7 MSBs of an 8-bit word. The LSB of the word sets either a read or write operation (see Figure 5). Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. To control the device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establish- ing a start condition, defined by a high to low transition on SDA while SCK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2816 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. The ADN2816 has 8 subaddresses to enable the user-accessible internal registers (see Table 1 through Table 7). It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then they cause an immediate jump to the idle condition. During a given SCK high
voltage TTL input, providing maximum system flexibility. and 100 ppm accuracy is sufficient. Figure 15. Differential REFCLK Configuration Figure 16. Single-Ended REFCLK Configuration Figure 17. No REFCLK Configuration
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
Table 11. CTRLA Settings
ADN2816 Preliminary Technical Data Rev. PrA | Page 18 of 27 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF, where DIV_FREF represents the divided-down reference referred to the 12.3 MHz to 25 MHz band. For example, if the reference clock frequency was 38.88 MHz and the input data rate was 622.08 Mb/s, then CTRLA[7:6] would be set to [01] to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] would be set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 2 In this mode, if the ADN2816 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2816 is operating in lock to reference mode, if the user ever changes the reference frequency, the FREF range (CTRLA[7:6]), or the FREF ratio (CTRLA[5:2]), this must be followed by writing a 0 to 1 transition into the CTRLA[0] bit to initiate a new lock to reference command. Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2816 compares the frequency of the incoming data to the incoming reference clock and returns a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy of the ADN2816 data rate measurement. For example, if a 100-ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. The reference clock can range from 12.3 MHz and 200 MHz. The ADN2816 expects a reference clock between 12.3 MHz and 25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2816 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2816. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. Step 2: Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Step 3: Read back MISC[2]. If it is 0, then the measurement is not complete. If it is 1, then the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. Step 4: Read back the data rate from registers FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0]. Use the following equation to determine the data rate: []( ) )_14(2/0..22 RATESEL REFCLKDATARATE fFREQf +×= where: FREQ[22:0] is the reading from FREQ2[6:0] (MSByte), FREQ1[7:0], and FREQ0[7:0] (LSByte). Table 12. FREQ2[6:0] FREQ1[7:0] FREQ0[7:0] fDATARATE is the data rate (Mb/s). fREFCLK is the REFCLK frequency (MHz). SEL_RATE is the setting from CTRLA[7:6]. For example, if the reference clock frequency is 32 MHz, SEL_RATE = 1, since the CTRLA[7:6] setting would be [01], because the reference frequency would fall into the 25 MHz to 50 MHz range. Assume for this example that the input data rate is 622.08 Mb/s (OC12). After following Steps 1 through 4, the value that is read back on FREQ[22:0] = 0x9B851, which is equal to 637 x 10 3. Plugging this value into the equation yields If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measurement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Steps 2 through 4 to read back the new data rate. Note: A data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid.
Preliminary Technical Data ADN2816 Rev. PrA | Page 19 of 27 Additional Features Available via the I2C Interface Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately +10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is de-asserted. The 8 MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table 13 provides coarse data rate readback to within ±10%. System Reset A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2816 in the operating mode that it was previously programmed to in registers CTRL[A], CTRL[B], and CTRL[C].
through the vias during reflow. as close as possible to the ADN2816 VCC pins. 18 for recommended connections. εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2. Figure 18. Typical ADN2816 Applications Circuit
skew between the differential traces. with 50 Ω to an internal reference voltage (see Figure 19). provide an ac ground for the inputs. all high speed digital traces away from sensitive analog nodes. Figure 19. ADN2816 AC-Coupled Input Configuration land length and 0.05 mm wider than the package land width. ensures a solid connection from the exposed pad to VEE. choose an ac coupling capacitor based on that amount of droop. require some trade-offs between droop and PDJ. t is the total discharge time, which is equal to nΤ. Note that this expression for tr is accurate only for the inputs.
- DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
- WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
- WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
DOES NOT RECOGNIZE THIS AS A VALID STATE.
- THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2816. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. Figure 20. Example of Baseline Wander
Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table
ADN2816 Preliminary Technical Data Rev. PrA | Page 24 of 27 Code F MID 192 3.3238e+08 193 3.3235e+08 194 3.3876e+08 195 3.4553e+08 196 3.5279e+08 197 3.6048e+08 198 3.6872e+08 199 3.7757e+08 200 3.8703e+08 Code F MID 201 3.9742e+08 202 4.0844e+08 203 4.2032e+08 204 4.3320e+08 205 4.4719e+08 206 4.6248e+08 207 4.7912e+08 208 4.7449e+08 209 4.7447e+08 Code F MID 210 4.8388e+08 211 4.9391e+08 212 5.0465e+08 213 5.1605e+08 214 5.2831e+08 215 5.4135e+08 216 5.5542e+08 217 5.7075e+08 218 5.8711e+08 Code F MID 219 6.0468e+08 220 6.2377e+08 221 6.4437e+08 222 6.6666e+08 223 6.9062e+08 224 6.6476e+08 225 6.6470e+08 226 6.7751e+08 227 6.9106e+08
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
3.50 REF
0.60 MAX
0.25 MIN
Figure 21. 32-Lead Frame Chip Scale Package [LFCSP]
ADN2816 Preliminary Technical Data Rev. PrA | Page 26 of 27 NOTES
Preliminary Technical Data ADN2816 Rev. PrA | Page 27 of 27 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners.