ADN2813ACPZ-RL7

ADN2813_V01 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 28

Technical content

Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp Data Sheet ADN2813 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Serial data input: 10 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typ Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 450 mW typ 5 mm × 5 mm 32-lead LFCSP , Pb free

APPLICATIONS

SONET OC-1/-3/-12 and all associated FEC rates Fibre Channel, GbE, HDTVs WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers GENERAL DESCRIPTION The ADN2813 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati- cally locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front-end, loss-of-signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2813 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM 04951-0-001 SLICEP/N LOL DATAOUTP/NLOSTHRADJ CLKOUTP/N ADN2813 VCC VEECF1 CF2 PIN NIN VREF QUANTIZER VCOPHASE SHIFTER PHASE DETECT FREQUENCY DETECT LOS DETECT DATA RE-TIMING LOOP FILTER LOOP FILTER REFCLKP/N (OPTIONAL) Figure 1.

Rev. C | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

4/14—Rev. B to Rev. C 6/10—Rev. A to Rev. B 2/09—Rev. 0 to Rev. A 9/05—Revision 0: Initial Version

Rev. C | Page 3 of 28 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF , SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit QUANTIZER—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 2.0 V Input Common-Mode Level DC-coupled (see Figure 27, Figure 28, and Figure 29) 2.3 2.5 2.8 V Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10–10 6 3.3 mV p-p Input Offset 500 µV Input RMS Noise BER = 1 × 10–10 290 µV rms QUANTIZER—AC CHARACTERISTICS Data Rate 10 1250 Mb/s S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF QUANTIZER—SLICE ADJUSTMENT Gain SLICEP – SLICEN = ±0.5 V 0.10 0.11 0.13 V/V Differential Control Voltage Input SLICEP – SLICEN −0.95 +0.95 V Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V Slice Threshold Offset 1 mV LOSS-OF-SIGNAL (LOS) DETECT Loss-of-Signal Detect Range (see Figure 6) RTHRESH = 0 Ω 14 16.5 19 mV RTHRESH = 100 kΩ 2.3 3.5 4.7 mV Hysteresis (Electrical) GbE RTHRESH = 0 Ω 6.4 7.2 8.0 dB RTHRESH = 100 kΩ 4.6 6.2 7.8 dB OC-1 RTHRESH = 0 Ω 5.5 6.6 7.7 dB RTHRESH = 10 kΩ 3.1 5.4 7.7 dB LOS Assert Time DC-coupled2 500 ns LOS Deassert Time DC-coupled2 400 ns LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time 10 Mb/s 5 ms OC-12 200 µs GbE 200 µs ACQUISITION TIME Lock-to-Data Mode GbE 1.5 ms OC-12 2.0 ms OC-3 3.4 ms OC-1 9.8 ms 10 Mb/s 40.0 ms Optional Lock to REFCLK Mode 20.0 ms DATA RATE READBACK ACCURACY Coarse Readback See Table 13 10 % Fine Readback In addition to REFCLK accuracy Data rate ≤ 20 Mb/s 200 ppm Data rate > 20 Mb/s 100 ppm

Rev. C | Page 4 of 28 Parameter Conditions Min Typ Max Unit POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V POWER SUPPLY CURRENT Locked to 1.25 Gb/s 139 155 mA OPERATING TEMPERATURE RANGE –40 +85 °C 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2813 input stage. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF , SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW OC-12 75 130 kHz OC-3 26 42 kHz Jitter Peaking OC-12 0 0.03 dB OC-3 0 0.03 dB Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms 0.011 0.026 UI p-p OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms 0.005 0.010 UI p-p Jitter Tolerance 1 GbE, IEEE 802.3 637 kHz 0.749 UI p-p OC-12, 223 − 1 PRBS

30 Hz1 100 UI p-p

300 Hz1 44 UI p-p

25 kHz 2.5 UI p-p 250 kHz1 1.0 UI p-p OC-3, 223 − 1 PRBS

30 Hz1 50 UI p-p

300 Hz1 23.5 UI p-p 6500 Hz 3.5 UI p-p 65 kHz1 1.0 UI p-p 1 Jitter tolerance of the ADN2813 at these jitter frequencies is better than what the test equipment is able to measure.

Rev. C | Page 5 of 28 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High VOH (see Figure 3), 655 Mb/s 1475 mV Output Voltage Low VOL (see Figure 3), 655 Mb/s 925 mV Differential Output Swing VOD (see Figure 3), 655 Mb/s 250 320 400 mV Differential Output Swing VOD (see Figure 3), 1.25 Gb/s 240 300 400 Output Offset Voltage VOS (see Figure 3) 1125 1200 1275 mV Output Impedance Differential 100 Ω LVDS Outputs Timing GbE Rise Time 20% to 80% 115 220 ps Fall Time 80% to 20% 115 220 ps Setup Time TS (see Figure 2), GbE 360 400 440 ps Hold Time TH (see Figure 2), GbE 360 400 440 ps I2C INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage VIH 0.7 VCC V Input Low Voltage VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 11 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time TR/TF 20 + 0.1 Cb1 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between a Stop and a Start tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN VIL 0 V VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 10 160 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH, VIN = 2.4 V 5 µA Input Low Current IIL, VIN = 0.4 V −5 µA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = −2.0 mA 2.4 V Output Low Voltage VOL, IOL = 2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in pF. If mixed with Hs mode devices, faster fall times are allowed.

Rev. C | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF , SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Rating Supply Voltage (VCC) 4.2 V Minimum Input Voltage (All Inputs) VEE − 0.4 V Maximum Input Voltage (All Inputs) VCC + 0.4 V Maximum Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-LFCSP , 4-layer board with exposed paddle soldered to VEE, θJA = 28°C / W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

24 VCC

23 VEE

22 LOS

21 SDA

32 VCC

20 SCK

19 SADDR5

18 VCC

17 VEE

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 5. Pin Configuration Table 5. Pin Function Descriptions 2 VCC P Power for Limiting Amplifier, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 SLICEP AI Differential Slice Level Adjust Input. 7 SLICEN AI Differential Slice Level Adjust Input. 8 VEE P GND for Limiting Amplifier, LOS. 9 THRADJ AI LOS Threshold Setting Resistor. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss-of-Lock Indicator. LVTTL active high. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 22 LOS DO Loss-of-Signal Detect Output. Active high. LVTTL. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. Exposed Pad Pad P Connect to GND. Works as a heat sink. 1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

Figure 6. LOS Comparator Trip Point Programming

1 A 5 00000 X

Figure 7. Slave Address Configuration Figure 8. I2C Write Data Transfer Figure 9. I2C Read Data Transfer Figure 10. I2C Data Transfer Timing Figure 11. I2C Port Timing Diagram

Table 6. Internal Register Map1 1 All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC Table 8. Control Register, CTRLA 1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Table 10. Control Register, CTRLC

Rev. C | Page 15 of 28 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and therefore the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies; therefore, larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accom- modation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.5 MHz at 1.25 Gb/s.

ppm frequency error. This hysteresis is shown in Figure 20. Figure 20. Transfer Function of LOL frequency. This hysteresis is shown in Figure 20. ADN2813 has reacquired lock. typical CDR could remain locked at the higher data rate. automatically locks onto the new data rate. switched from OC-12 to OC-3, then Td = 1/155.52 MHz. ensure that ρ = 0.5, for example, PRBS, 8B/10B. harmonic detector is disabled.

Rev. C | Page 18 of 28 SQUELCH MODE Two SQUELCH modes are available with the ADN2813. SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the SQUELCH function is not required, Pin 27 should be tied to VEE. SQUELCH DATAOUT or CLKOUT mode is selected when CTRLC[1] is 1. In this mode, when the SQUELCH input is driven to a high state, the DATAOUTN/DATA OUTP pins are squelched. When the SQUELCH input is driven to a low state, the CLKOUT pins are squelched. This is especially useful in repeater applications, where the recovered clock may not be needed. I2C INTERFACE The ADN2813 supports a 2-wire, I2C-compatible serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADN2813 has two possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address is factory programmed to 1. B5 of the slave address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are defaulted to all 0s. The slave address consists of the 7 MSBs of an 8-bit word. The LSB of the word either sets a read or write operation (see Figure 7). Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. To control the device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establish- ing a start condition, defined by a high-to-low transition on SDA while SCK remains high. This indicates that an address/ data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2813 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses, plus the R/W bit. The ADN2813 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10). It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Auto-increment mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCK high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADN2813 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while reading back in auto-increment mode, then the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. In a no acknowledge condition, the SDATA line is not pulled low on the ninth pulse. See Figure 8 and Figure 9 for sample read and write data transfers and Figure 10 for a more detailed timing diagram. REFERENCE CLOCK (OPTIONAL) A reference clock is not required to perform clock and data recovery with the ADN2813. However, support for an optional reference clock is provided. The reference clock can be driven differentially or single-ended. If the reference clock is not being used, then REFCLKP should be tied to VCC, and REFCLKN can be left floating or tied to VEE (the inputs are internally terminated to VCC/2). See Figure 21 through Figure 23 for sample configurations. The REFCLK input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended, low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical, and 100 ppm accuracy is sufficient.

Figure 21. Differential REFCLK Configuration Figure 22. Single-Ended REFCLK Configuration Figure 23. No REFCLK Configuration that has a variable frequency (see Application Note AN-632).

40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the

Table 11. CTRLA Settings onto the reference clock and continues to output a stable clock. initiate a new lock-to-reference command. measurement is within 200 ppm.

Rev. C | Page 20 of 28 The reference clock can range from 10 MHz and 160 MHz. The ADN2813 expects a reference clock between 10 MHz and 20 MHz by default. If it is between 20 MHz and 40 MHz,

40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs

to configure the ADN2813 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: 1. Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2813. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. 2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. 3. Read back MISC[2]. If it is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. 4. Read back the data rate from FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0]. The data rate can be determined by [ ]( ) )_(/.. RATESEL REFCLKDATARATE fFREQf +×= 142022 where: FREQ[22:0] is the reading from FREQ2[6:0] MSByte, FREQ1[7:0], and FREQ0[7:0] LSByte (see Table 12). fDATAR ATE is the data rate (Mb/s). fREFCLK is the REFCLK frequency (MHz). SEL_R ATE is the setting from CTRLA[7:6]. For example, if the reference clock frequency is 32 MHz, SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because the reference frequency falls into the 20 MHz to 40 MHz range. Assume for this example that the input data rate is 1.25 Gb/s (GbE). After following Step 1 through Step 4, the value that is read back on FREQ[22:0] = 0x138800, which is equal to 1.28 × 106. Plugging this value into the equation yields 128e6 × 32e6/2(14 + 1) = 1.25 Gb/s If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measurement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Step 2 through Step 4 to read back the new data rate. Note that a data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid. Additional Features Available via the I2C Interface Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately ±10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The eight MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table 13 provides coarse data rate readback to within ±10%. LOS Configuration The LOS detector output, Pin 22, can be configured to be either active high or active low. If CTRLC[2] is set to Logic 0 (default), the LOS pin is active high when a loss-of-signal condition is detected. Writing a 1 to CTRLC[2] configures the LOS pin to be active low when a loss-of-signal condition is detected. System Reset A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2813 in the operating mode that it was previously programmed to in Registers CTRL[A], CTRL[B], and CTRL[C]. Table 12. FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]

through the vias during reflow. as close as possible to the ADN2813 VCC pins. εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2. Figure 24. Typical ADN2813 Applications Circuit

matched in length to avoid skew between the differential traces. with 50 Ω to an internal reference voltage (see Figure 25). provide an ac ground for the inputs. all high speed digital traces away from sensitive analog nodes. Figure 25. ADN2813 AC-Coupled Input Configuration ensures a solid connection from the exposed pad to VEE. choose an ac coupling capacitor based on that amount of droop. require some trade-offs between droop and PDJ. t is the total discharge time, which is equal to nT. r is accurate only for the inputs.

Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table

Rev. C | Page 25 of 28 Code FMID 192 3.4397e+08 193 3.4394e+08 194 3.5067e+08 195 3.5783e+08 196 3.6551e+08 197 3.7370e+08 198 3.8247e+08 199 3.9177e+08 200 4.0179e+08 201 4.1322e+08 202 4.2490e+08 203 4.3758e+08 204 4.5133e+08 205 4.6636e+08 206 4.8272e+08 207 5.0061e+08 Code FMID 208 4.9064e+08 209 4.9062e+08 210 5.0059e+08 211 5.1123e+08 212 5.2267e+08 213 5.3485e+08 214 5.4794e+08 215 5.6195e+08 216 5.7706e+08 217 5.9423e+08 218 6.1189e+08 219 6.3098e+08 220 6.5173e+08 221 6.7423e+08 222 6.9873e+08 223 7.2525e+08 Code FMID 224 6.8793e+08 225 6.8789e+08 226 7.0135e+08 227 7.1567e+08 228 7.3102e+08 229 7.4741e+08 230 7.6493e+08 231 7.8355e+08 232 8.0358e+08 233 8.2643e+08 234 8.4981e+08 235 8.7516e+08 236 9.0266e+08 237 9.3272e+08 238 9.6543e+08 239 1.0012e+09 Code FMID 240 9.8129e+08 241 9.8124e+08 242 1.0012e+09 243 1.0225e+09 244 1.0453e+09 245 1.0697e+09 246 1.0959e+09 247 1.1239e+09 248 1.1541e+09 249 1.1885e+09 250 1.2238e+09 251 1.2620e+09 252 1.3035e+09 253 1.3485e+09 254 1.3975e+09 255 1.4505e+09

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

Figure 30. 32-Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. C | Page 27 of 28 NOTES

Rev. C | Page 28 of 28 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04951-0-4/14(C)