ADN2812

ADN2812 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp Data Sheet ADN2812 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.

FEATURES

Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice level adjust and LOS detector No reference clock required Loss of lock indicator I2C interface to access optional features Single-supply operation: 3.3 V Low power: 750 mW typical 5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2× Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 auto- matically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm × 5 mm 32-lead lead frame chip scale package (LFCSP). FUNCTIONAL BLOCK DIAGRAM 04228-001 SLICEP/N LOL DATAOUTP/NLOSTHRADJ CLKOUTP/N VCC VEECF1 CF2 PIN NIN VREF QUANTIZER VCOPHASE SHIFTER PHASE DETECT FREQUENCY DETECT LOS DETECT DATA RE-TIMING LOOP FILTER LOOP FILTER REFCLKP/N (OPTIONAL) Figure 1.

Rev. E | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

3/12—Rev. D to Rev. E 5/10—Rev. C to Rev. D 2/09—Rev. B to Rev. C 6/07—Rev. A to Rev. B 11/04—Rev. 0 to Rev. A Changes to Using the Reference Clock to Lock onto Data 3/04—Revision 0: Initial Version

Rev. E | Page 3 of 28 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF , SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit QUANTIZER—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN – NIN 2.0 V Input Common-Mode Level DC-coupled (see Figure 28, Figure 29, and Figure 30) 2.3 2.5 2.8 V Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10–10 10 6 mV p-p Input Overdrive (see Figure 12) 5 3 mV p-p Input Offset 500 µV Input RMS Noise BER = 1 x 10–10 290 µV rms QUANTIZER—AC CHARACTERISTICS Data Rate 12.3 2700 Mb/s S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF QUANTIZER—SLICE ADJUSTMENT Gain SLICEP – SLICEN = ±0.5 V 0.08 0.1 0.125 V/V Differential Control Voltage Input SLICEP – SLICEN −0.95 +0.95 V Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V Slice Threshold Offset 1 mV LOSS OF SIGNAL DETECT (LOS) Loss of Signal Detect Range RThresh = 0 Ω (see Figure 5) 11 13 17 mV RThresh = 100 kΩ 1.5 3 4.0 mV Hysteresis (Electrical) OC-48 RThresh = 0 Ω 5.6 6 7.2 dB RThresh = 100 kΩ 3.7 6 8.4 dB OC-1 RThresh = 0 Ω 5.6 6 7.2 dB RThresh = 10 kΩ 2.0 4 6.7 dB LOS Assert Time DC-coupled2 500 ns LOS Deassert Time DC-coupled2 450 ns LOSS OF LOCK DETECT (LOL) VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time 12.3 Mb/s 4 ms OC-12 1.0 µs OC-48 1.0 µs ACQUISITION TIME Lock to Data Mode OC-48 1.3 ms OC-12 2.0 ms OC-3 3.4 ms OC-1 9.8 ms 12.3 Mb/s 40.0 ms Optional Lock to REFCLK Mode 10.0 ms

Rev. E | Page 4 of 28 Parameter Conditions Min Typ Max Unit DATA RATE READBACK ACCURACY Coarse Readback See Table 14 10 % Fine Readback In addition to REFCLK accuracy Data rate ≤ 20 Mb/s 200 ppm Data rate > 20 Mb/s 100 ppm POWER SUPPLY VOLTAGE 3.0 3.3 3.6 V POWER SUPPLY CURRENT 235 259 mA OPERATING TEMPERATURE RANGE –40 +85 °C 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. 2 When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2812 input stage. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF , SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW OC-48 490 670 kHz OC-12 71 108 kHz OC-3 23 35 kHz Jitter Peaking OC-48 0 0.03 dB OC-12 0 0.03 dB OC-3 0 0.03 dB Jitter Generation OC-48, 12 kHz to 20 MHz 0.001 0.002 UI rms 0.02 0.037 UI p-p OC-12, 12 kHz to 5 MHz 0.001 0.002 UI rms 0.01 0.019 UI p-p OC-3, 12 kHz to 1.3 MHz 0.001 0.002 UI rms 0.01 0.011 UI p-p Jitter Tolerance OC-48, 223 − 1 PRBS

600 Hz 70 92 UI p-p

100 kHz 3.8 5 UI p-p 1 MHz 0.75 1 UI p-p 20 MHz 0.4 0.6 UI p-p OC-12, 223 − 1 PRBS

30 Hz1 100 UI p-p

300 Hz1 44 UI p-p

25 kHz 2.5 UI p-p 250 kHz1 1.0 UI p-p OC-3, 223 − 1 PRBS

30 Hz1 50 UI p-p

300 Hz1 24 UI p-p

6500 Hz 3.5 UI p-p 65 kHz 1.0 UI p-p 1 Jitter tolerance of the ADN2812 at these jitter frequencies is better than what the test equipment is able to measure.

Rev. E | Page 5 of 28 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Conditions Min Typ Max Unit CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Single-Ended Output Swing VSE (see Figure 3) 300 350 600 mV Differential Output Swing VDIFF (see Figure 3) 600 700 1200 mV Output High Voltage VOH VCC V Output Low Voltage VOL VCC − 0.6 VCC − 0.35 VCC − 0.3 V CML Outputs Timing Rise Time 20% to 80% 95 112 ps Fall Time 80% to 20% 95 123 ps Setup Time tS (see Figure 2), OC-48 150 200 250 ps Hold Time tH (see Figure 2), OC-48 150 200 250 ps I2C® INTERFACE DC CHARACTERISTICS LVCMOS Input High Voltage VIH 0.7 VCC V Input Low Voltage VIL 0.3 VCC V Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 11 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time tR/tF 20 + 0.1 Cb1 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between a Stop and a Start tBUF 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range @ REFCLKP or REFCLKN VIL 0 V VIH VCC V Minimum Differential Input Drive 100 mV p-p Reference Frequency 12.3 200 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH, VIN = 2.4 V 5 µA Input Low Current IIL, VIN = 0.4 V −5 µA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = −2.0 mA 2.4 V Output Low Voltage VOL, IOL = +2.0 mA 0.4 V 1 Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed (see Table 6).

Rev. E | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V , CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Rating Supply Voltage (VCC) 4.2 V Minimum Input Voltage (All Inputs) VEE − 0.4 V Maximum Input Voltage (All Inputs) VCC + 0.4 V Maximum Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering 10 s) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-LFCSP , 4-layer board with exposed paddle soldered to VEE θJA = 28°C/W . ESD CAUTION

24 VCC

23 VEE

22 LOS

21 SDA

32 VCC

20 SCK

19 SADDR5

18 VCC

17 VEE

31 VCC

30 VEE

29 DATAOUTP

28 DATAOUTN

27 SQUELCH

26 CLKOUTP

25 CLKOUTN

THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 4. Pin Configuration Table 5. Pin Function Descriptions 2 VCC P Power for Limamp, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6 SLICEP AI Differential Slice Level Adjust Input. 7 SLICEN AI Differential Slice Level Adjust Input. 8 VEE P GND for Limamp, LOS. 9 THRADJ AI LOS Threshold Setting Resistor. 10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss of Lock Indicator. LVTTL active high. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 22 LOS DO Loss of Signal Detect Output. Active high. LVTTL. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. CML. 26 CLKOUTP DO Differential Recovered Clock Output. CML. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL. 28 DATAOUTN DO Differential Recovered Data Output. CML. 29 DATAOUTP DO Differential Recovered Data Output. CML. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. Exposed Pad Pad P Connect to GND. Works as a heat sink. 1 P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

1 A5 0 0 0 0 0 X

Figure 7. Slave Address Configuration Figure 8. I2C Write Data Transfer Figure 9. I2C Read Data Transfer Figure 10. I2C Data Transfer Timing Figure 11. I2C Port Timing Diagram

Table 6. Internal Register Map1

0 Reset

1 All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC Table 8. Control Register, CTRLA1 1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Table 10. Control Register, CTRLC

Rev. E | Page 15 of 28 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integra- tor declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 3 MHz at OC-48.

Figure 20. Transfer Function of LOL the divided down VCO and the divided down reference clock. serted when the VCO is within 250 ppm of the desired frequency. frequency. This hysteresis is shown in Figure 20. even after the ADN2812 has reacquired lock to a new data rate. until another loss of lock condition occurs. could remain locked at the higher data rate. automatically locks onto the new data rate. switched from OC-48 to OC-12, then Td = 1/622 MHz. to ensure that ρ = 0.5, for example, PRBS, 8B/10B. the harmonic detector is disabled. Two squelch modes are available with the ADN2812. is not required, Pin 27 should be tied to VEE. driven to a high state, the DATAOUT pins are squelched. cations, where the recovered clock may not be needed.

the user does not know the data rate and wants to measure it.

50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz,

Table 11. CTRLA[7:6] Settings Table 12. CTRLA[5:2] Settings [01] to give a divided-down reference clock of 19.44 MHz. accuracy of the measurement is within 200 ppm. The reference clock can range from 12.3 MHz to 200 MHz.

50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user

the reference clock in this manner.

Rev. E | Page 20 of 28 Prior to reading back the data rate using the reference clock, Control Register CTRLA Bits[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: 1. Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2812. This bit is level-sensitive and does not need to be reset to perform subsequent frequency measurements. 2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. 3. Read back MISC[2]. If it is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. 4. Read back the data rate from Register FREQ2[6:0], Register FREQ1[7:0], and Register FREQ0[7:0]. Use the following equation to determine the data rate: f DATARATE = (FREQ[22:0] × fREFCLK)/2(14 + SEL_RATE) where: FREQ[22:0] is the reading from FREQ2[6:0] (MSByte), FREQ1[7:0], and FREQ0[7:0] (LSByte). fDATAR ATE is the data rate (Mb/s). fREFCLK is the REFCLK frequency (MHz). SEL_R ATE is the setting from CTRLA[7:6]. Table 13. FREQ2[6:0] FREQ1[7:0] FREQ0[7:0] For example, if the reference clock frequency is 32 MHz, SEL_RATE = 1, because the CTRLA[7:6] setting is [01] and the reference frequency falls into the 25 MHz to 50 MHz range. Assume for this example that the input data rate is 2.488 Gb/s (OC-48). After following Step 1 through Step 4, the value that is read back on FREQ[22:0] = 0x26E010, which is equal to 2.5477 × 10 6. Plugging this value into the equation yields If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The meas- urement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Step 2 through Step 4 to read back the new data rate. Note that a data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid. Additional Features Available via the I2C Interface Coarse Data Rate Readback The data rate can be read back over the I2C interface to approxi- mately ±10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The 8 MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table 14 provides coarse data rate readback to within ±10%. LOS Configuration The LOS detector output, LOS (Pin 22), can be configured to be either active high or active low. If CTRLC[2] is set to Logic 0 (default), the LOS pin is active high when a loss of signal condition is detected. Writing a 1 to CTRLC[2] configures the LOS pin to be active low when a loss of signal condition is detected. System Reset A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2812 in the operating mode that it was previously programmed to in Register CTRL[A], Register CTRL[B], and Register CTRL[C].

leak through the vias during reflow. and as close as possible to the ADN2812 VCC pins. εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR-4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2. Figure 24. Typical Applications Circuit

Rev. E | Page 24 of 28 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 14. Code FMID 0 5.1934e+06 1 5.1930e+06 2 5.2930e+06 3 5.3989e+06 4 5.5124e+06 5 5.6325e+06 6 5.7612e+06 7 5.8995e+06 8 6.0473e+06 9 6.2097e+06 10 6.3819e+06 11 6.5675e+06 12 6.7688e+06 13 6.9874e+06 14 7.2262e+06 15 7.4863e+06 16 7.4139e+06 17 7.4135e+06 18 7.5606e+06 19 7.7173e+06 20 7.8852e+06 21 8.0633e+06 22 8.2548e+06 23 8.4586e+06 24 8.6784e+06 25 8.9180e+06 26 9.1736e+06 27 9.4481e+06 28 9.7464e+06 29 1.0068e+07 30 1.0417e+07 31 1.0791e+07 32 1.0387e+07 33 1.0386e+07 34 1.0586e+07 35 1.0798e+07 36 1.1025e+07 37 1.1265e+07 38 1.1522e+07 39 1.1799e+07 40 1.2095e+07 41 1.2419e+07 42 1.2764e+07 43 1.3135e+07 44 1.3538e+07 45 1.3975e+07 46 1.4452e+07 47 1.4973e+07 Code FMID 48 1.4828e+07 49 1.4827e+07 50 1.5121e+07 51 1.5435e+07 52 1.5770e+07 53 1.6127e+07 54 1.6510e+07 55 1.6917e+07 56 1.7357e+07 57 1.7836e+07 58 1.8347e+07 59 1.8896e+07 60 1.9493e+07 61 2.0136e+07 62 2.0833e+07 63 2.1582e+07 64 2.0774e+07 65 2.0772e+07 66 2.1172e+07 67 2.1596e+07 68 2.2049e+07 69 2.2530e+07 70 2.3045e+07 71 2.3598e+07 72 2.4189e+07 73 2.4839e+07 74 2.5527e+07 75 2.6270e+07 76 2.7075e+07 77 2.7950e+07 78 2.8905e+07 79 2.9945e+07 80 2.9655e+07 81 2.9654e+07 82 3.0242e+07 83 3.0869e+07 84 3.1541e+07 85 3.2253e+07 86 3.3019e+07 87 3.3834e+07 88 3.4714e+07 89 3.5672e+07 90 3.6694e+07 91 3.7792e+07 92 3.8985e+07 93 4.0273e+07 94 4.1666e+07 95 4.3164e+07 Code FMID 96 4.1547e+07 97 4.1544e+07 98 4.2344e+07 99 4.3191e+07 100 4.4099e+07 101 4.5060e+07 102 4.6090e+07 103 4.7196e+07 104 4.8378e+07 105 4.9678e+07 106 5.1055e+07 107 5.2540e+07 108 5.4150e+07 109 5.5899e+07 110 5.7810e+07 111 5.9890e+07 112 5.9311e+07 113 5.9308e+07 114 6.0485e+07 115 6.1739e+07 116 6.3081e+07 117 6.4506e+07 118 6.6038e+07 119 6.7669e+07 120 6.9427e+07 121 7.1344e+07 122 7.3388e+07 123 7.5585e+07 124 7.7971e+07 125 8.0546e+07 126 8.3333e+07 127 8.6328e+07 128 8.3095e+07 129 8.3087e+07 130 8.4689e+07 131 8.6383e+07 132 8.8198e+07 133 9.0120e+07 134 9.2179e+07 135 9.4392e+07 136 9.6757e+07 137 9.9356e+07 138 1.0211e+08 139 1.0508e+08 140 1.0830e+08 141 1.1180e+08 142 1.1562e+08 143 1.1978e+08 Code FMID 144 1.1862e+08 145 1.1862e+08 146 1.2097e+08 147 1.2348e+08 148 1.2616e+08 149 1.2901e+08 150 1.3208e+08 151 1.3534e+08 152 1.3885e+08 153 1.4269e+08 154 1.4678e+08 155 1.5117e+08 156 1.5594e+08 157 1.6109e+08 158 1.6667e+08 159 1.7266e+08 160 1.6619e+08 161 1.6617e+08 162 1.6938e+08 163 1.7277e+08 164 1.7640e+08 165 1.8024e+08 166 1.8436e+08 167 1.8878e+08 168 1.9351e+08 169 1.9871e+08 170 2.0422e+08 171 2.1016e+08 172 2.1660e+08 173 2.2360e+08 174 2.3124e+08 175 2.3956e+08 176 2.3724e+08 177 2.3723e+08 178 2.4194e+08 179 2.4695e+08 180 2.5233e+08 181 2.5802e+08 182 2.6415e+08 183 2.7067e+08 184 2.7771e+08 185 2.8538e+08 186 2.9355e+08 187 3.0234e+08 188 3.1188e+08 189 3.2218e+08 190 3.3333e+08 191 3.4531e+08

Rev. E | Page 25 of 28 Code FMID 192 3.3238e+08 193 3.3235e+08 194 3.3876e+08 195 3.4553e+08 196 3.5279e+08 197 3.6048e+08 198 3.6872e+08 199 3.7757e+08 200 3.8703e+08 201 3.9742e+08 202 4.0844e+08 203 4.2032e+08 204 4.3320e+08 205 4.4719e+08 206 4.6248e+08 207 4.7912e+08 208 4.7449e+08 209 4.7447e+08 210 4.8388e+08 211 4.9391e+08 212 5.0465e+08 213 5.1605e+08 214 5.2831e+08 215 5.4135e+08 Code FMID 216 5.5542e+08 217 5.7075e+08 218 5.8711e+08 219 6.0468e+08 220 6.2377e+08 221 6.4437e+08 222 6.6666e+08 223 6.9062e+08 224 6.6476e+08 225 6.6470e+08 226 6.7751e+08 227 6.9106e+08 228 7.0558e+08 229 7.2096e+08 230 7.3743e+08 231 7.5514e+08 232 7.7405e+08 233 7.9485e+08 234 8.1688e+08 235 8.4064e+08 236 8.6640e+08 237 8.9438e+08 238 9.2496e+08 239 9.5825e+08 Code FMID 240 9.4898e+08 241 9.4893e+08 242 9.6776e+08 243 9.8782e+08 244 1.0093e+09 245 1.0321e+09 246 1.0566e+09 247 1.0827e+09 248 1.1108e+09 249 1.1415e+09 250 1.1742e+09 251 1.2094e+09 252 1.2475e+09 253 1.2887e+09 254 1.3333e+09 255 1.3812e+09 256 1.3295e+09 257 1.3294e+09 258 1.3550e+09 259 1.3821e+09 260 1.4112e+09 261 1.4419e+09 262 1.4749e+09 263 1.5103e+09 Code FMID 264 1.5481e+09 265 1.5897e+09 266 1.6338e+09 267 1.6813e+09 268 1.7328e+09 269 1.7888e+09 270 1.8499e+09 271 1.9165e+09 272 1.8980e+09 273 1.8979e+09 274 1.9355e+09 275 1.9756e+09 276 2.0186e+09 277 2.0642e+09 278 2.1132e+09 279 2.1654e+09 280 2.2217e+09 281 2.2830e+09 282 2.3484e+09 283 2.4187e+09 284 2.4951e+09 285 2.5775e+09 286 2.6666e+09 287 2.7625e+09

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. E | Page 27 of 28 NOTES

Rev. E | Page 28 of 28 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04228-0-3/12(E)