ADN2807

ADN2807 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 21

Technical content

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amplifier Data Sheet ADN2807 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or

155.52 MHz REFCLK

REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible (LVPECL/LVDS only at 155.52 MHz) Optional 19.44 MHz on-chip oscillator to be used with external crystal Loss-of-lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm × 7 mm, 48-lead LFCSP

APPLICATIONS

SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Passive optical networks GENERAL DESCRIPTION The ADN2807 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, and 15/14 FEC. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for –40°C to +85°C ambient temperature, unless otherwise noted. The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both native rates and 15/14 rate digital wrappers are supported by the ADN2807, without any change of reference clock. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2807 is available in a compact 7 mm × 7 mm 48-lead chip-scale package (LFCSP). FUNCTIONAL BLOCK DIAGRAM LEVEL DETECT DATA RETIMING DIVIDER 1/2/4/16 FRACTIONAL DIVIDER FREQUENCY LOCK DETECTOR LOOP FILTER PHASE SHIFTER PHASE DET. VCO XTAL OSC LOOP FILTERQUANTIZER ADN2807 SLICEP/N VCC VEE CF1 CF2 LOL REFSEL[0..1] REFCLKP/N XO1 XO2 REFSEL SEL[0..2]CLKOUTP/NDATAOUTP/NSDOUTTHRADJ VREF NIN PIN 03877-0-001 Figure 1.

Rev. B | Page 2 of 21 TABLE OF CONTENTS

REVISION HISTORY

5/16—Rev. A to Rev. B 5/04—Rev. 0 to Rev. A 1/04—Revision 0: Initial Version

Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted

Rev. B | Page 4 of 21 Parameter Test Conditions/Comments Min Typ Max Unit PHASE-LOCKED LOOP CHARACTERISTICS PIN – NIN = 10 mV p-p Jitter Transfer BW OC-12 140 200 kHz OC-3 48 85 kHz Jitter Peaking OC-12 0.004 dB OC-3 0.002 dB Jitter Generation OC-12, 12 kHz to 5 MHz 0.003 UI rms 0.02 0.04 UI p-p OC-3, 12 kHz to 1.3 MHz 0.002 UI rms 0.02 0.04 UI p-p Jitter Tolerance OC-12

30 Hz3 100 UI p-p

300 Hz 44 UI p-p

25 kHz 5.8 UI p-p 250 kHz3 1.0 UI p-p OC-3

30 Hz3 50 UI p-p

300 Hz3 23.5 UI p-p 6500 Hz 6.0 UI p-p 65 kHz3 1.0 UI p-p CML OUTPUTS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing VSE (See Figure 7) 400 488 540 mV Differential Output Swing VDIFF (See Figure 7) 850 975 1100 mV Output High Voltage VOH VCC V Output Low Voltage VOL, referred to VCC –0.60 –0.30 V Rise Time 20% to 80% 150 ps Fall Time 80% to 20% 150 ps Setup Time TS (See Figure 3) OC-12 750 ps OC-3 3145 ps Hold Time TH (See Figure 3) OC-12 750 ps OC-3 3150 ps REFCLK DC INPUT CHARACTERISTICS Input Voltage Range At REFCLKP or REFCLKN 0 VCC V Peak-to-Peak Differential Input 100 mV Common-Mode Level DC-coupled, single-ended VCC/2 V TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N) CML inputs Peak-to-Peak Differential Input Voltage 0.8 V LVTTL DC INPUT CHARACTERISTICS Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input Current VIN = 0.4 V or VIN = 2.4 V –5 +5 µA Input Current (SEL0 and SEL1 Only)5 VIN = 0.4 V or VIN = 2.4 V –5 +50 µA LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage VOH, IOH = –2.0 mA 2.4 V Output Low Voltage VOL, IOL = +2.0 mA 0.4 V 1PIN and NIN should be driven differentially, ac-coupled for optimum sensitivity. 2PWD measurement made on quantizer outputs in BYPASS mode. 3Jitter tolerance measurements are equipment limited. 4TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled. 5SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.

Rev. B | Page 5 of 21 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage (VCC) 5.5 V Minimum Input Voltage (All Inputs) VEE – 0.4 V Maximum Input Voltage (All Inputs) VCC + 0.4 V Maximum Junction Temperature 165°C Storage Temperature –65°C to +150°C Lead Temperature (Soldering 10 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LFCSP , 4-layer board with exposed paddle soldered to VCC. θJA = 25°C/W . ESD CAUTION

1. EXPOSED PAD IS TIED OFF TO VCC PLANE WITH VIAS.

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 THRADJ AI LOS Threshold Setting Resistor. 2, 26, 28 VCC P Analog Supply. 4 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor. 5 PIN AI Differential Data Input. 6 NIN AI Differential Data Input. 7 SLICEP AI Differential Slice Level Adjust Input. 8 SLICEN AI Differential Slice Level Adjust Input. 10 LOL DO Loss-of-Lock Indicator. LVTTL active high. 11 XO1 AO Crystal Oscillator. 12 XO2 AO Crystal Oscillator. 13 REFCLKN DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). 14 REFCLKP DI Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). 15 REFSEL DI Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL. 17 TDINP AI Differential Test Data Input. CML. 18 TDINN AI Differential Test Data Input. CML. 20, 47 VCC P Digital Supply. 21 CF1 AO Frequency Loop Capacitor. 23 REFSEL1 DI Reference Frequency Select (See Table 6) LVTTL. 24 REFSEL0 DI Reference Frequency Select (See Table 6) LVTTL. 25 CF2 AO Frequency Loop Capacitor. 30 SEL1 DI Data Rate Select (See Table 5) LVTTL. 32 SEL0 DI Data Rate Select (See Table 5) LVTTL. 35, 36 VCC P Output Driver Supply. 37 DATAOUTN DO Differential Retimed Data Output. CML. 38 DATAOUTP DO Differential Retimed Data Output. CML. 39 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 40 CLKOUTN DO Differential Recovered Clock Output. CML. 41 CLKOUTP DO Differential Recovered Clock Output. CML. 44 BYPASS DI Bypass CDR Mode. Active high. LVTTL. 45 SDOUT DO Loss-of-Signal Detect Output. Active high. LVTTL. 48 LOOPEN DI Enable Test Data Inputs. Active high. LVTTL. Not applicable EPAD FP Exposed Pad. Exposed pad is tied off to VCC plane with vias. 1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, FP = floating pad.

separate feedback loops that share a common control voltage. the static phase error will be driven to zero. and, therefore, does not appear in the closed-loop transfer function. jitter peaking is minimized. contribute to hazardous jitter accumulation. Figure 13. Phase-Locked Loop/Delay-Locked Loop Architecture and phase-locked loops contribute to overall jitter accommodation. contributes little to the low frequency jitter accommodation.

in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. and little tuning of the phase shifter can be expected. Figure 14. Jitter Response vs. Conventional Phase-Locked Loop

Figure 19. Test Modes squelch function is not required, the pin must be tied to VEE. feature can help the system to deal with nonstandard bit rates. and LOOPEN pins are set to Logic 1 at the same time.

Rev. B | Page 16 of 21

APPLICATION INFORMATION

Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane to both analog and digital grounds is recommended. The VEE pins must be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias may be used in parallel to reduce the series inductance, especially on Pins 33 and 34, which are the ground returns for the output buffers. Use of a 10 µF electrolytic capacitor between VCC and GND is recommended at the location where the 3.3 V supply enters the PCB. Use of 0.1 µF and 1 nF ceramic chip capacitors must be placed between IC power supply VCC and GND as close as possible to the ADN2807 VCC pins. Again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on Pins 35 and 36, which supply power to the high speed CLKOUTP/N and DATAOUTP/N output buffers. Refer to the schematic in Figure 20 for recommended connections. Transmission Lines Use of 50 Ω transmission lines are required for all high frequency input and output signals to minimize reflections, including PIN, NIN, CLKOUTP , CLKOUTN, DATAOUTP , and DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It is also recommended that the PIN/NIN input traces are matched in length and that the CLKOUTP/N and DATAOUTP/ N traces are matched in length. All high speed CML outputs, CLKOUTP/N and DATAOUTP/N, also require 100 Ω back termination chip resistors connected between the output pin and VCC. These resistors must be placed as close as possible to the output pins. These 100 Ω resistors are in parallel with on- chip 100 Ω termination resistors to create a 50 Ω back termination (Figure 21). The high speed inputs, PIN and NIN, are internally terminated with 50 Ω to an internal reference voltage (Figure 22). A 0.1 µF capacitor is recommended between VREF (Pin 4) and GND to provide an ac ground for the inputs. As with any high speed mixed-signal design, care must be taken to keep all high speed digital traces away from sensitive analog nodes. Soldering Guidelines for Chip Scale Package The leads on the 48-lead LFCSP are rectangular. The printed circuit board pad for these must be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. The land must be centered on the pad. This ensures that solder joint size is maximized. The bottom of the LFCSP has a central exposed pad. The pad on the printed circuit board must be at least as large as this exposed pad. The user must connect the exposed pad to analog VCC. If vias are used, they must be incorporated into the pad at 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. copper to plug the via.

with the two 50 Ω resistors in the signal path must be considered. periods of CIDs, and where baseline wander cannot be tolerated. outputs and the ADN2807 inputs.

• The ADN2807 is locked to the input data stream; LOL = 0.
• The input data stream is lost due to a break in the link. The VCO frequency drifts until the frequency error is greater than 1000 ppm. LOL is asserted to a Logic 1 as control of the VCO is passed back to the frequency loop.
• The frequency loop pulls the VCO to within 500 ppm of the center frequency. Control of the VCO is passed back to the phase loop and LOL is deasserted to Logic 0.
• The phase loop tries to acquire, but there is no input data present so the VCO frequency drifts.
• The VCO frequency drifts until the frequency error is greater than 1000 ppm. LOL is asserted to a Logic 1 as control of the VCO is passed back to the frequency loop. This process is repeated until a valid input data stream is re-established. 50Ω ADN2807 NIN PIN 50Ω VREF CIN CIN V2V1 V2bV1b TIA LIMAMP CDR COUT COUT DATAOUTP DATAOUTN 4321 V1b V2b VDIFF VDIFF = V2–V2b VTH = ADN2807 QUANTIZERTHRESHOLD VREF VTH NOTES 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0. 2. WHENTHE OUTPUT OFTHE TIA GOESTO CID, V1 AND V1b ARE DRIVENTO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGETO THE VREF LEVEL,WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSSTHE AC COUPLING CAPACITORS. 3. WHENTHE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSSTHE AC COUPLING CAPACITORS IS APPLIEDTO THE INPUT LEVELS, CAUSING A DC SHIFT INTHE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCHTHAT ONE OFTHE STATES, EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHENTHE TIA WENTTO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZETHIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTILTHE DIFFERENTIAL INPUT VOLTAGE EXCEEDSTHE SENSITIVITY OFTHE ADN2807.THE QUANTIZER WILL BE ABLETO RECOGNIZE BOTH HIGH AND LOW STATES ATTHIS POINT. 03877-0-023

Figure 23. Example of Baseline Wander

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

0.02 NOM

0.25 MIN

0.20 REF

Figure 27. 48-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. B | Page 21 of 21 NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03877-0-5/16(B)