ADN2530

ADN2530 (Rev. D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 18

Technical content

11.3 Gbps, Active Back-Termination,

Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Up to 11.3 Gbps operation −40°C to +100°C operation Very low power: ISUPPLY = 65 mA Typical 26 ps rise/fall times Full back-termination of output transmission lines Crosspoint adjust function PECL-/CML-compatible data inputs Bias current range: 2 mA to 25 mA Differential modulation current range: 2.2 mA to 23 mA Automatic laser shutdown (ALS)

3.3 V operation

Compact 3 mm × 3 mm LFCSP Voltage-input control for bias and modulation currents XFP-compliant bias current monitor

APPLICATIONS

10 Gb Ethernet optical transceivers

10G-BASE-LRM optical transceivers 8× and 10× Fibre Channel optical transceivers XFP/X2/XENPAK/MSA 300 optical modules SONET OC-192/SDH STM-64 optical transceivers GENERAL DESCRIPTION The ADN2530 laser diode driver is designed for direct modula- tion of packaged VCSELs with a differential resistance ranging from 35 Ω to 140 Ω. The active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. The back-termination in the ADN2530 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. The small package provides the optimum solution for compact modules where laser diodes are packaged in low pin count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. The eye crosspoint in the output eye diagram is adjustable via the crosspoint adjust (CPA) control voltage input. The automatic laser shutdown (ALS) feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with the proper logic levels. The product is available in a space-saving 3 mm × 3 mm LFCSP specified from −40°C to +100°C. FUNCTIONAL BLOCK DIAGRAM 05457-001 100Ω 200Ω 800Ω 200Ω 10Ω VCCDATAP DATAN MSET GND BSET IBMON IBIAS IMODP IMODN ADN2530 VCC ALS GND VCC VCC 50Ω 50Ω CPA 200Ω 800Ω CROSS POINT ADJUST IMOD Figure 1.

Rev. D | Page 2 of 18 TABLE OF CONTENTS

REVISION HISTORY

7/2017—Rev. C to Rev. D Ch 16—Rev. B to Rev. C —Rev. A to Rev. B 8/2006—Re v. 0 to Rev. A /2005—Revision 0: Initial Version

Rev. D | Page 3 of 18 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted. Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments BIAS CURRENT (IBIAS) Bias Current Range 2 25 mA Bias Current While ALS Asserted 50 µA ALS = high Compliance Voltage1 0.55 VCC − 1.3 V IBIAS = 25 mA 0.55 VCC − 0.8 V IBIAS = 2 mA MODULATION CURRENT (IMODP , IMODN) Modulation Current Range 2.2 23 mA diff RLOAD = 35 Ω to 100 Ω differential 2.2 19 mA diff RLOAD = 140 Ω differential Modulation Current While ALS Asserted 250 µA diff ALS = high Crosspoint Adjust (CPA) Range2 35 65 % Rise Time (20% to 80%)2, 3, 4 26 32.5 ps CPA disabled 26.4 34.7 ps CPA 35% to 65% Fall Time (20% to 80%)2, 3, 4 26 32.5 ps CPA disabled 26.5 33.7 ps CPA 35% to 65% Random Jitter2, 3, 4 <0.5 ps rms CPA disabled <0.5 ps rms CPA 35% to 65% Deterministic Jitter2, 4, 5 5.4 8.2 ps p-p 10.7 Gbps, CPA disabled 5.8 8.2 ps p-p 10.7 Gbps, CPA 35% to 65% Deterministic Jitter 2, 4, 6 5.4 8.2 ps p-p 11.3 Gbps, CPA disabled 5.8 8.2 ps p-p 11.3 Gbps, CPA 35% to 65% Differential |S22| −5 dB 5 GHz < f < 10 GHz, Z0 = 100 Ω differential −13.6 dB f < 5 GHz, Z0 = 100 Ω differential Compliance Voltage1 VCC − 0.7 VCC + 0.7 V DATA INPUTS (DATAP , DATAN) Input Data Rate 11.3 Gbps NRZ Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled Differential |S11| −15 dB f < 10 GHz, Z0 = 100 Ω differential Input Termination Resistance 85 100 115 Ω Differential BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain 15 20 24 mA/V BSET Input Resistance 800 1000 1200 Ω MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain 14 19 23 mA/V MSET Input Resistance 800 1000 1200 Ω BIAS MONITOR (IBMON) IBMON to IBIAS Ratio 50 µA/mA Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % IBIAS = 2 mA, RIBMON = 750 Ω −4.3 +4.3 % IBIAS = 4 mA, RIBMON = 750 Ω −3.5 +3.5 % IBIAS = 8 mA, RIBMON = 750 Ω −3.0 +3.0 % IBIAS = 14 mA, RIBMON = 750 Ω −2.5 +2.5 % IBIAS = 25 mA, RIBMON = 750 Ω AUTOMATIC LASER SHUTDOWN (ALS) VIH 2.4 V VIL 0.8 V IIL −20 +20 µA IIH 0 200 µA

Rev. D | Page 5 of 18 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage, VCC to GND −0.3 V to +4.2 V IMODP , IMODN to GND VCC − 1.5 V to +4.5 V DATAP, DATAN to GND VCC − 1.8 V to VCC − 0.4 V All Other Pins −0.3 V to VCC + 0.3 V Junction Temperature 150°C Storage Temperature Range −65°C to +150°C Soldering Temperature (<10 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. THERE IS AN EXPOSED PAD ON THE

CONNECTED TO THE VCC OR GND PLANE. Figure 4. Pin Configuration Table 4. Pin Function Descriptions

1 MSET Input Modulation Current Control Input

2 CPA Input Crosspoint Adjust Control Input

3 ALS Input Automatic Laser Shutdown

4 GND Power Negative Power Supply

5 VCC Power Positive Power Supply

6 IMODN Output Modulation Current Negative Output

7 IMODP Output Modulation Current Positive Output

8 VCC Power Positive Power Supply

9 GND Power Negative Power Supply

10 IBIAS Output Bias Current Output

11 IBMON Output Bias Current Monitoring Output

12 BSET Input Bias Current Control Input

13 VCC Power Positive Power Supply

14 DATAP Input Data Signal Positive Input

15 DATAN Input Data Signal Negative Input

16 VCC Power Positive Power Supply

Figure 17. Total Supply Current vs. IMOD Figure 18. Worst Case Rise Time Distribution Figure 19. Worst Case Fall Time Distribution

1 LEVEL 1 LEVEL

0 LEVEL 0 LEVEL

Figure 20. Electrical Eye Diagram Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL

TJ is the IC junction temperature in degrees Celsius. P is the ADN2530 power dissipation in watts. θJ-TOP is the thermal resistance from IC junction to package top. TTOP is the temperature at top of package in degrees Celsius. Figure 38. Electrical Model for Thermal Calculations top and paddle temperatures. θJ-TOP and θJ-PAD are given in Table 2.

Rev. D | Page 16 of 18 DESIGN EXAMPLE This design example covers:

• Headroom calculations for IBIAS, IMODP , and IMODN pins.
• Calculation of the typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents.
• Calculations of the IBIAS monitor accuracy over the IBIAS current range. This design example assumes that the impedance of the TOSA is 60 Ω, the forward voltage of the VCSEL at low current is V F = 1.2 V , IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V . Headroom Calculations To ensure proper device operation, the voltages on the IBIAS, IMODP , and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 39, the voltage at the IBIAS pin can be written as VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. For proper operation, the minimum voltage at the IBIAS pin must be greater than 0.55 V , as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 50 Ω transmission lines is negligible and that V LA = 0 V, VF = 1 . 2 V, and IBIAS = 10 mA, VIBIAS = 1.5 V > 0.55 V, which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by VCOMPLIANCE_MAX = VCC − 0.75 − 22 × IBIAS (A) For this example, VCOMPLIANCE_MAX = VCC – 0.75 − 22 × 0.01 = 2.33 V VIBIAS = 1.5 V < 2.33 V, which satisfies the requirement To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD × 50 Ω, as R TOSA < 100 Ω. For proper operation of the ADN2530, the voltage at each modulation output pin must be within the normal operation region shown in Figure 35. Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V and IMOD = 10 mA, the minimum voltage at the modulation output pins is equal to VCC − (IMOD × 50)/2 = VCC − 0.25 VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement The maximum voltage at the modulation output pins is equal to VCC + (IMOD × 50)/2 = VCC + 0.25 VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions. BSET and MSET Pin Voltage Calculation To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2530 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA and the typical IBIAS/VBSET ratio of 20 mA/V , the BSET voltage is given by V5.020 mA/V20 (mA) === IBIASVBSET The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using K IMODVMSET = where K is the MSET voltage to IMOD ratio. The value of K depends on the actual resistance of the TOSA and can be obtained from Figure 34. For a TOSA resistance of 60 Ω, the typical value of K = 24 mA/V . Assuming that IMOD = 10 mA and using the preceding equation, the MSET voltage is given by V42.024 mA/V24 (mA) === IMODVMSET The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 34.

Figure 40. Accuracy of IBIAS to IBMON Ratio the Table 1 and is plotted in Figure 40. maximum IBIAS value of 14 mA. sources to calculate an overall accuracy for the IBMON voltage.

Rev. D | Page 18 of 18 OUTLINE DIMENSIONS 0.30 0.23 0.18 1.75 1.60 SQ 1.45 3.10 3.00 SQ 2.90 0.50 BSC BOTTOM VIEWTOP VIEW 0.50 0.40 0.30

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

0.08 PIN 1 INDICATOR 0.80 0.75 0.70 COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. PKG-005138 SEATING PLANE TOP VIEW EXPOSED PAD 02-23-2017-E PIN 1 INDICA TOR AREA OPTIONS (SEE DETAIL A) DETAIL A (JEDEC 95) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. F igure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADN2530YCPZ-500R7 −40°C to +100°C 16-Lead Lead Frame Chip Scale Package [LFCSP],

500 Piece Reel

ADN2530YCPZ-REEL7 −40°C to +100°C 16-Lead Lead Frame Chip Scale Package [LFCSP],

1500 Piece Reel

1 Z = RoHS Compliant Part. ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05457-0-7/17(D)