ADN2526 AD | Alldatasheet
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11.3 Gbps Active Back-Termination,
Differential Laser Diode Driver ADN2526 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
3.3 V operation
Up to 11.3 Gbps operation Typical 24 ps rise/fall times Full back-termination of output transmission lines Drives TOSAs with resistances ranging from 5 Ω to 50 Ω Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Voltage input control for bias and modulation currents Data inputs sensitivity: 150 mV p-p diff Automatic laser shutdown (ALS) Cross point adjustment (CPA) XFP-compliant bias current monitor SFP+ MSA compliant Optical evaluation board available Compact 3 mm × 3 mm LFCSP
APPLICATIONS
SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules GENERAL DESCRIPTION The ADN2526 laser diode driver is designed for direct modula- tion of packaged laser diodes that have a differential resistance ranging from 5 Ω to 50 Ω. The active back-termination in the ADN2526 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. ADN2526 is an SFP+ MSA- compliant device, and its small package and enhanced ESD protection provide the optimum solution for compact modules where laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average optical power and extinction ratio control schemes, including closed-loop or look-up table control. The automatic laser shutdown (ALS) feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with a LVT TL logic source. The product is available in a space-saving 3 mm × 3 mm LFCSP specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM 50Ω 200Ω 800Ω 200Ω 2Ω VCC DATAP DATAN MSET VEE BSET IBMON IBIAS IMODP IMODN ADN2526 VCC ALS VCC CPA GND VCC 50Ω 50Ω 200Ω 800Ω IMOD CROSS POINT ADJUST 07511-001 Figure 1.
Rev. A | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
8/09—Rev. 0 to Rev. A 1/09—Revision 0: Initial Version
Rev. A | Page 3 of 16 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at TA = 25°C, IMODD 1 = 40 mA, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments BIAS CURRENT (IBIAS) Bias Current Range 10 100 mA Bias Current While ALS Asserted 300 μA ALS = high Compliance Voltage2 0.6 VCC V IBIAS = 100 mA
0.6 VCC V IBIAS = 10 mA
MODULATION CURRENT (IMODP , IMODN) Modulation Current Range 10 80 mA diff RLOAD = 5 Ω to 50 Ω differential Modulation Current While ALS Asserted 0.5 mA diff ALS = high Rise Time (20% to 80%)3, 4 24 32.5 ps Fall Time (20% to 80%)3, 4 24 32.5 ps Random Jitter3, 4 0.4 0.9 ps rms Deterministic Jitter3, 5 7.2 12 ps p-p Includes pulse width distortion Pulse Width Distortion3, 4 2 5 ps PWD = (|THIGH – TLOW|)/2 Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential −14 dB f < 5 GHz, Z0 = 50 Ω differential Compliance Voltage2 VCC − 1.1 VCC + 1.1 V DATA INPUTS (DATAP , DATAN) Input Data Rate 11.3 Gbps NRZ Differential Input Swing 0.15 1.6 V p-p diff Differential, ac-coupled Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential Input Termination Resistance 100 Ω Differential BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain 90 mA/V BSET Input Resistance 1000 Ω MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain 50 78 100 mA/V See Figure 29 MSET Input Resistance 1000 Ω BIAS MONITOR (IBMON) IBMON to IBIAS Ratio 10 μA/mA Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ −4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ −2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ −2 +2 % 70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ AUTOMATIC LASER SHUTDOWN (ALS) VIH 2.0 V VIL 0.8 V IIL −30 +30 μA IIH 0 200 μA ALS Assert Time 2 μs Rising edge of ALS to falling edge of IBIAS and IMOD below 10% of nominal, see Figure 2 ALS Negate Time 10 μs Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal, see Figure 2
1 IMOD is the total modulation current sink capability for a differential driver. IMOD = IMODP + IMODN, the dynamic current sank by the IMODP and IMODN pins. 2 Refers to the voltage between the pin for which the compliance voltage is specified and VEE. 3 The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps. 4 Measured using the high speed characterization circuit shown in Figure 3. 6 Only includes current in the VCC pins. 7 Without laser diode loaded. Figure 2. ALS Timing Diagram
Figure 3. High Speed Characterization Circuit
Rev. A | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VEE connected to supply ground. Table 3. Parameter Rating Supply Voltage, VCC to VEE −0.3 V to +4.2 V IMODP , IMODN to VEE 1.1 V to 4.75 V DATAP , DATAN to VEE VCC − 1.8 V to VCC − 0.4 V All Other Pins −0.3 V to VCC + 0.3 V HBM ESD on IMODP , IMODN 200 V HBM ESD on All Other Pins 1 kV Junction Temperature 150°C Storage Temperature Range −65°C to +150°C Soldering Temperature (Less Than 10 sec) 300°C ESD CAUTION
11 IBMON
12 BSET
10 IBIAS
- THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VCC OR THE GND PLANE. Figure 4. Pin Configuration Table 4. Pin Function Descriptions 1 MSET AI Modulation Current Control Input. 2 CPA AI Adjustable Cross Point. Defaults to not connected (NC) mode (floating). 3 ALS DI Automatic Laser Shutdown. 4 VEE P Negative Power Supply. Normally connected to system ground. 5 VCC P Positive Power Supply. 6 IMODN AI Modulation Current Sink, Negative. 7 IMODP AI Modulation Current Sink, Positive. 8 VCC P Positive Power Supply. 9 VEE P Negative Power Supply. Normally connected to system ground. 10 IBIAS AI Bias Current Sink. 11 IBMON AO Bias Current Monitoring Output. 12 BSET AI Bias Current Control Input. 13 VCC P Positive Power Supply. 14 DATAP AI Data Signal Positive Input. 15 DATAN AI Data Signal Negative Input. 16 VCC P Positive Power Supply. 17 (EPAD) Exposed Pad (EPAD) P The exposed pad on the bottom of the package must be connected to VCC or the GND plane. 1 AI = analog input, DI = digital input, P = power, AO = analog output.
Rev. A | Page 15 of 16 DESIGN EXAMPLE This design example covers:
- Headroom calculations for the IBIAS, IMODP , and IMODN pins.
- Calculation of the typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents. This design example assumes that the resistance of the TOSA is 25 Ω, the forward voltage of the laser at low current is V F = 1 V , IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V . Headroom Calculations To ensure proper device operation, the voltages on the IBIAS, IMODP , and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 34, the voltage at the IBIAS pin can be written as VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V , as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 25 Ω transmission lines is negligible and that V LA = 0 V , VF = 1 V , and IBIAS = 40 mA VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement. The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS (2) For this example, VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement. To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC, due to the ac-coupled configuration, and a swing equal to IMOD × 25 Ω. For proper operation of the ADN2526, the voltage at each modulation output pin should be within the normal operation region shown in Figure 30. VLB is the dc voltage drop across L1, L2, L3, and L4. Assuming that VLB = 0 V and IMOD = 60 mA, the minimum voltage at the modulation output pins is equal to VCC − (IMOD × 25)/2 = VCC − 0.75 VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement. The maximum voltage at the modulation pins is equal to VCC + (IMOD × 25)/2 = VCC + 0.75 VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement. Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions. BSET and MSET Pin Voltage Calculation To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2526 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and the typical IBIAS/V BSET ratio of 100 mA/V , the BSET voltage is given by V 4 . 0100 mA/V 100 (mA) = == IBIASVBSET The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using K IMODVMSET = where K is the MSET voltage to IMOD ratio. The value of K depends on the actual resistance of the TOSA. It can be read using the plot shown in Figure 29. For a TOSA resistance of 25 Ω, the typical value of K is equal to 120 mA/V . Assuming that IMOD = 60 mA and using the preceding equation, the MSET voltage is given by V 5 . 0120 mA/V 120 (mA) = == IMODVMSET The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 29.
EXCEPT FOR EXPOSED PAD DIMENSION.
0.60 MAX
1.50 REF
0.25 MIN
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.