ADN2525

ADN2525 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

10.7 Gbps Active Back-Termination,

Differential Laser Diode Driver Data Sheet ADN2525 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Up to 10.7 Gbps operation Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA) Typical 24 ps rise/fall times Full back-termination of output transmission lines Compatible with XMD-MSA TOSA Drives TOSAs with resistances ranging from 5 Ω to 50 Ω PECL-/CML-compatible data inputs Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Automatic laser shutdown (ALS)

3.3 V operation

Compact 3 mm × 3 mm LFCSP Voltage input control for bias and modulation currents XFP-compliant bias current monitor Optical evaluation board available

APPLICATIONS

SONET OC-192 optical transceivers SDH STM-64 optical transceivers

10 Gb Ethernet optical transceivers

XFP/X2/XENPAK/XPAK/MSA 300 optical modules SR and VSR optical links GENERAL DESCRIPTION The ADN2525 laser diode driver is designed for direct modula- tion of packaged laser diodes having a differential resistance ranging from 5 Ω to 50 Ω. The active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. The back-termination in the ADN2525 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. The small package provides the optimum solution for compact modules where laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. The automatic laser shutdown (ALS) feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with the proper logic levels. The product is available in a space-saving 3 mm × 3 mm LFCSP specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM 50Ω 200Ω 800Ω 200Ω 2Ω VCC DATAP DATAN MSET GND BSET IBMON IBIAS IMODP IMODN ADN2525 VCC ALS GND VCC VCC 50Ω 50Ω 200Ω 800Ω IMOD 05077-001 Figure 1.

Rev. B | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

4/2017—Rev. A to Rev. B 8/2006—Rev. 0 to Rev. A 3/2005—Revision 0: Initial Version

Rev. B | Page 3 of 16 SPECIFICATIONS VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at 25°C, IMOD = 40 mA. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments BIAS CURRENT (IBIAS) Bias Current Range 10 100 mA Bias Current while ALS Asserted 100 µA ALS = high Compliance Voltage1 0.6 VCC – 1.2 V IBIAS = 100 mA 0.6 VCC – 0.8 V IBIAS = 10 mA MODULATION CURRENT (IMODP , IMODN) Modulation Current Range 10 80 mA diff RLOAD = 5 Ω to 50 Ω differential Modulation Current While ALS Asserted 0.5 mA diff ALS = high Rise Time (20% to 80%)2, 3 24 32.5 ps Fall Time (20% to 80%)2, 3 24 32.5 ps Random Jitter2, 3 0.4 0.9 ps rms Deterministic Jitter3, 4 7.2 12 ps p-p Includes pulse-width distortion Pulse-Width Distortion2, 3 2 5 ps PWD = ABS(THIGH − TLOW)/2 Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential −14 dB f < 5 GHz, Z0 = 50 Ω differential Compliance Voltage1 VCC − 1.1 VCC + 1.1 V DATA INPUTS (DATAP , DATAN) Input Data Rate 10.7 Gbps NRZ Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential Input Termination Resistance 85 100 115 Ω Differential BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain 75 100 120 mA/V BSET Input Resistance 800 1000 1200 Ω MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain 70 88 110 mA/V See Figure 29 MSET Input Resistance 800 1000 1200 Ω BIAS MONITOR (IBMON) IBMON to IBIAS Ratio 10 µA/mA Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ −4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ −2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ −2 +2 % 70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ AUTOMATIC LASER SHUTDOWN (ALS) VIH 2.4 V VIL 0.8 V IIL −20 +20 µA IIH 0 200 µA ALS Assert Time 2 µs Rising edge of ALS to fall of IBIAS and IMOD below 10% of nominal; see Figure 2 ALS Negate Time 10 µs Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal; see Figure 2 POWER SUPPLY VCC 3.07 3.3 3.53 V ICC5 39 45 mA VBSET = VMSET = 0 V ISUPPLY6 157 176 mA VBSET = VMSET = 0 V; ISUPPLY = ICC + IMODP + IMODN See notes on next page.

Rev. B | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Min Max Unit Supply Voltage, VCC to GND −0.3 +4.2 V IMODP , IMODN to GND VCC − 1 .5 4.75 V DATAP, DATAN to GND VCC − 1.8 VCC − 0.4 V All Other Pins −0.3 VCC + 0.3 V Junction Temperature 150 °C Storage Temperature Range −65 +150 °C Soldering Temperature (Less than 10 sec) 300 °C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

Figure 4. Pin Configuration Note that the exposed pad on the bottom of the package must be connected to the VCC or GND plane. Table 4. Pin Function Description

1 MSET Input Modulation Current Control Input

2 NC N/A No Connect—Leave Floating

3 ALS Input Automatic Laser Shutdown

4 GND Power Negative Power Supply

5 VCC Power Positive Power Supply

6 IMODN Output Modulation Current Negative Output

7 IMODP Output Modulation Current Positive Output

8 VCC Power Positive Power Supply

9 GND Power Negative Power Supply

10 IBIAS Output Bias Current Output

11 IBMON Output Bias Current Monitoring Output

12 BSET Input Bias Current Control Input

13 VCC Power Positive Power Supply

14 DATAP Input Data Signal Positive Input

15 DATAN Input Data Signal Negative Input

16 VCC Power Positive Power Supply

Rev. B | Page 14 of 16 DESIGN EXAMPLE This design example covers:

• Headroom calculations for IBIAS, IMODP , and IMODN pins.
• Calculation of the typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents. This design example assumes that the resistance of the TOSA is 25 Ω, the forward voltage of the laser at low current is VF = 1 V, IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V . Headroom Calculations To ensure proper device operation, the voltages on the IBIAS, IMODP , and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 33, the voltage at the IBIAS pin can be written as VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. VLB is the dc voltage drop across L1, L2, L3, and L4. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V , as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 25 Ω transmission lines is negligible and that VLA = 0 V, VF = 1 V, and IBIAS = 40 mA, VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by V COMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS (A) For this example: VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD × 25 Ω. For proper operation of the ADN2525, the voltage at each modulation output pin should be within the normal operation region shown in Figure 30. Assuming VLB = 0 V and IMOD = 60 mA, the minimum voltage at the modulation output pins is equal to VCC − (IMOD × 25)/2 = VCC − 0.75 VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement The maximum voltage at the modulation output pins is equal to VCC + (IMOD × 25)/2 = VCC + 0.75 VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions. BSET and MSET Pin Voltage Calculation To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2525 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and the typical IBIAS/V BSET ratio of 100 mA/V , the BSET voltage is given by V 4 . 0100 mA/V 100 (mA) = == IBIASVBSET The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table The voltage required at the MSET pin to produce the desired modulation current can be calculated using K IMODVMSET = where K is the MSET voltage to IMOD ratio. The value of K depends on the actual resistance of the TOSA. It can be read using the plot shown in Figure 29. For a TOSA resistance of 25 Ω, the typical value of K = 120 mA/V . Assuming that IMOD = 60 mA and using the preceding equation, the MSET voltage is given by V 5 . 0120 mA/V 120 (mA) = == IMODVMSET The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 29.

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. B | Page 16 of 16 NOTES ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05077-0-4/17(B)