ADM485_V01 AD | Alldatasheet

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5 V Low Power

Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.

FEATURES

5 Mbps data rate

–7 V to +12 V bus common-mode range High speed, low power BiCMOS Thermal shutdown protection Short-circuit protection Driver propagation delay: 10 ns typical Receiver propagation delay: 15 ns typical High-Z outputs with power off Superior upgrade for L TC485

APPLICATIONS

Local area networks (LNAs) Data concentration Data multiplexers Integrated services digital network (ISDN) FUNCTIONAL BLOCK DIAGRAM A GND B VCCR D RO RE DE DI ADM485 00078-001 Figure 1. GENERAL DESCRIPTION The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with EIA standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver can be enabled independently. When disabled, the outputs are three-stated. The ADM485 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. If during fault conditions, a significant temperature increase is detected in the internal driver circuitry, this feature forces the driver output into a high impedance state. Up to 32 transceivers can be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and when powered down, which minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the common-mode voltage range of −7 V to +12 V . The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up. The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbps while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in 8-lead PDIP , 8-lead SOIC, and small footprint, 8-lead MSOP packages.

Rev. F | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

04/08—Rev. E to Rev. F 10/03—Rev. D to Rev. E 7/03—Rev. C to Rev. D 1/03—Rev. B to Rev. C. 12/02—Rev. A to Rev. B.

Rev. F | Page 3 of 16 SPECIFICATIONS VCC = 5 V ± 5%, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, VOD 5.0 V R = ∞, see Figure 20 2.0 5.0 V VCC = 5 V, R = 50 Ω (RS-422), see Figure 20 1.5 5.0 V R = 27 Ω (RS-485), see Figure 20 VOD3 1.5 5.0 V VTST = −7 V to +12 V, see Figure 21 Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 20 Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 20 Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω Output Short-Circuit Current, VOUT = High 35 250 mA −7 V ≤ VO ≤ +12 V Output Short-Circuit Current, VOUT = Low 35 250 mA −7 V ≤ VO ≤ +12 V CMOS Input Logic Threshold Low, VINL 0.8 V CMOS Input Logic Threshold High, VINH 2.0 V Logic Input Current (DE, DI) ±1.0 μA RECEIVER Differential Input Threshold Voltage, VTH −0.2 +0.2 V −7 V ≤ VCM ≤ +12 V Input Voltage Hysteresis, ΔVTH 70 mV VCM = 0 V Input Resistance 12 kΩ −7 V ≤ VCM ≤ +12 V Input Current (A, B) 1 mA VIN = 12 V –0.8 mA VIN = −7 V CMOS Input Logic Threshold Low, VINL 0.8 V CMOS Input Logic Threshold High, VINH 2.0 V Logic Enable Input Current (RE) ±1 μA CMOS Output Voltage Low, VOL 0.4 V IOUT = 4.0 mA CMOS Output Voltage High, VOH 4.0 V IOUT = −4.0 mA Short-Circuit Output Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±1.0 μA 0.4 V ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT ICC, Outputs Enabled 1.0 2.2 mA Digital inputs = GND or VCC ICC, Outputs Disabled 0.6 1 mA Digital inputs = GND or VCC

Rev. F | Page 4 of 16 TIMING SPECIFICATIONS VCC = 5 V ± 5%, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Propagation Delay Input to Output, tPLH, tPHL 2 10 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22 Driver Output to OUTPUT, tSKEW 1 5 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22 Driver Rise/Fall Time, tR, tF 8 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 22 Driver Enable to Output Valid 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23 Driver Disable Timing 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23 Matched Enable Switching |tZH − tZL| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 231 Matched Disable Switching |tHZ − tLZ| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 231 RECEIVER Propagation Delay Input to Output, tPLH, tPHL 8 15 30 ns CL = 15 pF, see Figure 24 Skew |tPLH − tPHL| 5 ns CL = 15 pF, see Figure 24 Receiver Enable, tZH, tZL 5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25 Receiver Disable, tHZ, tLZ 5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25 Tx Pulse Width Distortion 1 ns Rx Pulse Width Distortion 1 ns 1 Guaranteed by characterization.

TA = 25°C, unless otherwise noted. Table 4. Transmitting

0 X1 Z2 Z2

Table 5. Receiving

0 Inputs open 1

1 X1 Z2

Figure 2. Pin Configuration Table 6. Pin Function Descriptions 1 RO Receiver Output. When enabled, if A is greater than B by 200 mV, RO is high. If A is less than B by 200 mV, RO is low. 2 RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state. 5 GND Ground Connection, 0 V. 6 A Noninverting Receiver Input A/Driver Output A. 7 B Inverting Receiver Input B/Driver Output B. 8 VCC Power Supply, 5 V ± 5%.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]

0.65 BSC

1.10 MAX

Figure 32. 8-Lead Mini Small Outline Package [MSOP]

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP] 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

Rev. F | Page 15 of 16 NOTES

Rev. F | Page 16 of 16 NOTES ©1993–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00078-0-4/08(F)