ADM4853ARZ

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5 V, Slew-Rate Limited, Half-Duplex and

Full-Duplex RS-485/RS-422 Transceivers ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.

FEATURES

EIA RS-485-/RS-422-compliant Data rate options ADM4850/ADM4854: 115 kbps ADM4851/ADM4855: 500 kbps ADM4852/ADM4856: 2.5 Mbps ADM4853/ADM4857: 10 Mbps Half- and full-duplex options Reduced slew rates for low EMI True fail-safe receiver inputs 5 μA (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-Z when disabled or powered off −7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with the MAX308x Specified over the −40°C to +85°C temperature range Available in 8-lead SOIC, LFCSP , and MSOP packages Qualified for automotive applications

APPLICATIONS

Low power RS-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators FUNCTIONAL BLOCK DIAGRAMS 04931-001 RO RE R DE DI D A B GND VCC ADM4850/ADM4851/ ADM4852/ADM4853 Figure 1. 04931-028 RO R A B DI D Z Y GND VCC ADM4854/ADM4855/ ADM4856/ADM4857 Figure 2. GENERAL DESCRIPTION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are half- duplex transceivers that share differential lines and have separate enable inputs for the driver and receiver. The full-duplex ADM4854/ADM4855/ADM4856/ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Because only one driver should be enabled at any time, the output of a disabled or pow- ered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC, LFCSP (ADM4850/ADM4851/ADM4852/ADM4853), and MSOP (ADM4850 only) packages. Table 1. Selection Table

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

1/12—Rev. C to Rev. D 1/11—Rev. B to Rev. C 7/09—Rev. A to Rev. B 4/09—Rev. 0 to Rev. A 10/04—Revision 0: Initial Version

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 3 of 16 SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, VOD V CC V R = ∞, see Figure 181 2.0 5 V R = 50 Ω (RS-422), see Figure 18 1.5 5 V R = 27 Ω (RS-485), see Figure 18 |VOD3| 1.5 5 V VTST = −7 V to 12 V, see Figure 19 ∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18 Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 18 ∆|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18 Output Short-Circuit Current, VOUT = High −200 +200 mA −7 V < VOUT < +12 V Output Short-Circuit Current, VOUT = Low −200 +200 mA −7 V < VOUT < +12 V DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 0.8 V CMOS Input Logic Threshold High 2.0 V CMOS Logic Input Current (DI) ±1 μA DE Input Resistance to GND 220 kΩ RECEIVER Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V < VOC < +12 V Input Hysteresis 20 mV −7 V < VOC < +12 V Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V Input Current (A, B) 0.125 mA VIN = +12 V − 0.1 mA VIN = −7 V CMOS Logic Input Current (RE) ± 1 μA CMOS Output Voltage Low 0.4 V IOUT = +4 mA CMOS Output Voltage High 4.0 V IOUT = −4 mA Output Short-Circuit Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±2 μA 0.4 V ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT 115 kbps Options (ADM4850/ADM4854) 5 μA DE = 0 V, RE = VCC (shutdown) 36 60 μA DE = 0 V, RE = 0 V 100 160 μA DE = VCC 500 kbps Options (ADM4851/ADM4855) 5 μA DE = 0 V, RE = VCC (shutdown) 80 120 μA DE = 0 V, RE = 0 V 120 200 μA DE = VCC

2.5 Mbps Options (ADM4852/ADM4856) 5 μA DE = 0 V, RE = VCC (shutdown)

250 400 μA DE = 0 V, RE = 0 V 320 500 μA DE = VCC

10 Mbps Options (ADM4853/ADM4857) 5 μA DE = 0 V, RE = VCC (shutdown)

250 400 μA DE = 0 V, RE = 0 V 320 500 μA DE = VCC 1 Guaranteed by design.

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 4 of 16 ADM4850/ADM4854 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 115 kbps Propagation Delay, tPLH, tPHL 600 2500 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Skew, tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Rise/Fall Times, tR, tF 600 2400 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Enable Time, tZH 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850 Disable Time, tZL 2000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850 RECEIVER Propagation Delay, tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 22 Differential Skew, tSKEW 255 ns CL = 15 pF, see Figure 22 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850 Time to Shutdown 50 330 3000 ns ADM48501 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 500 kbps Propagation Delay, tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Skew, tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Rise/Fall Times, tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Enable Time, tZH 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851 Disable Time, tZL 1000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851 RECEIVER Propagation Delay, tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 22 Differential Skew, tSKEW 250 ns CL = 15 pF, see Figure 22 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851 Time to Shutdown 50 330 3000 ns ADM48511 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 5 of 16 ADM4852/ADM4856 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5. Parameter Min Typ Max Unit Test Conditions/Comments D R I V E R Maximum Data Rate 2.5 Mbps Propagation Delay, tPLH, tPHL 50 180 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Skew, tSKEW 50 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Rise/Fall Times, tR, tF 140 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Enable Time, tZH 180 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852 Disable Time, tZL 180 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852 R E C E I V E R Propagation Delay, tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 22 Differential Skew, tSKEW 50 ns CL = 15 pF, see Figure 22 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852 Time to Shutdown 50 330 3000 ns ADM48521 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6. Parameter Min Typ Max Unit Test Conditions/Comments D R I V E R Maximum Data Rate 10 Mbps Propagation Delay, tPLH, tPHL 0 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Skew, tSKEW 10 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Rise/Fall Times, tR, tF 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20 Enable Time, tZH 35 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853 Disable Time, tZL 35 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853 R E C E I V E R Propagation Delay, tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 22 Differential Skew, tSKEW 30 ns CL = 15 pF, see Figure 22 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853 Time to Shutdown 50 330 3000 ns ADM48531 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating VCC to GND 6 V Digital I/O Voltage (DE, RE, DI, RO) −0.3 V to VCC + 0.3 V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C θJA Thermal Impedance SOIC 110°C/W LFCSP 62°C/W MSOP 133.1°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 5. ADM4854/ADM4855/ADM4856/ADM4857 Pin Configuration, SOIC Table 9. ADM4854/ADM4855/ADM4856/ADM4857 Pin Descriptions 2 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low. on DI forces Y high and Z low. 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 B Inverting Receiver Input. 8 A Noninverting Receiver Input.

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 14 of 16 HIGH RECEIVER INPUT IMPEDANCE The input impedance of the ADM4850/ADM4851/ADM4852/ ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers is 96 kΩ, which is eight times higher than the standard RS-485 unit load of 12 kΩ. This 96 kΩ impedance enables a standard driver to drive 32 unit loads or to be connected to 256 ADM4850/ ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ ADM4856/ADM4857 receivers. An RS-485 bus, driven by a single standard driver, can be connected to a combination of ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 devices and standard unit load receivers, up to an equivalent of 32 standard unit loads. THREE-STATE BUS CONNECTION The half-duplex parts (ADM4850/ADM4851/ADM4852/ ADM4853) have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the half-duplex devices have an active low receiver enable (RE ) pin. Taking this pin low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an RS-485 bus. Note that only one driver should be enabled at a time, but that many receivers can be enabled. SHUTDOWN MODE The ADM4850/ADM4851/ADM4852/ADM4853 have a low power shutdown mode, which is enabled by taking RE high and DE low. If shutdown mode is not used, the fact that DE is active high and RE is active low offers a convenient way of switching the device between transmit and receive by tying DE and RE together. If DE is driven low and RE is driven high for less than 50 ns, the devices are guaranteed not to enter shutdown mode. If DE is driven low and RE is driven high for at least 3000 ns, the devices are guaranteed to enter shutdown mode. FAIL-SAFE OPERATION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mV EIA/TIA-485 standard. A logic high receiver output is generated when the receiver inputs are shorted together or open circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between −30 mV and −200 mV . If the differential receiver input voltage (A − B) is greater than or equal to −30 mV , RO is logic high. If (A − B) is less than or equal to −200 mV , RO is logic low. In the case of a terminated bus with all transmitters disabled, the differential input voltage of the receiver is pulled to 0 V by the internal circuitry of the ADM4850/ADM4851/ADM4852/ ADM4853/ADM4854/ADM4855/ADM4856/ADM4857, which results in a logic high with 30 mV minimum noise margin. CURRENT LIMIT AND THERMAL SHUTDOWN The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 incorporate two protection mechanisms to guard the drivers against short circuits, bus con- tention, or other fault conditions. The first is a current limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 mA. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150°C, and does not turn them back on until the temperature falls to 130°C.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]

0.65 BSC

1.10 MAX

Figure 31. 8-Lead Mini Small Outline Package [MSOP]

0.65 TYP

0.90 MAX

0.01 NOM

0.20 REF

0.60 MAX

Figure 32. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 Rev. D | Page 16 of 16 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding ADM4850ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M8Q ADM4850ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4850ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4850ARMZ −40°C to +85°C 8-Lead MSOP RM-8 M8Q ADM4850ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 M8Q ADM4851ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4851ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4852ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M9M ADM4852ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4852ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4853ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 F0B ADM4853ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4853ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4853WARZ-RL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4854ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4855AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4855ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4856ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4856ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM4857ARZ −40°C to +85°C 8-Lead SOIC_N R-8 ADM4857ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. 2 W = qualified for automotive products. AUTOMOTIVE PRODUCT The ADM4853W ARZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04931-0-1/12(D)