ADM4852ACP-REEL7

ADM4853 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

5 V Slew-Rate Limited Half- and Full-Duplex

RS-485/RS-422 Transceivers ADM4850–ADM4857 Rev. 0 Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

EIA RS-485-/RS-422-compliant Data rate options ADM4850/ADM4854—115 kbps ADM4851/ADM4855—500 kbps ADM4852/ADM4856—2.5 Mbps ADM4853/ADM4857—10 Mbps Half- and full-duplex options Reduced slew rates for low EMI True fail-safe receiver inputs 5 µA (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-z when disabled or powered off −7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MAX308x Specified over the −40°C to +85°C temperature range Available in 8-lead SOIC and LFCSP packages

APPLICATIONS

Low power RS-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators FUNCTIONAL BLOCK DIAGRAM 04931-001 RO R A B DI D Z Y GND VCC ADM4854/ADM4855/ ADM4856/ADM4857 RO RE R DE DI D A B GND VCC ADM4850/ADM4851/ ADM4852/ADM4853 Figure 1. GENERAL DESCRIPTION The ADM4850−ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850−ADM4853 are half-duplex transceivers, which share differential lines and have separate enable inputs for the driver and receiver. The full-duplex ADM4854−ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or pow- ered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends. The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges, and are available in 8-lead SOIC and LFCSP packages. Table 1. Selection Table

ADM4850–ADM4857 Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

10/04—Revision 0: Initial Version

ADM4850–ADM4857 Rev. 0 | Page 3 of 16 SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments D R I V E R Differential Output Voltage, VOD VCC V R = ∞, Figure 41 2.0 5 V R = 50 Ω (RS-422), Figure 4 1.5 5 V R = 27 Ω (RS-485), Figure 4 1.5 5 V VTST = −7 V to 12 V, Figure 5 ∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 4 Common-Mode Output Voltage, VO 3 V R = 27 Ω or 50 Ω, Figure 4 ∆|VO | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 4 Output Short-Circuit Current, VOUT = High −200 +200 mA −7 V < VOUT < +12 V Output Short-Circuit Current, VOUT = Low −200 +200 mA −7 V < VOUT < +12 V DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 1.4 0.8 V CMOS Input Logic Threshold High 2.0 1.4 V CMOS Logic Input Current (DI) ±1 µA DE Input Resistance to GND 220 kΩ R E C E I V E R Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V < VM < +12 V Input Hysteresis 20 mV −7 V < VM < +12 V Input Resistance (A, B) 96 150 kΩ −7 V < VM < +12 V Input Current (A, B) 0.125 mA VIN = +12 V − 0 . 1 m A VIN = −7 V CMOS Logic Input Current (RE) ± 1 µ A CMOS Output Voltage Low 0.4 V IOUT = +4 mA CMOS Output Voltage High 4.0 V IOUT = −4 mA Output Short Circuit Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±2 µA 0.4 V ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT I (115 kbps Options) 5 µA DE = 0 V, RE = VCC (shutdown) 36 60 µA DE = 0 V, RE = 0 V 100 160 µA DE = VCC I (500 kbps Options) 5 µA DE = 0 V, RE = VCC (shutdown) 80 120 µA DE = 0 V, RE = 0 V 120 200 µA DE = VCC I (2.5 Mbps Options) 5 µA DE = 0 V, RE = VCC (shutdown) 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC I (10 Mbps Options) 5 µA DE = 0 V, RE = VCC (shutdown) 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC 1 Guaranteed by design.

ADM4850–ADM4857 Rev. 0 | Page 4 of 16 ADM4850/ADM4854 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments D R I V E R Maximum Data Rate 115 kbps Propagation Delay tPLH, tPHL 600 2500 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Skew tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Rise/Fall Time tR, tF 600 2400 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Enable Time 2000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850 Disable Time 2000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4850 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850 R E C E I V E R Propagation Delay tPLH, tPH 400 1000 ns CL = 15 pF, Figure 8 Differential Skew tSKEW 255 ns CL = 15 pF, Figure 8 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850 Time to Shut Down 50 330 3000 ns ADM48501 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 500 kbps Propagation Delay tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Skew tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Rise/Fall Time tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Enable Time 1000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851 Disable Time 1000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4851 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851 RECEIVER Propagation Delay tPLH, tPHL 400 1000 ns CL = 15 pF, Figure 8 Differential Skew tSKEW 250 ns CL = 15 pF, Figure 8 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4851 Disable Time 20 50 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851 Enable Time from Shutdown 4000 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851 Time to Shut Down 50 330 3000 ns ADM48511 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

ADM4850–ADM4857 Rev. 0 | Page 5 of 16 ADM4852/ADM4856 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 2.5 Mbps Propagation Delay tPLH, tPHL 50 180 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Skew tSKEW 50 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Rise/Fall Time tR, tF 140 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Enable Time 180 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4852 Disable Time 180 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4852 Enable Time from Shutdown 4000 ns RL =500 Ω, CL = 100 pF, Figure 7, ADM4852 RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, Figure 8 Differential Skew tSKEW 50 ns CL = 15 pF, Figure 8 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852 Time to Shut Down 50 330 3000 ns ADM48521 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS V = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 10 Mbps Propagation Delay tPLH, tPHL 0 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Skew tSKEW 10 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Rise/Fall Time tR, tF 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 6 Enable Time 35 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853 Disable Time 35 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4853 Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853 RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, Figure 8 Differential Skew tSKEW 30 ns CL = 15 pF, Figure 8 Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853 Time to Shut Down 50 330 3000 ns ADM48531 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.

ADM4850–ADM4857 Rev. 0 | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating VCC to GND 6 V Digital I/O Voltage (DE, RE, DI, ROUT) −0.3 V to VCC + 0.3 V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C θJA Thermal Impedance SOIC 110°C/W LFCSP 62°C/W Lead Temperature Soldering (10 s) 300°C Vapour Phase (60 s) 215°C Infrared (15 s) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ADM4850–ADM4857 Rev. 0 | Page 13 of 16 HIGH RECEIVER INPUT IMPEDANCE The input impedance of the ADM485x receivers is 96 kΩ, which is 8 times higher than the standard RS-485 unit load of 12 kΩ. This 96 kΩ impedance, enables a standard driver to drive 32 unit loads or be connected to 256 ADM485x receivers. An RS-485 bus, driven by a single standard driver, can be connected to a combination of ADM485x and standard unit load receivers, up to an equivalent of 32 standard unit loads. THREE-STATE BUS CONNECTION The half-duplex parts have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the half- duplex devices have an active-low receiver enable (RE) pin. Taking this pin low enables the receiver, while taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an RS-485 bus. Note that only one driver should be enabled at a time, while many receivers can be enabled. SHUTDOWN MODE The ADM4850–ADM4853 have a low power shutdown mode, which is enabled by taking RE high and DE low. If shutdown mode is not used, the fact that DE is active high and RE is active low offers a convenient way of switching the device between transmit and receive by tying DE and RE together. The devices are guaranteed not to enter shutdown mode if DE and RE are driven in this way. If DE is low and RE is high for less than 50 ns, the device does not enter shutdown mode. If DE is low and RE is high for less than 3000 ns, the device is guaranteed to enter shutdown mode. FAIL-SAFE OPERATION The ADM4850–ADM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mV EIA/TIA-485 standard. A logic-high receiver output is generated when the receiver inputs are shorted together or open-circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between −30 mV and −200 mV . If the differential receiver input voltage (A-B) is greater than or equal to −30 mV , RO is logic high. If A-B is less than or equal to −200 mV , RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver’s differential input voltage is pulled to 0 V by the ADM485x’s internal circuitry, which results in a logic high with 30 mV minimum noise margin. CURRENT LIMIT AND THERMAL SHUTDOWN The ADM485x incorporates two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current-limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 mA. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150°C, and does not turn them back on until the temperature falls to 130°C.

Figure 28. 8-Lead Standard Small Outline Package [SOIC]

0.60 MAX PIN 1

0.05 MAX

0.02 NOM

0.20 REF

Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP]

ADM4850–ADM4857 Rev. 0 | Page 15 of 16 ORDERING GUIDE Model Temperature Range Package Description Package Type Branding ADM4850ACP-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0R ADM4850ACP-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0R ADM4850AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4850AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4850AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4851ACP-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0S ADM4851ACP-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0S ADM4851AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4851AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4851AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4852ACP-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0T ADM4852ACP-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0T ADM4852AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4852AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4852AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4853ACP-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0U ADM4853ACP-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package CP-8-2 M0U ADM4853AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4853AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4853AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4854AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4855AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4855AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4855AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4856AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4856AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4856AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4857AR −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4857AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package R-8 ADM4857AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package R-8

ADM4850–ADM4857 Rev. 0 | Page 16 of 16 NOTES © 2004 Analog Devices, Inc . A ll rig hts r eserved. Trademarks an d registered tr ademarks ar e t he proper ty of t heir respec tive o wners. D04931–0–10/04(0)