ADM4850 AD | Alldatasheet
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Technical content
5 V, Slew Rate Limited, Half-Duplex and
Full Duplex RS-485/RS-422 Transceivers Data Sheet ADM4850 to ADM4857 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Electronics industries alliance (EIA) RS-485/RS-422 compliant Data rate options ADM4850/ADM4854: 115 kbps ADM4851/ADM4855: 500 kbps ADM4852/ADM4856: 2.5 Mbps ADM4853/ADM4857: 10 Mbps Half-duplex and full duplex options Reduced slew rates for low electromagnetic interference (EMI) True fail-safe receiver inputs 5 µA (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-Z when disabled or powered off −7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with the MAX308x Specified over the −40°C to +85°C temperature range Available in 8-lead SOIC, 8-lead LFCSP , and 8-lead MSOP Qualified for automotive applications
APPLICATIONS
Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators GENERAL DESCRIPTION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 are differential line transceivers suitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/ ADM4852/ADM4853 are half-duplex transceivers that share differential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854/ADM4855/ADM4856/ ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only one driver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. FUNCTIONAL BLOCK DIAGRAMS Figure 1. ADM4850/ADM4851/ADM4852/ADM4853 Functional Block Diagram Figure 2. ADM4854/ADM4855/ADM4856/ADM4857 Functional Block Diagram before communication begins and when communication ends. errors caused by reflections from improperly terminated buses. output shorting is prevented with a thermal shutdown circuit. ADM4853), and 8-lead MSOP (ADM4850 only) packages. Table 1. Selection Table
ADM4850 to ADM4857 Data Sheet Rev. F | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
5/16—Rev. E to Rev. F C Reformatted and Changes to Pin Configuration and Function 6—Rev. D to Rev. E Changed Circuit Description Section to Theory of Operation Changes to the Three-State Bus Connection Section and the 2—Rev. C to Rev. D 1/11—Rev. B to Rev. C 9—Rev. A to Rev. B 9—Rev. 0 to Rev. A 10/04—R evision 0: Initial Version
Data Sheet ADM4850 to ADM4857 Rev. F | Page 3 of 16 SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Mi n Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage VOD VCC V R = ∞, see Figure 191 2. 0 5 V R = 50 Ω (RS-422), see Figure 19 1. 5 5 V R = 27 Ω (RS-485), see Figure 19 Differential Output Voltage over Common- Mode Range |VOD3| 1.5 5 V VTST = −7 V to +12 V, see Figure 20 Δ|VOD| for Complementary Output States 0. 2 V R = 27 Ω or 50 Ω, see Figure 19 Common-Mode Output Voltage VOC 3 V R = 27 Ω or 50 Ω, see Figure 19 Δ|VOC| for Complementary Output States 0. 2 V R = 27 Ω or 50 Ω, see Figure 19 Output Short-Circuit Current −7 V < VOUT < +12 V VOUT = High −200 +200 mA VOUT = Low −200 +200 mA DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 0. 8 V High 2. 0 V CMOS Logic Input Current (DI) ±1 µA DE Input Resistance to GND 220 kΩ RECEIVER Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VOC < +12 V Input Hysteresis 20 mV −7 V < VOC < +12 V Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V Input Current (A, B) 0. 125 mA VIN = 12 V −0. 1 mA VIN = −7 V CMOS Logic Input Current (RE) ±1 µA CMOS Output Voltage Low 0. 4 V IOUT = 4 mA High 4. 0 V IOUT = −4 mA Output Short-Circuit Current 7 85 mA VOUT = GND or VCC Three-State Output Leakage Current ±2 µA 0.4 V ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT 115 kbps Options (ADM4850/ADM4854) 5 µA DE = 0 V, RE = VCC (shutdown) 36 60 µA DE = 0 V, RE = 0 V 100 160 µA DE = VCC 500 kbps Options (ADM4855) 5 µA DE = 0 V, RE = VCC (shutdown) 80 120 µA DE = 0 V, RE = 0 V 120 200 µA DE = VCC
2.5 Mbps Options (ADM4852/ADM4856) 5 µA DE = 0 V, RE = VCC (shutdown)
250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC
10 Mbps Options (ADM4853/ADM4857) 5 µA DE = 0 V, RE = VCC (shutdown)
250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = VCC 1 Guaranteed by design.
ADM4850 to ADM4857 Data Sheet Rev. F | Page 4 of 16 ADM4850/ADM4854 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 115 k bps Propagation Delay tPLH, tPHL 600 250 0 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 600 240 0 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 200 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4850 only) Disable Time tLZ, tHZ 200 0 ns RL = 500 Ω, CL = 15 pF, see Figure 22 and Figure 27 (ADM4850 only) Enable Time from Shutdown 400 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4850 only) RECEIVER Propagation Delay tPLH, tPHL 400 100 0 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 255 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 and Figure 28 (ADM4850 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 and Figure 28 (ADM4850 only) Enable Time from Shutdown 400 0 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 (ADM4850 only) Time to Shutdown 50 330 300 0 ns ADM4850 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 500 k bps Propagation Delay tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 100 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) Disable Time tLZ, tHZ 100 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) Enable Time from Shutdown 400 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4851 only) RECEIVER Propagation Delay tPLH, tPHL 400 100 0 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 250 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) Enable Time from Shutdown 400 0 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 (ADM4851 only) Time to Shutdown 50 330 300 0 ns ADM4851 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Data Sheet ADM4850 to ADM4857 Rev. F | Page 5 of 16 ADM4852/ADM4856 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 2. 5 M bps Propagation Delay tPLH, tPHL 50 180 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 50 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 140 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 180 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4852 only) Disable Time tLZ, tHZ 180 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4852 only) Enable Time from Shutdown 400 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4852 only) RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 50 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) Enable Time from Shutdown 400 0 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 (ADM4852 only) Time to Shutdown 50 330 300 0 ns ADM4852 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 10 M bps Propagation Delay tPLH, tPHL 0 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Skew tSKEW 10 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Rise/Fall Times tR, tF 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 21 and Figure 25 Enable Time tZH, tZL 35 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) Disable Time tLZ, tHZ 35 ns RL = 500 Ω, CL = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) Enable Time from Shutdown 400 0 ns RL = 500 Ω, CL = 100 pF, see Figure 22 (ADM4853 only) RECEIVER Propagation Delay tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 23 and Figure 26 Differential Skew tSKEW 30 ns CL = 15 pF, see Figure 23 and Figure 26 Enable Time tZH, tZL 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) Disable Time tLZ, tHZ 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) Enable Time from Shutdown 400 0 ns RL = 1 kΩ, CL = 15 pF , see Figure 24 (ADM4853 only) Time to Shutdown 50 330 300 0 ns ADM4853 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4850 to ADM4857 Data Sheet Rev. F | Page 6 of 16 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating VCC to GND 6 V Digital Input/Output Voltage (DE, RE, DI, RO) −0.3 V to VCC + 0.3 V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C θJA Thermal Impedance 8-Lead SOIC 110°C/W 8-Lead LFCSP 62°C/W 8-Lead MSOP 133.1°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C S tresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Table 8. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead MSOP and 8-Lead SOIC, Pin Function Descriptions the driver differential outputs into a high impedance state. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B.
Table 9. ADM4850/ADM4852/ADM4853, 8-Lead LFCSP, Pin Function Descriptions driver differential outputs into a high impedance state. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B. increase the reliability of the solder joints and to maximize the thermal capability of the package. Table 10. ADM4854/ADM4855/ADM4856/ADM4857, 8-Lead SOIC, Pin Function Descriptions 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 B Inverting Receiver Input. 8 A Noninverting Receiver Input.
- THE EXPOSED PADDLE ON THE UNDERSIDE
Data Sheet ADM4850 to ADM4857 Rev. F | Page 13 of 16 THEORY OF OPERATION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 are high speed RS-485/RS-422 transceivers offering enhanced performance over industry- standard devices. All devices in the family contain one driver and one receiver but offer a choice of performance options. The devices feature true fail-safe operation, which guarantees a logic high receiver output when the receiver inputs are open circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe Operation section). SLEW RATE CONTROL The ADM4850 and ADM4854 feature a controlled slew rate driver that minimizes EMI and reduces reflections caused by incorrectly terminated cables, allowing error free data transmission rates up to 115 kbps. The ADM4851 and ADM4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. The driver slew rates of the ADM4852/ ADM4856 and the ADM4853/ADM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 10 Mbps, respectively. RECEIVER INPUT FILTERING The receivers of all the devices incorporate input hysteresis. In addition, the receivers of the 115 kbps ADM4850 and ADM4854 and the 500 kbps ADM4851 and ADM4855 incorporate input filtering, which enhances noise immunity with differential signals that have very slow rise and fall times. However, it causes the propagation delay to increase by 20%. HALF-DUPLEX/FULL DUPLEX OPERATION Half-duplex operation implies that the transceiver can transmit and receive, but it can do only one of these at any given time. However, with full duplex operation, the transceiver can transmit and receive simultaneously. The ADM4850/ADM4851/ADM4852/ ADM4853 are half-duplex devices in which the driver and the receiver share differential bus terminals. The ADM4854/ ADM4855/ADM4856/ADM4857 are full duplex devices that have dedicated driver output and receiver input pins. Figure 29 and Figure 30 show typical half-duplex and full duplex topologies. F igure 29. Typical Half-Duplex RS-485 Network Topology F igure 30. Typical Full Duplex Point-to-Point RS-485 Network Topology 04931-026 RO RE DE DID RA B MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256 RO RE DE DI D R A B R D RO RE DE DI A B R D RO RE DE DI A B ADM4850/ ADM4852/ADM4853 ADM4850/ ADM4852/ADM4853 ADM4850 ADM4852/ADM4853 ADM4850/ ADM4852/ADM4853 NOTES 1. THE ADM4851 IS A HALF-DUPLEX RS-485 TRANSCEIVER, BUT IT DOES NOT HAVE THE DRIVER ENABLE (DE) AND THE RECEIVER ENABLE (RE) PINS. 04931-027GND RO DI D R A B RO DID A B Z Y R GND VCC VCC Z Y ADM4854/ADM4855/ ADM4856/ADM4857 ADM4854/ADM4855/ ADM4856/ADM4857
ADM4850 to ADM4857 Data Sheet Rev. F | Page 14 of 16 HIGH RECEIVER INPUT IMPEDANCE The input impedance of the ADM4850/ADM4851/ADM4852/ ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers is 96 kΩ, which is eight times higher than the standard RS-485 unit load of 12 kΩ. This 96 kΩ impedance enables a standard driver to drive 32 unit loads or to be connected to 256 ADM4850/ ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ ADM4856/ADM4857 receivers. An RS-485 bus, driven by a single standard driver, can be connected to a combination of ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 devices and standard unit load receivers, up to an equivalent of 32 standard unit loads. THREE-STATE BUS CONNECTION The half-duplex devices (ADM4850/ADM4852/ADM4853) have a driver enable pin (DE) that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the half-duplex devices have an active low receiver enable pin (RE). Taking this pin low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state, which allows several driver outputs to be connected to an RS-485 bus. Note that only one driver must be enabled at a time, but that many receivers can be enabled. SHUTDOWN MODE The ADM4850/ADM4852/ADM4853 have a low power shutdown mode, which is enabled by taking RE high and DE low. If shutdown mode is not used, the fact that DE is active high and RE is active low offers a convenient way of switching the device between transmit and receive by tying DE and RE together. If DE is driven low and RE is driven high for less than 50 ns, the devices are guaranteed not to enter shutdown mode. If DE is driven low and RE is driven high for at least 3000 ns, the devices are guaranteed to enter shutdown mode. FAIL-SAFE OPERATION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 offer true fail-safe operation while remaining fully compliant with the ±200 mV EIA/TIA-485 standard. A logic high receiver output generates when the receiver inputs are shorted together or open circuit, or when they are connected to a terminated transmission line with all drivers disabled. This logic high is done by setting the receiver threshold between −30 mV and −200 mV . If the differential receiver input voltage (A − B) is greater than or equal to −30 mV , RO is logic high. If (A − B) is less than or equal to −200 mV , RO is logic low. In the case of a terminated bus with all transmitters disabled, the differential input voltage of the receiver is pulled to 0 V by the internal circuitry of the ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857, which results in a logic high with 30 mV minimum noise margin. CURRENT LIMIT AND THERMAL SHUTDOWN The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4855/ADM4856/ADM4857 incorporate two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 mA. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150°C, and does not turn them back on until the temperature falls to 130°C.
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N] Figure 32. 8-Lead Mini Small Outline Package [MSOP] REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.65 BSC
1.10 MAX
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
ADM4850 to ADM4857 Data Sheet Rev. F | Page 16 of 16 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding ADM4850ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 M8Q ADM4850ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4850ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4850ARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8Q ADM4850ARMZ-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8Q ADM4851ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4851ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4852ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 M9M ADM4852ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4852ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4853ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 F0B ADM4853ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4853ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4853WARZ-RL7 −40°C to +85°C 8-Lead Stan dard Small Outline Package [SOIC_N] R-8 ADM4854ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4855ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4856ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4856ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4857ARZ −40°C to +85°C 8-Lead Standa rd Small Outline Package [SOIC_N] R-8 ADM4857ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCT The ADM4853W ARZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04931-0-5/16(F)