ADM483JR-REEL7

ADM483 AD | Alldatasheet

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Technical content

5 V Low Power, Slew-Rate Limited

Rev. 0 Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

EIA RS-485/RS-422-compliant Data rates up to 250 kbps Slew-rate limited for low EMI 100 nA supply current in shutdown mode Low power consumption (120 µA) Up to 32 transceivers on one bus Outputs high-z when disabled or powered off –7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MAX483 Specified over –40°C to +85°C temperature range Available in 8-lead SOIC package

APPLICATIONS

Low power RS-485 applications EMI sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators FUNCTIONAL BLOCK DIAGRAM 05079-001 RO RE R DE DI D A B GND VCC ADM483 Figure 1. GENERAL DESCRIPTION The ADM483 is a low power differential line transceiver suitable for half-duplex data communication on multipoint bus trans- mission lines. It is designed for balanced data transmission, and complies with EIA Standards RS-485 and RS-422.The part contains a differential line driver and a differential line receiver. Both share the same differential pins, with either the driver or the receiver being enabled at any given time. The device has an input impedance of 12 kΩ, allowing up to 32 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. This high impedance driver output is maintained over the entire common-mode voltage range from –7 V to +12 V. The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. The part is fully specified over the industrial temperature range, and is available in an 8-lead SOIC package.

Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, VOD 5 V R = ∞, Figure 3

2.0 V R = 50 Ω (RS-422), Figure 3

1.5 5 V R = 27 Ω (RS-485), Figure 3 1.5 5 V VTST = –7 V to 12 V, Figure 4 ∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3 Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, Figure 3 ∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3 Output Short-Circuit Current, VOUT = High 35 250 mA –7 V < VOUT < +12 V Output Short-Circuit Current, VOUT = Low 35 250 mA –7 V < VOUT < +12 V DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 0.8 V CMOS Input Logic Threshold High 2.0 V CMOS Logic Input Current (DI) ±2 µA DE Input Resistance to GND 220 kΩ RECEIVER Differential Input Threshold Voltage, VTH –200 +200 mV –7 V < VCM < +12 V Input Hysteresis 70 mV VCM = 0V Input Resistance (A, B) 12 kΩ –7 V < VCM < +12 V Input Current (A, B) 1 mA VIN = +12 V –0.8 mA VIN = –7 V CMOS Logic Input Current (RE) ±2 µA CMOS Output Voltage Low 0.4 V IOUT = 4 mA CMOS Output Voltage High 3.5 V IOUT = –4 mA Output Short-Circuit Current 7 95 mA 0 V < VOUT < VCC Three-State Output Leakage Current ±2 µA 0.4 ≤ VOUT ≤ 2.4 V POWER SUPPLY CURRENT 0.1 10 µA DE = 0 V, RE = VCC (shutdown) 120 250 µA DE = 0 V, RE = 0 V 350 650 µA DE = VCC

Rev. 0 | Page 4 of 16 TIMING SPECIFICATIONS VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 250 kbps Propagation Delay tPLH, tPHL 250 800 2000 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Skew tSKEW 100 800 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Rise/Fall Time tR, tF 200 2000 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Figure 5 Enable Time 125 2000 ns RL = 500 Ω, CL = 100 pF, Figure 6 Disable Time 125 3000 ns RL = 500 Ω, CL = 15 pF, Figure 6 Enable Time from Shutdown 5000 ns RL = 500 Ω, CL = 100 pF, Figure 6 RECEIVER Propagation Delay tPLH, tPHL 250 2000 ns CL = 15 pF, Figure 7 Differential Skew tSKEW 100 ns CL = 15 pF, Figure 7 Enable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 8 Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 8 Enable Time from Shutdown 5000 ns RL = 1 kΩ, CL = 15 pF, Figure 8 Time to Shutdown1 50 330 3000 ns 1 The device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to have entered shutdown mode.

Rev. 0 | Page 5 of 16 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VCC to GND 6 V Digital I/O Voltage (DE, RE, DI, ROUT) –0.3 V to VCC + 0.3 V Driver Output/Receiver Input Voltage –9 V to +14 V Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +125°C θJA Thermal Impedance (SOIC) 110°C/W Lead Temperature Soldering (10 s) 300°C Vapor Phase (60 s) 215°C Infrared (15 s) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 4. Pin Function Descriptions 1 RO Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low. 2 RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state. 3 DE Driver Output Enable. A high level enables the driver differential inputs A and B. A low level places it in a high impedance state. while a logic high on DI forces A high and B low. 6 A Noninverting Receiver Input A/Driver Output A. 7 B Inverting Receiver Input B/Driver Output B.

Rev. 0 | Page 12 of 16 THERMAL SHUTDOWN The ADM483 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temp- erature and disables the driver outputs. The thermal sensing circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at 140°C. RECEIVER OPEN-CIRCUIT FAIL-SAFE The receiver input includes a fail-safe feature that guarantees a logic high on the receiver when the inputs are open circuit or floating.

Figure 25. 8-Lead Standard Small Outline Package [SOIC]

Rev. 0 | Page 14 of 16 NOTES

Rev. 0 | Page 15 of 16 NOTES

Rev. 0 | Page 16 of 16 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . D05079-0-10/04(0)