ADM483E AD | Alldatasheet
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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM483E Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 615 kV ESD Protected, EMC Compliant Slew Rate Limited, EIA RS-485 Transceiver FUNCTIONAL BLOCK DIAGRAMFEATURES Robust RS-485 Transceiver 15 kV ESD Protection Using HBM 2 kV EFT Protection Meets IEC1000-4-4 High EM Immunity Meets IEC1000-4-3 Reduced Slew Rate for Low EM Interference 250 kbps Data Rate Single +5 V 6 10% Supply –7 V to +12 V Bus Common-Mode Range 12 kV Input Impedance Short Circuit Protection Excellent Noise Immunity 36 mA Supply Current 0.1 mA Shutdown Current
APPLICATIONS
Electrically Harsh Environments EMI Sensitive Applications DTE-DCE Interface Packet Switching Local Area Networks D R A B DI DE RE RO ADM483E GENERAL DESCRIPTION The ADM483E is a robust, low power differential line trans- ceiver suitable for communication on multipoint bus transmis- sion lines. Internal protection against electrostatic discharge (ESD), electrical fast transient (EFT) and electromagnetic immunity (EMI) allows operation in electrically harsh environ- ments. ESD protection on the I-O lines meets ± 15 kV when tested using the Human Body Model. EFT protection meets ± 2 kV in accordance with IEC1000-4-4, while EMI immunity is in excess of 10 V/m meeting IEC1000-4-3. The level of unwanted emissions is also carefully controlled using slew limiting on the driver outputs. This reduces reflec- tions with improperly terminated cables and also minimizes electromagnetic interference. The controlled slew rate limits the data rate to 250 kbps. The ADM483E is intended for balanced data transmission and complies with both EIA Standards RS-485 and RS-422. It contains a differential line driver and a differential line receiver and is suitable for half duplex data transmission, as the driver and receiver share the same differential pins. The input impedance on the ADM483E is 12 k Ω , allowing up to 32 transceivers on the bus. The ADM483E operates from a single +5 V ± 10% power sup- ply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if, during fault conditions, a significant temperature increase is detected in the internal driver circuitry. The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM483E is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with robust bipolar technology. It is fully specified over the industrial temperature range and is available in 8-lead DIP and SOIC packages.
–2– REV. 0 ADM483E–SPECIFICATIONS Parameter Min Typ Max Units Test Conditions/Comments DRIVER Differential Output Voltage, V OD 5.0 V V CC = 5.25 V. R = ∞ , Figure 1 2.0 5.0 V R = 50 Ω (RS-422), Figure 1 1.5 5.0 V R = 27 Ω (RS-485), Figure 1 1.5 5.0 V V TST = –7 V to +12 V, Figure 2, V CC ≥ 4.75 V Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω , Figure 1 Common-Mode Output Voltage V OC 3 V R = 27 Ω or 50 Ω , Figure 1 Δ|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω Output Short Circuit Current (V OUT = High) 250 mA –7 V ≤ VO ≤ +12 V Output Short Circuit Current (V OUT = Low) 250 mA –7 V ≤ VO ≤ +12 V CMOS Input Logic Threshold Low, V INL 1.4 0.8 V CMOS Input Logic Threshold High, V INH 2.0 1.4 V Logic Input Current (DE, DI) ± 1.0 µA RECEIVER Differential Input Threshold Voltage, V TH –0.2 +0.2 V –7 V ≤ VCM ≤ +12 V Input Voltage Hysteresis, ΔVTH 70 mV V CM = 0 V Input Resistance 12 k Ω –7 V ≤ VCM ≤ +12 V Input Current (A, B) +1 mA V IN = 12 V –0.8 mA V IN = –7 V Logic Enable Input Current ( RE) ± 1 µA CMOS Output Voltage Low, V OL 0.4 V I OUT = +4.0 mA CMOS Output Voltage High, V OH 4.0 V I OUT = –4.0 mA Short Circuit Output Current 7 85 mA V OUT = GND or VCC Three-State Output Leakage Current ± 1.0 µA 0.4 V ≤ VOUT ≤ +2.4 V POWER SUPPLY CURRENT Outputs Unloaded, Receivers Enabled ICC (ADM483E) 36 60 µA DE = 0 V (Disabled) RE = 0 V 270 360 µA DE = 5 V (Enabled) = RE = 0 V Supply Current in Shutdown 0.1 10 µA DE = 0 V, RE = VCC ESD/EFT IMMUNITY ESD Protection ± 15 kV HBM Air Discharge. A, B Pins ± 3.5 kV HBM 3015.7 Contact Discharge. All Pins EFT Protection ± 2 kV IEC1000-4-4, A, B Pins EMI Immunity 10 V/m IEC1000-4-3 Specifications subject to change without notice. TIMING SPECIFICATIONS Parameter Min Typ Max Units Test Conditions/Comments DRIVER Propagation Delay Input to Output TPLH, TPHL 250 2000 ns R L Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 5 Driver O/P to O/P TSKEW 100 800 ns R L Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 5 Driver Rise/Fall Time T R, TF 250 2000 ns R L Diff = 54 Ω CL1 = CL2 = 100 pF, Figure 5 Driver Enable to Output Valid 250 2000 ns R L = 500 Ω , CL = 100 pF, Figure 3 Driver Disable Timing 300 3000 ns R L = 500 Ω , CL = 15 pF, Figure 3 RECEIVER Propagation Delay Input to Output TPLH, TPHL 250 2000 ns C L = 15 pF, Figure 5 Skew |TPLH–TPHL| 200 ns Receiver Enable TEN1 10 50 ns R L = 1 kΩ , CL = 15 pF, Figure 4 Receiver Disable TEN2 10 50 ns R L = 1 kΩ , CL = 15 pF, Figure 4 SHUTDOWN Time to Shutdown 50 200 600 ns Driver Enable from Shutdown 2000 ns R L = 500 Ω , CL = 100 pF, Figure 3 Receiver Enable from Shutdown 2500 ns R L = 1 kΩ , CL = 15 pF, Figure 4 Specifications subject to change without notice. (VCC = +5 V 6 10%. All specifications T MIN to TMAX unless otherwise noted) (VCC = +5 V 6 10%. All specifications T MIN to TMAX unless otherwise noted.)
–3–REV. 0 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Inputs Outputs ESD Rating: Air (Human Body Model) (A, B Pins) . . ± 15 kV ESD Rating: Contact (Human Body Model) ESD Rating MIL-STD-883B Method 3015 θ Operating Temperature Range *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Option ADM483EAN –40 °C to +85°C N-8 ADM483EAR –40 °C to +85°C SO-8 PIN FUNCTION DESCRIPTION Pin Mnemonic Function 1 RO Receiver Output. When enabled if A > B by 200 mV, then RO = High. If A < B by 200 mV, then RO = Low. 2 RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state. 3 DE Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places it in a high impedance state. 4 DI Driver Input. When the driver is enabled a logic Low on DI forces A low and B high while a logic High on DI forces A high and B low. 5 GND Ground Connection, 0 V.
6 A Noninverting Receiver Input A/Driver
Output A. 7 B Inverting Receiver Input B/Driver Output B. 8V CC Power Supply, 5 V ± 10%. PIN CONFIGURATION RE DE DI VCC B A GND TOP VIEW (Not to Scale) ADM483E RO Table I. Selection Table Part No. Duplex Data Rate Low Power Tx/Rx I CC No of Tx/Rx ESD EFT EMI kb/s Shutdown Enable mA On Bus kV kV V/m ADM483E Half 250 Yes Yes 36 32 ± 15 ± 21 0
Figure 11. Receiver Output Low Figure 14. Driver Output High Figure 17. Driver Output Waveform Figure 12. Receiver Output High
50 OUTPUT CURRENT – mA
Figure 15. Driver Differential Output Figure 18. Radiated Emissions Figure 13. Driver Output Low Figure 16. ADM483E Driving Figure 19. Conducted Emissions
EFT event without user intervention. lights, thyristor drives, inductive loads, etc. of anechoic chamber, stripline cell, TEM cell and GTEM cell.
- Temporary Degradation or loss of function that is self-
recoverable when the interfering signal is removed.
- Temporary degradation or loss of function that requires
- Degradation or loss of function that is not recoverable due to
30 V/m showed no performance degradation and error-free data
transmission continued even during irradiation. minimize the level of electromagnetic interference generated. Figure 25. Driver Output Waveform and FFT Plot Trans- improperly terminated cables. emissions predominate above this frequency. ADM483E are well below the allowable limits. Figure 26. Conducted Emissions Test Setup
–10– REV. 0 ADM483E OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35)SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 8-Pin Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
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–12– C2934–12–1/97PRINTED IN U.S.A.