ADM4210-2AUJZ-RL7

ADM4210 AD | Alldatasheet

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Rev. 0 | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 16 SPECIFICATIONS VCC = 2.7 V to 16.5 V , TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Conditions VCC PIN Operating Voltage Range VCC 2.7 16.5 V Supply Current ICC 0.65 3.5 mA Undervoltage Lockout VUVLO 2.2 2.5 2.65 V VCC rising Undervoltage Lockout Hysteresis VUVLOHYS 100 mV ON (ON-CLR) PIN Input Current IINON −10 0 +10 μA Threshold VON 1.22 1.3 1.38 V ON rising Threshold Hysteresis VONHYST 80 mV SENSE PIN Input Current IINSENSE −10 +5 +10 μA VSENSE = VCC Circuit Breaker Limit Voltage VCB 44 50 56 mV VCB = (VCC− VSENSE) GATE PIN Pull-Up Current IGATEUP −5 −10 −15 μA VGATE = 0 V Pull-Down Current IGATEDN 25 mA VTIMER = 1.5 V, VGATE = 3 V or VON = 0 V, VGATE = 3 V or VCC − VSENSE = 100 mV, VGATE = 3 V Gate Drive Voltage VGATE 4.5 7.5 10 V VGATE − VCC, VCC = 3 V 5.0 8.5 12 V VGATE − VCC, VCC = 3.3 V 8.75 12 16 V VGATE − VCC, VCC = 5 V 7.6 12 16 V VGATE − VCC, VCC = 12 V 6.0 11 18 V VGATE − VCC, VCC = 15 V TIMER PIN Pull-Up Current ITIMERUP −2 −5 −8.5 μA Initial cycle, VTIMER = 1 V −25 −60 −100 μA During current fault, VTIMER = 1 V Pull-Down Current ITIMERDN 2 3.5 μA After current fault, VTIMER = 1 V 100 μA Normal operation, VTIMER = 1 V Threshold High VTIMERH 1.22 1.3 1.38 V TIMER rising Threshold Low VTIMERL 0.15 0.2 0.25 V TIMER falling tOFF Turn-Off Time (TIMER Rise to GATE Fall) tOFF(TMRHIGH) 1 μs VTIMER = 0 V to 2 V step, VCC = VON = 5 V Turn-Off Time (ON (ON-CLR) Fall to GATE Fall) tOFF(ONLOW) 30 μs VON = 5 V to 0 V step, VCC = 5 V Turn-Off Time (VCC Rise to IC Reset) tOFF(VCCLOW) 30 μs VCC = 0 V to 2 V step, VON = 5 V

soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance degradation or loss of functionality.

Rev. 0 | Page 11 of 16 THEORY OF OPERATION Many systems require the insertion or removal of circuit boards to live backplanes. During this event, the supply bypass and hold- up capacitors can require substantial transient currents from the backplane power supply as they charge. These currents can cause permanent damage to connector pins or undesirable glitches and resets to the system. The ADM4210 is intended to control the powering of a system (on and off) in a controlled manner, allowing the board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM4210 can reside either on the backplane or on the removable board. OVERVIEW The ADM4210 operates over a supply range of 2.7 V to 16.5 V . As the supply voltage is coming up, an undervoltage lockout circuit checks if sufficient supply voltage is present for proper operation. During this period, the FET is held off by the GATE pin being held to GND. When the supply voltage reaches a level above UVLO and the ON (ON-CLR ) pin is high, an initial timing cycle ensures that the board is fully inserted in the backplane before turning on the FET . The TIMER pin capacitor sets the periods for all of the TIMER pin functions. After the initial timing cycle, the ADM4210 monitors the inrush current through an external sense resistor. Overcurrent conditions are actively limited to 50 mV/R SENSE for the circuit breaker timer limit. The ADM4210-1 automatically retries after a current limit fault and the ADM4210-2 latches off. The retry duty cycle on the ADM4210-1 timer function is limited to 3.8% for FET cooling. UVLO If the VCC supply is too low for normal operation, an under- voltage lockout circuit holds the ADM4210 in reset. The GATE pin is held to GND during this period. When the supply reaches this UVLO voltage, the ADM4210 starts when the ON (ON-CLR) pin condition is satisfied. ON (ON-CLR) PIN The ON (ON-CLR) pin is the enable pin. It is connected to a comparator that has a low-to-high threshold of 1.3 V with 80 mV hysteresis and a glitch filter. The ADM4210 is reset when the ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is high, the ADM4210 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting the device on the latched off model, the ADM4210-2. A low input on the ON (ON-CLR) pin turns off the external FET by pulling the GATE pin to ground and resets the timer. An external resistor divider at the ON (ON-CLR ) pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit. There is a glitch filter delay of approximately 3 μs on rising allowing the addition of an RC filter at the ON (ON-CLR) pin to increase the delay time at card insertion. If using a short pin system to enable the device, a pull-down resistor should be used to hold the device prior to insertion. GATE Gate drive for the external N-channel MOSFET is achieved using an internal charge pump. The gate driver consists of a 12 μA pull-up from the internal charge pump. There are various pull-down devices on this pin. At a hot swap condition the board is hot inserted to the supply bus. During this event, it is possible for the external FET GATE capacitance to be charged up by the sudden presence of the supply voltage. This can cause uncontrolled inrush currents. An internal strong pull-down circuit holds GATE low while in UVLO. This reduces current surges at inser- tion. After the initial timing cycle, the GATE is then pulled high. During an overcurrent condition, the ADM4210 servos the GATE pin in an attempt to maintain a constant current to the load until the circuit breaker timeout completes. In the event of a timeout, the GATE pin abruptly shuts down using the 4 mA pull-down device. Care must be taken not to load the GATE pin resistively because this reduces the gate drive capability. CURRENT LIMIT FUNCTION The ADM4210 features a fast response current control loop that actively limits the current by reducing the gate voltage of the external FET. This current is measured by monitoring the voltage drop across an external sense resistor. The ADM4210 tries to regulate the gate of the FET to achieve a 50 mV voltage drop across the sense resistor. CALCULATING THE CURRENT LIMIT The sense resistor connected between VCC and the SENSE pin is used to determine the nominal fault current limit. This is given by the following equation: ILIMITNOM = VCBNOM/RSENSENOM (1) The minimum load current is given by Equation 2 ILIMITMIN = VCBMIN/RSENSEMAX (2) The maximum load current is given by Equation 3 ILIMITMAX = VCBMAX/RSENSEMIN (3) For proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. The sense resistor power rating must exceed (VCBMAX)2/RSENSEMIN

2.90 BSC

0.95 BSC

0.10 MAX

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 34. 6-Lead Thin Small Outline Transistor Package [TSOT]

Rev. 0 | Page 15 of 16 NOTES

Rev. 0 | Page 16 of 16 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05132-0-7/06(0)