ADM4168E

ADM4168E (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 12

Technical content

±15 kV ESD Protected, Dual RS-422 Transceiver Data Sheet ADM4168E Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual RS-422 transceiver for ESD protection on bus input/output pins ±15 kV HBM ±8 kV IEC 61000-4-2, contact discharge ±8 kV IEC 61000-4-2, air discharge Complies with TIA/EIA-422-B and ITU-T recommendation V.11 Open circuit fail-safe Suitable for 5 V power supply applications Low supply current operation: 9 mA maximum Low driver output skew Receiver line input resistance: 30 kΩ typical Receiver common-mode range: −7 V to +7 V Power-up/power-down without glitches 16-lead TSSOP package Operating temperature range: −40°C to +85°C

APPLICATIONS

High data rate motor control Single-ended to differential signal conversion Point to point and multidrop transmission systems FUNCTIONAL BLOCK DIAGRAM RO1 DE1 DI1 VCC GND D1R1 ADM4168E RO2 DE2 DI2 D2R2 10820-001 Figure 1. GENERAL DESCRIPTION The ADM4168E is a dual RS-422 transceiver suitable for high speed communication on point to point and multidrop transmission lines. The ADM4168E is designed for balanced transmission lines and complies with TIA/EIA-422-B. The differential driver outputs and receiver inputs feature electro- static discharge (ESD) circuitry that provides protection up to ±15 kV human body model (HBM) and ±8 kV IEC 61000-4-2 (contact and air discharge). The ADM4168E operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or output shorting is prevented by short-circuit protection circuitry. Short- circuit protection circuits limit the maximum output current to −150 mA during fault conditions. The receivers of the ADM4168E contain a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM4168E is fully specified over the commercial and industrial temperature ranges and is available in a 16-lead TSSOP package.

Rev. B | Page 2 of 12 TABLE OF CONTENTS

REVISION HISTORY

6/2019—Rev. A to Rev. B 9/2017—Rev. 0 to Rev. A Added Applications Information Section, Figure 17; 9/2012—Revision 0: Initial Version

Rev. B | Page 3 of 12 SPECIFICATIONS 4.5 V ≤ VCC ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VCC = 5.0 V , unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOW SUPPLY CURRENT No load, drivers enabled Total Package ICC 4 6 mA Input voltage (VI) = VCC or GND 5 9 mA VI = 2.4 V or 0.5 V1 DRIVER Differential Outputs (Y1, Z1, Y2, Z2 Pins) Input Clamp Voltage VIK −1.5 V II = −18 mA Output Voltage High VOH 2.4 3.5 V VIH = 2 V, VIL = 0.8 V, output high voltage (IOH) = −20 mA Output Voltage Low VOL 0.2 0.4 V VIH = 2 V, VIL = 0.8 V, output low voltage (IOL) = 20 mA Differential Output Voltage No Load |VOD1| 2.0 6.0 V IO = 0 mA Outputs Loaded2 |VOD2| 2.0 3.7 V Load resistance (RL) = 100 Ω (see Figure 11) Δ|VOD| for Complementary Output States ∆|VOD| ±0.4 V RL = 100 Ω (see Figure 11) Common-Mode Output Voltage VOC ±3.0 V RL = 100 Ω (see Figure 11) Δ|VOC| for Complementary Output States Δ|VOC| ±0.4 V RL = 100 Ω (see Figure 11) Output Leakage Current IO 100 µA DEx = 0 V, VCC = 0 V or 5 V, output voltage (VO) = 6 V −100 µA DEx = 0 V, VCC = 0 V or 5 V, VO = −0.25 V Output Current (Short Circuit)3 IOS −30 −150 mA VO = VCC or GND Input Capacitance CI 6 pF Logic Inputs (DIx, DEx Pins) Input Voltage High VIH 2.0 V Input Voltage Low VIL 0.8 V Input Current High IIH 1 µA VI = VCC or VIH Input Current Low IIL −1 µA VI = GND or VIL RECEIVER Differential Inputs (A1, B1, A2, B2 Pins) Differential Input Threshold Voltage2 VTH −200 +200 mV Input Voltage Hysteresis VHYS 60 mV Input Current II 1.5 mA VI = 7 V, other input at 0 V −2.5 mA VI = −7 V, other input at 0 V Line Input Resistance RIN 12 30 kΩ VIC4 = −7 V to +7 V, other input at 0 V Logic Outputs (RO1, RO2 Pins) Output Voltage High VOH 3.8 4.2 V VID5 = 200 mV, IOH = −6 mA Output Voltage Low VOL 0.1 0.3 V VID = −200 mV, IOL = 6 mA 1 Measured per input with other inputs at VCC or GND. 2 For exact conditions, see TIA/EIA-422-B. 3 No more than one output shorted at any time, with the duration of the short not to exceed 1 second. 4 VIC is the receiver input common mode voltage. 5 VID is the receiver input differential voltage.

Rev. B | Page 4 of 12 TIMING SPECIFICATIONS 4.5 V ≤ VCC ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VCC = 5.0 V , unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate DRATE 30 Mbps R1, R2 = 50 Ω; R3 = 500 Ω; C1, C2, C3 = 40 pF Propagation Delay tDPLH, tDPHL 8 16 ns S1 open (see Figure 12 and Figure 13) Driver Output Skew tSK 1.5 4 ns S1 open (see Figure 12 and Figure 13) Rise Time/Fall Time tDR, tDF 5 10 ns S1 open (see Figure 12 and Figure 13) Enable Time tZH, tZL 10 19 ns S1 closed (see Figure 13 and Figure 14) Disable Time tHZ, tLZ 7 16 ns S1 closed (see Figure 13 and Figure 14) RECEIVER1 Propagation Delay tRPLH, tRPHL 9 15 27 ns Load capacitance (CL) = 50 pF (see Figure 15 and Figure 16) Transition Time tTLH, tTHL 4 9 ns VIC = 0 V, CL = 50 pF (see Figure 15 and Figure 16) 1 Measured per input with other inputs at VCC or GND.

Table 4. Thermal Resistance

Figure 2. Pin Configuration Table 5. Pin Function Descriptions 1 B1 Inverting Receiver Input B, Transceiver 1. 2 A1 Noninverting Receiver Input A, Transceiver 1. 3 RO1 Receiver Output, Transceiver 1. places the differential driver outputs in a high impedance state. 5 RO2 Receiver Output, Transceiver 2. 6 A2 Noninverting Receiver Input A, Transceiver 2. 7 B2 Inverting Receiver Input B, Transceiver 2. a logic high on DI2 forces Y2 high and Z2 low. 10 Y2 Noninverting Driver Output Y, Transceiver 2. 11 Z2 Inverting Driver Output Z, Transceiver 2. places the differential driver outputs in a high impedance state. 13 Z1 Inverting Driver Output Z, Transceiver 1. 14 Y1 Noninverting Driver Output Y, Transceiver 1. a logic high on DI1 forces Y1 high and Z1 low. 16 VCC Power Supply (5 V ± 10%).

is suitable for full duplex data transmission. high output state if the inputs are unconnected (floating). distortion free transmission. of electromagnetic interference (EMI). Table 6. Abbreviations in Truth Tables Table 7. Transmitting (Each Driver) Table 8. Receiving (Each Receiver)

Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the prop erty of their respective owners.