ADM1034

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Fan Speed (RPM) Controller ADM1034 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

1 local and 2 remote temperature channels ±1°C accuracy on local and remote channels Automatic remote temperature channels, up to 1 kΩ Fast (up to 64 measurements per second) SMBus 2.0, 1.1, and 1.0 compliant SMBus address input/LOCATION input to UDID Programmable over-/undertemperature limits Programmable fault queue SMBusALERT output Fail-safe overtemperature comparator output Fan speed (RPM) controller Look-up table for temperature-to-fan-speed control Linear and discrete options for look-up table FAN_FAULToutput THERM input, used to time PROCHOT assertions REF input, used as reference for THERM (PROCHOT) 3 V to 5.5 V supply Small 16-lead QSOP package

APPLICATIONS

Telecommunications equipment LCD projectors FUNCTIONAL BLOCK DIAGRAM ANALOG MULTIPLEXER TACH1 ALERT THERM SDA SCL GND VCC DRIVE1 ADM1034 TACH2 DRIVE2 LOCATION SMBUS ADDRESS MASK REGISTERS FAULT QUEUE THERM PERCENT TIMER FAULT QUEUE HYSTERESIS REGISTERS OFFSET REGISTERS CONVERSION RATE REGISTER CONFIGURATION REGISTERS BAND GAP REFERENCE BAND GAP TEMPERATURE SENSOR SRC BLOCK FAN SPEED COUNTER TEMPERATURE-TO- FAN-SPEED LOOK-UP TABLE MANUAL FAN SPEED CONTROL REGISTERS FAN RESPONSE TACH SIGNAL CONDITIONING FAN SPEED CONTROLLER ADC LIMIT COMPARATOR VALUE AND LIMIT REGISTERS STATUS REGISTER SERIAL BUS INTERFACE ADDRESS POINTER REGISTER D2– D2+ D1– D1+ FAN_FAULT REF ALERT THERM 04918-0-001 Figure 1.

Rev. 0 | Page 2 of 40 TABLE OF CONTENTS Programming the THERM Limit for Each T emperature

REVISION HISTORY

8/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 40 GENERAL DESCRIPTION The ADM1034 is a dual-channel remote- and local-temperature sensor and fan controller. The remote channels monitor the temperature of two remote thermal diodes, which may be discrete 2N3904/6s or may be located on a microprocessor die. The device also monitors its own ambient temperature. The ADM1034 can monitor and control the speed of two cooling fans. The user can program a target fan speed, or else use the look-up table to input a temperature-to-fan-speed profile. The look-up table can be configured to run the fans at discrete speeds (discrete mode) or to ramp the fan speed with temperature (linear mode). The ADM1034 communicates over a 2-wire SMBus 2.0 interface. An 8-level LOCATION input allows the user to choose between SMBus 1.1 and SMBus 2.0. An ALERT output indicates error conditions. The THERM I/O signals over- temperature as an output and times THERM assertions as an input. Pin 8 can be configured as a reference for the THERM (PROCHOT) input.

Rev. 0 | Page 4 of 40 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1 Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, VCC2 3.0 3.30 3.6 V Supply Current, ICC 3 mA Interface inactive, ADC active 900 µA Standby mode Undervoltage Lockout Threshold 2.5 V Power-On Reset Threshold 1 2.4 V TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ±1 ±2 °C 20°C ≤ TA ≤ 60°C Resolution 0.03125 °C External Diode Sensor Accuracy ±0.5 ±1 °C −40°C ≤ TD ≤ +100°C; TA = +40°C Resolution 0.03125 °C Remote Sensor Source Current 85 µA High level 34 µΑ Mid level 5 µΑ Low level Series Resistance Cancellation 1000 Ω Power Supply Sensitivity ±1 %/V Conversion Time (Local Temperature) 11 ms Averaging enabled Conversion Time (Remote Temperature) 32 ms Averaging enabled Total Conversion Time 75 ms Averaging enabled OPEN-DRAIN DIGITAL OUTPUTS (ALERT, THERM, FAN_FAULT, DRIVE1, DRIVE2)3 Output Low Voltage, VOL 0.4 V IOUT = −6.0 mA; VCC = +3 V High Level Output Leakage Current, IOH 0.1 1 µA VOUT = VCC; VCC = 3 V DIGITAL INPUT LEAKAGE CURRENT (TACH1, TACH2) Input High Current, IIH −1 µA −VIN = VCC Input Low Current, IIL 1 µA VIN = 0 Input Capacitance, CIN 7 pF DIGITAL INPUT LOGIC LEVELS (TACH1, TACH2) Input High Voltage, VIH 2.0 5.5 V Input Low Voltage, VIL −0.3 +0.8 V Hysteresis 500 mV p−p OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL 0.4 V IOUT = −6.0 mA; VCC High Level Output Leakage Current, IOH 0.1 1 µA VOUT = VCC SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.1 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV

VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2 Operation at 5.5 V is guaranteed by design, not production tested. 3 Recommend use of 100 kΩ pull-up resistors for all open-drain outputs from the ADM1034. 4 Guaranteed by design, not production tested. Figure 2. Serial Bus Timing Diagram

Rev. 0 | Page 6 of 40 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Positive Supply Voltage (VCC) −0.3 V to +6.5 V Voltage on Any Input or Output Pin except FAN_FAULT and LOCATION −0.3 V to +6.5 V Voltage on FAN_FAULT1 VCC Voltage on LOCATION VCC + 0.3 V Input Current at Any Pin ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering (10 s) 300°C IR Reflow Peak Temperature 220°C ESD Rating—All Pins 1500 V 1 During power-up the voltage on FAN_FAULT should not be higher than VCC. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 16-Lead QSOP Package: θJA = 150°C/W, θJC = 39°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 3. Pin Function Descriptions 1 DRIVE1 DRIVE1 Pin Drives Fan 1. Open-drain output. Requires a pull-up resistor. 2 TACH1 Fan 1 Fan Speed Measurement Input. Connects to the fan’s TACH output to measure the fan speed. 3 DRIVE2 DRIVE2 Pin Drives Fan 2. Open-drain output. Requires a pull-up resistor. 4 TACH2 Fan 2 Fan Speed Measurement Input. Connects to the fan’s TACH output to measure the fan speed. 5 GND Ground for Analog and Digital Circuitry. 6 VCC Power. Can be powered by 3.3 V standby power if monitoring in low power states is required. an INTEL CPU). A timer measures assertion times on the THERM pin (either input or output). 8 FAN_FAULT/REF FAN_FAULT: Open-Drain Output. Asserted low when one or both fans stall. Requires a pull-up resistor to VCC. REF: Analog Input Reference for the THERM Input. 9 D1− Cathode Connection for the First Thermal Diode or Diode-Connected Transistor. 10 D1+ Anode Connection for the First Thermal Diode or Diode-Connected Transistor. 11 D2− Cathode Connection for the Second Thermal Diode or Diode-Connected Transistor. 12 D2+ Anode Connection for the Second Thermal Diode or Diode-Connected Transistor. fixed-and-discoverable mode) and to set the LLL bits in the UDID (in ARP-capable mode). temperature. Can be configured as sticky SMBus mode or comparator mode. provided elsewhere in the system.

Figure 4. Temperature Error vs. PCB Track Resistance DXP to GND and VCC Figure 5. Remote Temperature Error vs. D+, D− Capacitance Figure 6. Remote Temperature Error vs. Series Resistance on D+ and D−

01 M 2M 3M 4M 65M

Figure 7. Remote Temperature Error vs. Power Supply Noise Frequency

01 M 2M 4M3M 5M 6M

Figure 8. Remote Temperature Error vs. Common-Mode Noise Frequency

01 M 3M2M 5M4M 6M

Figure 9. Remote Temperature Error vs. Differential Mode Noise Frequency

Table 4. Internal Register Descriptions Configuration Provides control and configuration of various functions on the device. Conversion Rate Determines the number of measurements per second completed by the ADM1034. first byte of data is always a register address, written to the address pointer register. Status Provides the status of each limit comparison. Interrupt Mask Allows the option to mask ALERTs due to particular out-of-limit conditions. Value and Limit Stores the results of temperature and fan speed measurements, along with their limit values. up to 15.875°C from a temperature reading. THERM Limit and Hysteresis Contains the temperature value at which THERM is asserted and indicates the level of hysteresis. Look-Up Table Used to program the look-up table for the fan-speed-to-temperature profile. percentage of a time window. The user can program the length of the time window. Table 5. Resistor Ratios for Setting LOCATION Bits 1 FD denotes fixed-and-discoverable mode, ARP denotes ARP-capable mode. Table 6. UDID Values random number address device). SMBus 2.0 as the Interface version.. random number (x). See Table 5 for information on setting the LLL bits.

Rev. 0 | Page 12 of 40 SMBus 2.0 FIXED-AND-DISCOVERABLE MODE The ADM1034 also supports fixed-and-discoverable mode, which is backwards-compatible with SMBus 1.0 and 1.1. Fixed- and-discoverable mode supports all the same functionality as ARP-capable mode, except for assign address—in which case it powers up with a fixed address and is not changed by the assign address call. The fixed address is determined by the state of the LOCATION pin on power-up. SMBus 2.0 READ AND WRITE OPERATIONS The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that an address/data stream is to follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, which consist of a 7-bit address (MSB first) plus an R/W bit. This last bit determines the direction of the data transfer (whether data is written to or read from the slave device). 1. The peripheral that corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, which is known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/ W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from it. 2. Data is sent over the serial bus in sequences of 9 clock pulses—8 bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. It is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot be changed without starting a new operation. To write data to one of the device data registers or to read data from it, the address pointer register (APR) must be set so that the correct data register is addressed; then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the APR. If data is to be written to the device, then the write operation contains a second data byte, which is written to the register selected by the APR. As illustrated in Figure 18, the device address is sent over the bus, followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the APR. The second data byte is the data to be written to the internal data register. When reading data from a register there are two possibilities. If the ADM1034’s APR value is unknown or incorrect, it must be set to the correct value before data can be read from the desired data register. To do this, perform a write to the ADM1034 as before, but send only the data byte containing the register. (See Figure 19.) A read operation is then performed, using the serial bus address and the R/ W bit set to 1, followed by the data byte read from the data register. (See Figure 20.) However, if the APR is already at the desired address, data can be read from the corresponding data register without first writing to the APR. In this case, Figure 19 can be omitted. In Figure 18 to Figure 20, the serial bus address is determined by the state of the LOCATION pin on power-up.

the local temperature sensor is 0.03125°C. updated even if the MSBs are locked. Table 7. Temperature Data Format Table 8. Local and Remote Sensor Extended Resolution is unsuitable for mass production. Figure 27. Measuring Temperature by Using Discreet Transistors

external sensor could work equally well as a discrete transistor. input and the base to the D+ input. waveform. This produces a dc voltage proportional to ∆Vbe. in two registers as a 13-bit word. averaging is enabled and 6 ms when averaging is disabled. +191.96875°C, although these are outside its operating range. Table 8. The data for the local and remote channels is stored in Local, Reg. 0x42 = Remote 1, and Reg. 0x44 = Remote 2). programmed high and low limits sets the appropriate status bit. Exceeding either limit can cause an SMBusALERT interrupt. Table 10. Temperature Measurement Limit Registers Figure 28. ADM1034 Signal Conditioning

the ADM1034 offer the systems designer added flexibility. Configuration 1 Register (Address 0x01). option to set up the ADM1034 to convert on one channel only. bit (Bit 7) in Configuration Register 2 (Address 0x02) to 0. Table 11. Channel Selector

00 Local Channel = Default

01 Remote 1 Channel

10 Remote 2 Channel

11 Reserved

Table 12. Offset Registers Table 13. Offset Register Values

microcontroller of an out-of-limit condition. Table 14. Temperature Limit Registers Table 15. THERM Limit Register whether the measured value is compared to a high or low limit. remote temperature measurement with averaging enabled. Once the conversion time elapses, the round robin starts again. synchronized with the temperature measurements in any way. located at Addresses 0x4F to 0x51. output has been pulled low by the ADM1034. as the error condition is gone. out of limit, its associated status bit is set in the status register.

Table 16. Interrupt Status Register 1 (Reg. 0x4F)

7 LH 1 = Local high temperature limit has been

6 LL 1 = Local low temperature limit has been

5 R1H 1 = Remote 1 high temperature limit has

4 R1L 1 = Remote 1 low temperature limit has

3 R1D 1 = Remote 1 diode error; indicates an open

or short on the D1+/D1− pins.

2 R2H 1 = Remote 2 high temperature limit has

1 R2L 1 = Remote 2 low temperature limit has

0 R2D 1 = Remote 2 diode error; indicates an open

or short on the D2+/D2− pins. Table 17. Status Register 2 (Reg. 0x50)

7 LT 1 = Local THERM temperature limit has

6 R1T 1 = Remote 1 THERM temperature limit has

5 R2T 1 = Remote 2 THERM temperature limit has

4 T% 1 = THERM % ontime limit has been

3 TA 1 = One of the THERM limits has been

Table 18. Status Register 3 (Reg. 0x51) 7 F1S 1 = Fan 1 has stalled. 5 F2S 1 = Fan 2 has stalled.

0 ALERT 1 = ALERT low; indicates the ALERT line has

output behaves when writing interrupt handler software. operate in either SMBusALERT mode or in comp mode. (Bit 3) of the Configuration Register 1 (Address 0x01) to 0. Configuration Register 1 (Address 0x01) to1. output is automatically pulled high again. whereas the comp mode ALERT output automatically resets. Figure 31. ALERT Comparator and SMBusALERT Outputs

Figure 32. Handling SMBusALERT

1. Detect an SMBus assertion.
2. Enter the interrupt handler.
3. Read the status register to identify the interrupt source.
4. Mask the interrupt source by setting the appropriate mask
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status register. If the interrupt status

bit clears, reset the corresponding interrupt mask bit to 0. being asserted; the appropriate status bit is still set as normal. Table 19. Mask Register 1 (Reg. 0x08)

7 LH 1 masks the ALERT for the local high

6 LL 1 masks the ALERT for the local low

5 R1H 1 masks the ALERT for the Remote 1 high

4 R1L 1 masks the ALERT for the Remote 1 low

3 R1D 1 masks the ALERT for the Remote 1 diode

2 R2H 1 masks the ALERT for the Remote 2 high

1 R2L 1 masks the ALERT for the Remote 2 low

0 R2D 1 masks the ALERT for the Remote 2 diode

Table 20. Mask Register 2 (Reg. 0x09)

4 T% 1 masks the ALERT for the THERM % ontime

3 TA 1 masks the ALERT for the THERM limit

2 TS 1 masks the ALERT for the THERM state; has

no effect on ALERT in ALERT comp mode. Table 21. Mask Register 3 (Reg. 0x0A) 7 F1S 1 masks the ALERT for Fan 1 stalling. 6 FA 1 masks the ALERT for fans at ALARM speed. 5 F2S 1 masks the ALERT for Fan 2 stalling.

the bits in the ALERT status registers. Table 22. Fault Queue Address 0x06

• SMBus ARA Command
• Read Status Register 1
• Power-On Reset The SMBusALERT clears, even if the condition that caused the SMBusALERT remains. The SMBusALERT is reasserted if the fault queue fills up. CONVERSION RATE REGISTER The ADM1034 makes up to 64 measurements per second. However, for the sake of reduced power consumption and better noise immunity, users may run the ADM1034 at a slower conversion rate. Better noise immunity results from the averaging that occurs at the slower conversion rates. Averaging does not occur at rates of 16, 32, or 64 conversions per second. Table 23 lists the available conversion rates. Note that the current round-robin loop must be finished for conversion rates changes to take effect. The conversion rate register is located at Address 0x05.

Table 23. Conversion Rates output by default on power-up. Figure 33. THERM Behavior

set in Configuration Register 2 (Address 0x02). THERM % On-Time Register (Address 0x4E). input, which is asserted continuously. Table 24. THERM % On-Time Window bit (Bit 0) of Configuration Register 4 (Address 0x04). events bit (Bit 1) of Configuration Register 4 (Address 0x04). events bit (Bit 2) of Configuration Register 4 (Address 0x04). percentage of the chosen time window. THERM % limit register is an 8-bit register. the time window has elapsed, assuming it is not masked.

measurement. These inputs are open-drain. be connected directly to the fan output. Figure 36. Fan with TACH Pull-Up to +VCC be chosen so that it is greater than VIH but less than 5 V. between 3 V and 5 V is suitable. Figure 37. Fan with TACH Pull-Up to Voltage > 5 V, Clamped with Zener Diode attenuator may be used, as shown in Figure 39.

2 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5 V

1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ. This gives a high input voltage of 3.83 V. Figure 38. Fan with Strong TACH. Pull-Up to >VCC or Totem-Pole Output, Clamped with Zener and Resistor. Figure 39. Fan with Strong TACH. Pull-Up to >VCC or Totem-Pole Output, proportional to the fan speed. measure for a full revolution.

Figure 40. Fan Speed Measurement for a 4-Pole Fan Table 25. TACH Value Registers preventing erroneous fan speed measurement readings. running very slowly (< 75 rpm). (Address 0x03) is correct for both fans. Configuration 2 Register (Address 0x02) is not set to 1. prevent situations like overshoot. Table 26. Fan Response Codes Table 27. Fan Response Register (Address 0x3C)

7 Reserved

3 Reserved

until the temperature drops below the T7 temperature value. When the look-up table is split in two, the same applies. decreasing temperature can be different. overrides the look-up table. Figure 43. Programming Two Points on the Look-Up Table Table 29. Look-Up Table Register Addresses table are used for both fans. increases) with temperature. increases with temperature to FSX+1 at temperature TX+1. speed once the temperature threshold is exceeded. Table 30. Drive X BHVR Bits

00 Local Temperature Controls Fan x

01 Remote 1 Temperature Controls Fan x

10 Remote 2 Temperature Controls Fan x

11 Fan x Runs at Full Speed

not be as important in the linear mode.

thresholds. Table 31 gives examples of values for programming. Table 31. Programming the Hysteresis exceeded under normal system operating conditions. The THERM temperature limit registers are listed in Table 32. Table 32. THERM Hysteresis Registers resolution of 1°C. Table 33 gives some examples. Table 33. Programming THERM Hysteresis Figure 44. XOR Tree Test default values, see Table 34 to Table 74.

Table 34. ADM1034 Registers

Table 35. Register 0x00, # Bytes/Block Read, POR = 0x20, Lock = Y, S/W Reset =Y <7:0> # Bytes Block Read R/W Block reads are # bytes/block read long. The maximum is 32 bytes, the SMBus transaction limit. Table 36. Register 0x01, Configuration Register 1, Power-On Default 0x01, Lock = Y, SW Reset = Y ADM1034 is in software/manual control mode. Default = 0. locked. 0 = ADM1034 registers unlocked. Default = 0. 5 SDA Timeout R/W 1 = SDA timeout enabled. 0 = SDA timeout disabled. Default = 0. 4 SCL Timeout R/W 1 = SCL timeout enabled. 0 = SDL timeout disabled. Default = 0. 3 ALERT Configuration R/W 0 = SMBusALERT. Default = 0. 1 = ALERT_COMP mode. 2 Enable THERM Timer R/W 1 = timer enabled, 0 = timer disabled. This bit enables THERM as an input. Default = 0. Table 37. Register 0x02, Configuration Register 2, Power-On Default 0x84, Lock = Y, SW Reset = Y mode. The ADC converts on one channel only, which is determined by the channel selector bits. <5:4> Channel Selector R/W This bit determines the channel on which the ADC converts. 3 4:8 Look-Up Table R/W This bit determines how many table points are used to control each fan.

Speed temperature between the two thresholds. Default = 1 = Linear. offset registers, and look-up table registers. This bit self-clears. Default = 0. Table 38. Register 0x03, Configuration Register 3, Power-On Default= 0x44, Lock = Y, SW Reset = Y always be an even number, because there cannot be an odd number of poles in a fan. always be an even number, because there cannot be an odd number of poles in a fan. Table 39. Register 0x04, Configuration Register 4, Power-On Default = 0x00, Lock = Y, SW Reset = Y is CMOS). 1 = Reference input for THERM. <6:4> THERM % Time Window R/W These bits set the time window over which THERM % is calculated. 3 XOR Test R/W Set this bit to 1 to enable the XOR connectivity test. is enabled and the Remote 2 temperature exceeeds its THERM limit. is enabled and the Remote 1 temperature exceeeds its THERM limit. is enabled and the local temperature exceeeds its THERM limit. Table 40. Register 0x05, Conversion Rate Register, Power-On Default = 0x07, Lock = Y, SW Reset = Y 7 Res R This bit is reserved for future use. Do not write to this bit. conversion rate until the start of the next round robin.

Table 41. Register 0x06, Fault Queue, Power-On Default = 0x01, Lock = Y, SW Reset = Y Table 42. Register 0x07, Fan Behavior Register, Power-On Default = 0x09, Lock = Y, SW Reset = Y 7 Fan2 Off R/W Set this bit to 1 to switch off Fan 2. 6 Fan1 Off R Set this bit to 1 to switch off Fan 1. <3:2> DRIVE2 BHVR R/W These bits determine which temperature source controls the DRIVE2 output. 00 = Local temperature controls DRIVE2. 01 = Remote 1 temperature controls DRIVE2. 10 = Remote 2 temperature controls DRIVE2. <1:0> DRIVE1 BHVR R/W These bits determine which temperature source controls the DRIVE1 output. 00 = Local temperature controls DRIVE1. 01 = Remote 1 temperature controls DRIVE1. 10 = Remote 2 temperature controls DRIVE1. Table 43. Register 0x08, Mask Register 1, Power-On Default = 0x52, Lock = N, SW Reset = Y 7 Local High R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. 6 Local Low R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. 5 Remote 1 High R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. 4 Remote 1 Low R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. 3 Remote 1 Diode Error R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. 2 Remote 2 High R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0. 1 Remote 2 Low R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 1. 0 Remote 2 Diode Error R/W A 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. The status bit is not affected. Default = 0.

Table 44. Register 0x09, Mask Register 2, Power-On Default = 0x10, Lock = N, SW Reset = Y 4 THERM % R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. 3 THERM Assert R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. 2 THERM_State R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the corresponding status bit does not generate an ALERT in that mode. Table 45. Register 0x0A, Mask Register 3, Power-On Default = 0x00, Lock = N, SW Reset = Y 7 Fan 1 Stalled R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. 6 Fan Alarm Speed R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. 5 Fan 2 Stalled R/W A 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. The status bit is not affected. Default = 0. 4 Reserved R Reserved. Default = 0. 3 Reserved R Reserved. Default = 0. 2 Reserved R Reserved. Default = 0. 1 Reserved R Reserved. Default = 0. 0 Reserved R Reserved. Default = 0. Table 46. Register 0x0B, Local High Limit, Power-On Default = 0x8B, Lock = N, SW Reset = N <7:0> Local High Limit R/W When the local temperature exceeds this temperature, the corresponding interrupt status bit is set. Table 47. Register 0x0C ,Local Low Limit, Power-On Default = 0x54, Lock = N, SW Reset = N Table 48. Register 0x0D, Local THERM Limit, Power-On Default = 0x95, Lock = Y, SW Reset = N Table 49. Register 0x0E, Remote 1 High Limit, Power-On Default = 0x8B, Lock = N, SW Reset = N Table 50. Register 0x0F, Remote 1 Low Limit, Power-On Default = 0x54, Lock = N, SW Reset = N

Table 51. Register 0x10, Remote 1 THERM Limit, Power-On Default = 0x95, Lock = Y, SW Reset = N and the THERM output is activated. Table 52. Register 0x11, Remote 2 High Limit, Power-On Default = 0x8B, Lock = N, SW Reset = N Table 53. Register 0x12, Remote 2 Low Limit, Power-On Default = 0x54, Lock = N, SW Reset = N Table 54. Register 0x13, Remote 2 THERM Limit, Power-On Default = 0x95, Lock = Y, SW Reset = N and the THERM output is activated. Table 55. Register 0x16, Local Offset Register, Power-On Default = 0x00, Lock = Y, SW Reset = N Table 56. Register 0x17, Remote 1 Offset Register, Power-On Default = 0x00, Lock = Y, SW Reset = N Table 57. Register 0x18, Remote 2 Offset Register, Power-On Default = 0x00, Lock = Y, SW Reset = N Table 58. Register 0x19, THERM Timer % Limit, Power-On Default = 0xFF, Lock = Y, SW Reset = N Table 59. Register 0x1A, THERM Hysteresis, Power-On Default = 0x05, Lock = Y, SW Reset = N

Table 60. Look-Up Table Registers, Lock = Y, SW Reset = Y Table 61. Register 0x3A, Look-Up Table Hysteresis, Power-On Default = 0x05 Lock = Y, SW Reset = Y Table 62. Register 0x3C, Fan Response Register, Power-On Default = 0x11, Lock = Y, SW Reset = Y <6:4> Fan 2 Response R/W These bits set the fan’s response in the fan speed control mode. <2:0> Fan 1 Response R/W These bits set the fan’s response in the fan speed control mode.

Table 63. Register 0x3D, Device ID, Power-On Default = 0x34, Lock = N, SW Reset = N <7:0> Device ID R This read-only value contains the device ID, which is 0x34. Table 64. Register 0x3E, Company ID, Power-On Default = 0x41, Lock = N, SW Reset = N <7:0> Company ID R This read-only value contains the company ID, which is 0x41. Table 65. Register 0x3F, Revision Register, Power-On Default = 0x02, Lock = N, SW Reset = N <7:0> Revision ID R This read-only value contains the revision ID. Table 66. Register 0x40/41, Local Temp Registers, Power-On Default = 0x00, Lock = N, SW Reset = Y R This register contains the LSBs of the last measured local temperature value. R This register contains the MSBs of the last measured local temperature value. Table 67. Register 0x42/43, Remote 1 Temp Registers, Power-On Default = 0x00, Lock = N, SW Reset = Y Table 68. Register 0x44/45, Remote 2 Temp Registers, Power-On Default = 0x00, Lock = N, SW Reset = Y Table 69. Register 0x4A/4B, TACH1 Period, Power-On Default = 0x00, Lock = N, SW Reset = Y <7:0> Fan 1 Period Count, LSB R This register contains the LSBs of the last measured Fan 1 revolution count. <15:8> Fan 1 Period Count, MSB R This register contains the MSBs of the last measured Fan 1 revolution count. Table 70. Register 0x4C/4D, TACH2 Period, Power-On Default = 0x00, Lock = N, SW Reset = Y <7:0> Fan 2 Period Count, LSB R This register contains the LSBs of the last measured Fan 2 revolution count. <15:8> Fan 2 Period Count, MSB R This register contains the MSBs of the last measured Fan 2 revolution count. Table 71. Register 0x4E, THERM % On-Time, Power-On Default = 0x00, Lock = N, SW Reset = Y <7:0> THERM % On-Time R Represents the % time of THERM activity within the time window set by the configuration bits.

Table 72. Register 0x4F, Status 1, Power-On Default = 0x00, Lock = N, SW Reset = Y 7 Local Temp High R A 1 indicates that the local high limit has been tripped. 6 Local Temp Low R A 1 indicates that the local low limit has been tripped. 5 Remote 1 Temp High R A 1 indicates that the Remote 1 high limit has been tripped. 4 Remote 1 Temp Low R A 1 indicates that the Remote 1 low limit has been tripped. 3 Remote 1 Diode Error R A 1 indicates that a short or an open has been detected on the Remote 1 temperature channel. This test is completed once on each conversion. 2 Remote 2 Temp High R A 1 indicates that the Remote 2 high limit has been tripped. 1 Remote 2 Temp Low R A 1 indicates that the Remote 2 low limit has been tripped. 0 Remote 2 Diode Error R A 1 indicates that a short or an open has been detected on the Remote 2 temperature channel. This test is completed once on each conversion. Table 73. Register 0x50, Status 2, Power-On Default = 0x00, Lock = N, SW Reset = Y 7 Local THERM R A 1 indicates that the local THERM limit has been tripped. 6 Remote 1 THERM R A 1 indicates that the Remote 1 THERM limit has been tripped. 5 Remote 2 THERM R A 1 indicates that the Remote 2 THERM limit has been tripped. 4 THERM % Exceeded R A 1 indicates that the THERM signal has been asserted for longer than the programmed limit. Clear on Read. If THERM % Limit = 0x00 and THERM is asserted, it is reasserted immediately. 3 THERM Asserted R A 1 indicates that the THERM signal has been asserted low as an input only. 2 THERM_State R A 1 indicates that the THERM pin has been asserted low as an output. Table 74. Register 0x51, Status Register 3, Power-On Default = 0x00, Lock = N, SW Reset = Y 7 Fan 1 Stalled R A 1 indicates that Fan 1 has stalled. a THERM temperature limit is exceeded. 5 Fan 2 Stalled R A 1 indicates that Fan 2 has stalled.

Figure 45. 16-Lead Shrink Small Outline Package [QSOP] registered tra demarks are the prop erty of their respective owners .