ADM1029

ADM1029 ONSEMI | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 ADM1029 * Dual PWM Fan Controller and Temperature Monitor for High Availability Systems FUNCTIONAL BLOCK DIAGRAM FAN 2 STATUS REGISTER INTERRUPT MASKING INTERRUPT MASK REGISTERS BANDGAP REFERENCE ANALOG MUX BANDGAP TEMP SENSOR ADC ADD AIN0/GPIO0 REMOTE SENSOR SIGNAL CONDITIONING G.P. I/O REGISTER VALUE AND LIMIT REGISTERS AIN1/GPIO1 D1+/GPIO4 D1–/GPIO3 LIMIT COMPARATOR TACH1 TACH2 FAULT2 PRESENT2 FAULT1 PRESENT1 DRIVE1 DRIVE2 FAN SPEED COUNTER ADDRESS POINTER REGISTER GND INT CFAULT D2–/GPIO5 D2+/GPIO6 RESET GPIO2 TMIN/INSTALL FAN 1 STATUS REGISTER SLAVE ADDRESS REGISTER SERIAL BUS INTERFACE SCL SDA VCC INTERRUPT STATUS REGISTERS FAN 1 ALARM SPEED REGISTER FAN 1 MIN SPEED REGISTER PWM CONTROLLER FAN 1 HOT-PLUG SPEED REGISTER FAN 2 HOT-PLUG SPEED REGISTER FAN 2 ALARM SPEED REGISTER FAN 2 MIN SPEED REGISTER PWM CONTROLLER ADM1029

FEATURES

Software Programmable and Automatic Fan Speed Control Automatic Fan Speed Control Allows Control Independent of CPU Intervention after Initial Setup Control Loop Minimizes Acoustic Noise and Power Consumption Remote and Local Temperature Monitoring Dual Fan Speed Measurement Supports Backup and Redundant Fans Supports Hot Swapping of Fans Cascadable Fault Output Allows Fault Signaling between Multiple ADM1029s Address Pin Allows Up to Eight ADM1029s in A System Small 24-Lead QSOP Package

APPLICATIONS

Network Servers and Personal Computers Microprocessor-Based Office Equipment High Availability Telecommunications Equipment *Protected by U.S. Patent Numbers 6,255,973 and 6,18 8,189 ©2009 SCILLC. All rights reserved. Publication Order Number: January 2009 - Rev. 1 ADM1029/D

Rev. 1 | Page 2 of 50 | www.onsemi.com ADM1029–SPECIFICATIONS 1, 2 (T A = T MIN to T MAX , V CC = V MIN to V MAX , unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, V CC 3.0 3.30 5.5 V Supply Current, I CC 1.7 3.0 mA Interface Inactive, ADC Active 1.5 mA ADC Inactive, DAC Active 10 60 µ A Shutdown Mode TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ± 1 ± 3 °C Resolution 1 °C External Diode Sensor Accuracy ± 3 ± 5 °C 0 °C ≤ T A ≤ 100 °C Resolution 1 °C Remote Sensor Source Current 90 µ A High Level 5.5 µ A Low Level ANALOG-TO-DIGITAL CONVERTER Total Unadjusted Error, TUE ± 1 % Note 3 Differential Nonlinearity, DNL ± 1 LSB Power Supply Sensitivity ± 1 %/ V Conversion Time Analog Input or Internal Temperature 11.6 ms External Temperature 185.6 ms FAN RPM-TO-DIGITAL CONVERTER Accuracy ± 6 % 60 °C ≤ T A ≤ 100 °C: V CC = 3.3 V Full-Scale Count 255 FAN 1 and FAN 2 Nominal Input RPM 4 8800 rpm Divisor = 1, Fan Count = 153 4400 rpm Divisor = 2, Fan Count = 153 2200 rpm Divisor = 4, Fan Count = 153 1100 rpm Divisor = 8, Fan Count = 153 Internal Clock Frequency 56.4 60.0 63.6 kHz OPEN-DRAIN DIGITAL OUTPUTS ( INT , CFAULT ) Output Low Voltage, V OL 0.4 V I OUT = –6.0 mA, V CC = 3 V High Level Output Current, I OH 0.1 1 µ A V OUT = V CC OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, V OL 0.4 V I OUT = –6.0 mA, V CC = 3 V High Level Output Leakage Current, I OH 0.1 1 µ A V OUT = V CC SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, V IH 2.1 V Input Low Voltage, V IL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS RESET , GPIO1-6, FAULT1/2, TACH1/2, PRESENT1/2 Input High Voltage, V IH 2.1 V Input Low Voltage, V IL 0.8 V DIGITAL INPUT CURRENT Input High Current, I IH –1 µ A V IN = V CC Input Low Current, I IL +1 µ A V IN = 0 Input Capacitance, C IN 20 pF SERIAL BUS TIMING 5 Clock Frequency, f SCLK 10 100 kHz See Figure 1 Glitch Immunity, t SW 50 ns See Figure 1 Bus Free Time, t BUF 4.7 µ s See Figure 1 Start Setup Time, t SU:STA 4.7 µ s See Figure 1 Start Hold Time, t HD:STA 4 µ s See Figure 1 Stop Condition Setup Time, t SU:STO 4 µ s See Figure 1

1All voltages are measured with respect to GND, unle ss otherwise specified. 2Typicals are at T A = 25 °C and represent most likely parametric norm. Shutdo wn current typ is measured with V CC = 3.3 V. 3TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer. 4The total fan count is based on two pulses per revo lution of the fan tachometer output. 5Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.1 V for a rising edge. Specifications subject to change without notice. conditions for extended periods may affect device r eliability. Figure 1. Diagram for Serial Bus Timing

Rev. 1 | Page 4 of 50 | www.onsemi.com PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DRIVE1 Open Drain Digital Output. Pulsewidth Modula ted (PWM) output to control the speed of Fan 1. Requires 10 k Ω typical pull-up resistor. 2 FAULT1 Open Drain Digital I/O. When used with a fan having a fault output, a Logic 0 input to this pin signals a fault on Fan 1. Also used as a fault outp ut. 3 TACH1 Open Drain Digital Input. Digital fan tachome ter input for Fan 1. Will accept logic signals up to 5 V even when V CC is lower than 5 V. 4 PRESENT1 Open Drain Digital Input. A shorting link in the fa n connector holds this pin low when Fan 1 is connected. 5 SCL Open Drain Digital Input. Serial Bus Clock. Req uires 2.2 k Ω pull-up typical. 6 SDA Digital I/O. Serial Bus bidirectional data. Ope n-drain output requires 2.2 k Ω pull-up.

7 GND System Ground

combination of 10 µ F (electrolytic or tantalum) and 0.1 µ F (ceramic) bypass capacitors. 9 CFAULT Open Drain Digital I/O. Cascade fault input/output used for fault signaling between multiple ADM1029s. 10 INT Digital Output. Interrupt Request (Open Drain). The output is enabled when Bit 1 of the Configuration Register is set to 0. The default sta te is enabled. 11 GPIO2 Open Drain Digital I/O. General-purpose logi c I/O pin. 12 RESET Open Drain Digital Input. Active low reset input. 13 D1–/GPIO3 Analog Input/Open Drain Digital I/O. Con nected to cathode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 14 D1+/GPIO4 Analog Input/Open Drain Digital I/O. Con nected to anode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 15 ADD Eight-Level Analog Input. Used to set the thre e LSBs of the serial bus address. 16 D2–/GPIO5 Analog Input/Open Drain Digital I/O. Con nected to cathode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 17 D2+/GPIO6 Analog Input/Open Drain Digital I/O. Con nected to anode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 18 TMIN/INSTALL Eight-Level Analog Input. The voltage on this pin defines whether automatic fan speed co ntrol is enabled, the minimum temperature at which the fa n(s) will turn on in automatic speed con- trol mode, and the number of fans that should be in stalled. 19 AIN0/GPIO0 Analog Input/Open Drain Digital I/O. Ma y be configured as a 0 V to 2.5 V analog input or a s a general-purpose digital I/O pin. 20 AIN1/GPIO1 Analog Input/Open Drain Digital I/O. Ma y be configured as a 0 V to 2.5 V analog input or a s a general-purpose digital I/O pin. 21 PRESENT2 Open Drain Digital Input. A shorting link in the fa n connector holds this pin low when Fan 2 is connected. 22 TACH2 Open Drain Digital Input. Digital fan tachom eter input for Fan 2. Will accept logic signals up to 5 V even when V CC is lower than 5 V. 23 FAULT2 Open Drain Digital I/O. When used with a fan having a fault output, a Logic 0 input to this pin signals a fault on Fan 2. Also used as a fault outp ut. 24 DRIVE2 Open Drain Digital Output. Pulsewidth Modul ated (PWM) output to control the speed of Fan 2. Requires 10 k Ω typical pull-up resistor. ADM1029

Rev. 1 | Page 5 of 50 | www.onsemi.com Typical Performance Characteristics–ADM1029 – 5 – 10 – 15 – 20 0 3.3 10 30 100 REMOTE TEMPERATURE ERROR – /H11543C LEAKAGE RESISTANCE – M /H9024 DXP TO GND DXP TO V CC (3.3V) TPC 1. Remote Temperature Error vs. PC Board Track Resistance 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 – 0.5 – 1.0 0 1 4 8 12 16 20 50 100 200 300 400 500 600 REMOTE TEMPERATURE ERROR – /H11543C FREQUENCY – MHz VIN = 100mV p-p VIN = 250mV p-p TPC 2. Remote Temperature Error vs. Power Supply Noise Frequency – 1 0 0.4 0.8 10 600 150 400 50 250 500 100 200 350 450 550 300 REMOTE TEMPERATURE ERROR – /H11543C FREQUENCY – MHz VIN = 40mV p-p VIN = 60mV p-p VIN = 100mV p-p TPC 3. Remote Temperature Error vs. Common-Mode Noise Frequency 110 100 0 10 20 30 40 50 60 70 80 90 100 110 READING MEASURED TEMPERATURE TPC 4. Pentium ® III Temperature Measurement vs. ADM1029 Reading – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10 – 11 – 12 – 13 – 14 – 15 – 16 REMOTE TEMPERATURE ERROR – /H11543C DXP – DXN CAPACITANCE – nF TPC 5. Remote Temperature Error vs. Capacitance Between D+ and D– 0 1 5 10 25 50 75 100 250 500 750 1000 SUPPLY CURRENT – /H9262A SCLK FREQUENCY – kHz VCC = 5V VCC = 3.3V TPC 6. Standby Current vs. Clock Frequency TPC = Typical Performance Characteristics Figure

Rev. 1 | Page 6 of 50 | www.onsemi.com – 1 0 600 12 400 20 300 100 500 1 4 8 16 50 200 REMOTE TEMPERATURE ERROR – /H11543C FREQUENCY – MHz VIN = 30mV p-p VIN = 20mV p-p VIN = 40mV p-p TPC 7. Remote Temperature Error vs. Differential-Mod e Noise Frequency SUPPLY CURRENT – /H9262A SUPPLY VOLTAGE – V TPC 8. Standby Supply Current vs. Supply Voltage 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 SUPPLY CURRENT – mA SUPPLY VOLTAGE – V TPC 9. Supply Current vs. Supply Voltage – 1 0 1 4 8 12 16 20 50 100 200 300 400 500 600 LOCAL TEMPERATURE ERROR – /H11543C FREQUENCY – MHz VIN = 100mV p-p VIN = 250mV p-p TPC 10. Local Sensor Temperature Error vs. Power Su pply Noise Frequency 120 110 100 0 1 2 3 4 5 6 7 8 9 10 TEMPERATURE – /H11543C TIME – Seconds TPC 11. ADM1029 Response to Thermal Shock ERROR – /H11543C TEMPERATURE – /H11543C 0.10 0.00 – 0.10 – 0.20 – 0.30 – 0.40 – 0.50 – 0.60 – 0.70 – 0.80 – 0.90 – 1.00 – 1.10 – 1.20 0 20 40 60 80 85 100 105 120 TPC 12. Remote Temperature Error TPC = Typical Performance Characteristics Figure ADM1029

Rev. 1 | Page 8 of 50 | www.onsemi.com Table I. Resistor Ratios for Setting Serial Bus Address

3 MSBs Ideal Ratio R1 R2 Actual Error

of ADC R2/(R1 + R2) (k /H9024) (k /H9024) R2/(R1 + R2) % Address

111 N/A 0 ∞ 1 0 0101111

110 0.8125 18 82 0.82 +0.75 0101110 101 0.6875 22 47 0.6812 –0.63 0101101 100 0.5625 12 15 0.5556 –0.69 0101100 011 0.4375 15 12 0.4444 +0.69 0101011 010 0.3125 47 22 0.3188 +0.63 0101010 001 0.1875 82 18 0.18 –0.75 0101001

000 N/A ∞ 0 0 0 0101000

The serial bus protocol operates as follows: 1. The master initiates data transfer by establishin g a START condition, defined as a high-to-low transition on t he serial data line SDA, while the serial clock line SCL rema ins high. This indicates that an address/data stream will fol low. All slave peripherals connected to the serial bus respo nd to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/ W bit, which deter- mines the direction of the data transfer, i.e., whe ther data will be written to or read from the slave device. The peripheral whose address corresponds to the tra nsmitted address responds by pulling the data line low durin g the low period before the ninth clock pulse, known as the A cknowl- edge Bit. All other devices on the bus now remain i dle while the selected device waits for data to be read from or written to it. If the R/ W bit is a 0, the master will write to the slave device. If the R/ W bit is a 1 the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowled ge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high tra nsition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted ov er the serial bus in a single READ or WRITE operation is l imited only by what the master and slave devices can handl e. 3. When all data bytes have been read or written, st op condi- tions are established. In WRITE mode, the master wi ll pull the data line high during the tenth clock pulse to assert a STOP condition. In READ mode, the master device wil l override the acknowledge bit by pulling the data li ne high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tent h clock pulse, high during the tenth clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed wi thout starting a new operation. ADM1029

Rev. 1 | Page 10 of 50 | www.onsemi.com In the case of the ADM1029, write operations contai n either one or two bytes, and read operations contain one b yte, and perform the following functions: To write data to one of the device data registers o r read data from it, the Address Pointer Register must be set s o that the correct data register is addressed, data can be wri tten into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address P ointer Regis- ter. If data is to be written to the device, the wr ite operation contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in Figure 4a. The device addres s is sent over the bus followed by R/ W set to 0. This is followed by two data bytes. The first data byte is the address of the in ternal data register to be written to, which is stored in the A ddress Pointer Register. The second data byte is the data to be wr itten to the internal data register. When reading data from a register there are two possibilities: 1. If the ADM1029’s Address Pointer Register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desi red data register. This is done by performing a write to the ADM1029 as before, but only the data byte containing the register address is sent, as data is not to be written to the regist er. This is shown in Figure 4b. A read operation is then performed consisting of th e serial bus address, R/ W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 4c. 2. If the Address Pointer Register is known to be al ready at the desired address, data can be read from the correspo nding data register without first writing to the Address Pointer Register, so Figure 4b can be omitted. Note: although it is possible to read a data byte f rom a data register without first writing to the Address Point er Register, if the Address Pointer Register is already at the c orrect value, it is not possible to write data to a register with out writing to the Address Pointer Register, because the first dat a byte of a write is always written to the Address Pointer Regi ster. ALERT RESPONSE ADDRESS The ADM1029 has an interrupt ( INT ) output that is asserted low when a fault condition occurs. Several INT outputs can be wire OR’d to a common interrupt line. When the host processor receives an interrupt request, it would normally ne ed to read the interrupt status register of each device to identif y which device had made the interrupt request. However, the ADM102 9 sup- ports the optional Alert Response Address function of the SMBus protocol. W hen the host processor receives an interrupt reques t it can send a general call address (0001100) over t he bus. The device asserting INT will then send its own slave address back to the host processor, so the device asserting INT can be identi- fied immediately. If more than one device is asserting INT , all devices will try to respond with their slave address, but an arbitratio n process ensures that only the lowest address will be receiv ed by the host. After sending its slave address, the first device w ill then clear its INT output. The host can then check if the INT is still low and send the general call again if necessary until all devices asserting INT have responded. The ARA function can be disabled by setting Bit 2 o f the Con- figuration Register (address 01h). TEMPERATURE MEASUREMENT SYSTEM LOCAL TEMPERATURE MEASUREMENT The ADM1029 contains an on-chip bandgap temperature sensor, whose output is digitized by the on-chip ADC. The t emperature data is stored in the Local Temp Value Register (ad dress A0h). As both positive and negative temperatures can be measured, the temperature data is stored in two’s complement format, as shown in Table II. Theoretically, the temperature sensor and ADC can measure temperatures from –128 °C to +127 °C with a resolution of 1 °C, but temperatures outside the operating temperatu re range of the device cannot be measured by the inter nal sensor. REMOTE TEMPERATURE MEASUREMENT The ADM1029 can measure the temperature of one or t wo remote diode-connected transistors, connected to Pi ns 13 and 14 and/or 16 and 17. The data from the temperature measure- ments is stored in the Remote 1 and Remote 2 Temp V alue Registers (addresses A1h and A2h). If two remote temperature measurements are not requ ired, Pins 16 and 17 can be reconfigured as general-purpose lo gic I/O pins, as explained later. The forward voltage of a diode or diode-connected t ransistor, operated at a constant current, exhibits a negative temperature coefficient of about –2 mV/ °C. The absolute value of V BE varies from device to device and individual calibration is required to null this out so, unfortunately, the technique is u nsuitable for mass production. The technique used in the ADM1029 is to measure the change in V BE when the device is operated at two different curre nts. This is given by: ∆ VBE = KT /q × ln( N) where: K is Boltzmann’s constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 5 shows the input signal conditioning used t o measure the output of a remote temperature sensor. This fig ure shows the external sensor as a substrate transistor, prov ided for tem- perature monitoring on some microprocessors, but it could equally well be a discrete transistor. If a discrete transistor is used, the collector wil l not be grounded, and should be linked to the base. If a PNP transist or is used, the base is connected to the D– input and the emitter t o the D+ input. If an NPN transistor is used, the emitter is connected to the D– input and the base to the D+ input. ADM1029

Figure 5. Signal Conditioning for Remote Diode Tempe rature Sensors depends on the setting of these registers, as explained later. up to 1000 pF may be placed between the D+/D– pins. 8-bit, two’s complement format, as illustrated in Table II. ues from –15 °C to +15 °C are allowed. are programmed, the temperature measurements are un altered.

ADM1029’s behavior for out-of-limit temperature measurements. present or not and if fans have been hot-swapped. ADM1029 how many fans it should be controlling/moni toring. fan is actually, physically, connected. still be reflected in the corresponding Fan Status Register.

1. Place the ADM1029 as close as possible to the rem ote sens-

this distance can be 4 to 8 inches.

1. Route the D+ and D– tracks close together, in par allel, with

under the tracks if possible.

1. Use wide tracks to minimize inductance and reduce noise

Figure 6. Arrangement of Signal Tracks

1. Try to minimize the number of copper/solder joint s, which

path and at the same temperature. them, thermocouple voltages should be much less than 200 µ V.

1. Place 0.1 µ F bypass and 1000 pF input filter capacitors close
2. If the distance to the remote sensor is more than 8 inches,
3. For really long distances (up to 100 feet), use s hielded

unconnected to avoid ground loops. introduces about 0.5 °C error. to temperature measurement and control.

Figure 7. Temperature Sensing Flowchart

and not Fan 1, or even have no fans installed. is used, Pin 18 would be set to some other level ac cording to Table VIII. corresponding Fan Status Registers at addresses 10h and 11h. input goes low. It must be cleared by writing a zer o to it. input(s) on the ADM1029 should be pulled high to V CC . failure indicator such as an LED. input goes high while the fault output is low. Bit 1 of the corresponding Fan Status Register. Free Wheel Test commences automatically. chip oscillator into the input of an 8-bit counter. until the counter overranges if the fan tach period is too long. the second fan (if installed) will be measured in t he same way. The measurement cycle will repeat until monitoring is disabled. registers at addresses 70h and 71h. ters (68h for Fan 1 and 69h for Fan 2). Figure 8. Fan Speed Measurement are programmed into the Tach Limit Registers for th e fans.

1. It should be noted that, since fan period rather than speed is

measurement exceeds the limit value.

Rev. 1 | Page 15 of 50 | www.onsemi.com ADM1029 For the most accurate fan failure indication, the o scillator frequency should be chosen to give as large a limit value as possible without the counter overranging. A count c lose to 3/4 full-scale or 191 is the optimum value. For example, if a fan produces two tach pulses per revolution and the fan failure speed is to be 600 rpm, the osc illator fre- quency should be set to 940 Hz. This will give a co unt at the fail speed of: 940 /H11003 4 /H11003 60/600/2 = 188 If the oscillator frequency were only 470 Hz, the c ount would be 94, while an oscillator frequency of 1880 Hz can not be used because the count would be 376 and the counter would overrange. FAN MONITORING CYCLE TIME Five complete tach periods are required to carry ou t a fan speed measurement Therefore, if the start of a fan measur ement just misses a rising edge, the measurement can take almo st six tach periods for each fan. The worst-case monitoring cycle time is when both f ans are under speed and the fan speed counter counts up to its maxi- mum value. The actual count takes 256 oscillator pu lses over four tach periods, plus a further two tach periods or 128 oscilla- tor pulses before the count starts. The total monit oring cycle time is therefore: t MEAS = 384/ fOSC (FAN 1) + 384/ fOSC (FAN 2) In order to read a valid result from the Fan Tach Value Registers, the total monitoring time allowed after starting th e monitoring cycle should be greater than this. TACH SIGNAL CONDITIONING Signal conditioning in the ADM1029 accommodates the slow rise and fall times typical of fan tachometer outpu ts. The maxi- mum input signal range is 0 V to 5 V, even if V CC is less than 5 V. In the event that these inputs are supplied fr om fan outputs that exceed 0 V to 5 V, either resistive attenuatio n of the fan signal or diode clamping must be included to keep i nputs within an acceptable range. Figures 9a to 9d show circuits for most common fan tach outputs. If the fan tach output has a resistive pull-up to V CC , it can be connected directly to the fan input, as shown in Figure 9a. 12V FAN SPEED COUNTER TACH1 OR TACH2 PULL-UP 4.7k /H9024 TYP TACH OUTPUT VCC Figure 9a. Fan with Tach Pull-Up to +V CC If the fan output has a resistive pull-up to 12 V ( or other voltage greater than 6.5 V), the fan output can be clamped with a Zener diode, as shown in Figure 9b. The Zener voltage sho uld be chosen so that it is greater than V IH but less than 6.5 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5 V is suitable. 12V FAN SPEED COUNTER TACH1 OR TACH2 TACH OUTPUT ZD1 * ZENER PULL-UP 4.7k /H9024 TYP *CHOOSE ZD1 VOLTAGE APPROX. 0.8 /H11547 V CC VCC

12 V) Clamped with Zener Diode

If the fan has a strong pull-up (less than 1 k Ω ) to 12 V, or a totem-pole output, a series resistor can be added t o limit the Zener current, as shown in Figure 9c. Alternatively, a resistive attenuator may be used, as shown in Figure 9d. R1 and R2 should be chosen such that:

2 V < V

PULLUP × R2/( RPULLUP + R1 + R2) < 5 V The fan inputs have an input resistance of nominall y 160 k Ω to ground, so this should be taken into account when c alculating resistor values. With a pull-up voltage of 12 V and pull-up resistor less than 1 k Ω , suitable values for R1 and R2 would be 100 k Ω and 47 k Ω . This will give a high input voltage of 3.83 V. 12V FAN SPEED COUNTER TACH1 OR TACH2 PULL-UP TYP <1k /H9024 OR TOTEM-POLE ZD1 ZENER * 10k /H9024 TACH O/P *CHOOSE ZD1 VOLTAGE APPROX. 0.8 /H11547 V CC VCC Figure 9c. Fan with Strong Tach. Pull-Up to >V CC or Totem-Pole Output, Clamped with Zener and Resistor 12V FAN SPEED COUNTER TACH1 OR TACH2 TACH OUTPUT R1 * R2 * <1k /H9024 VCC *SEE TEXT Figure 9d. Fan with Strong Tach. Pull-Up to >V CC or Totem-Pole Output, Attenuated with R1/R2 FAN SPEED CONTROL Fan speed is controlled using pulsewidth modulation (PWM). The PWM outputs (Pins 1 and 24) give a pulse output with a programmable frequency (default 250 Hz) and a duty- cycle defined by the contents of the relevant fan speed r egister, or by the automatic fan speed control when this mode is e nabled. The speed at which a fan runs is determined by fault co nditions and the settings of various control and mask registers. A fan can only be driven if it is defined as being supported by the controller in register 02h. The ADM1029 support s up to two fans, so Bits 0 and 1 of this register are perm anently set. This register is read-only.

Rev. 1 | Page 16 of 50 | www.onsemi.com A fan will only be driven if it is defined as being supported by the system in register 03h. If Bit 0 of this regist er is set, it indi- cates that Fan 1 is installed. This is the power-on default. If Bit 1 is set, it indicates that Fan 2 is installed. This bit is set by the state of Pin 18 at power-up. This register is r ead/write and the default/power-on setting can be overwritten. If a fan is not supported in register 03h it will not be driven, ev en if it is physi- cally installed. The PWM outputs are open-drain outputs. They require pull-up resistors and must be amplified and buffered to dri ve the fans. Minimum Speed The normal operating fan speed is set by the four L SBs of the Fan 1 and Fan 2 Minimum/Alarm Speed Registers (addr esses 60h, 61h). These bits also set the minimum speed at which a fan will run in automatic control mode. These bits shou ld be set to 05h. This corresponds to 33% PWM duty-cycle, which is the lowest speed at which most fans will run reliably. Fan(s) will run at minimum speed if there is no fau lt condition, automatic fan speed is disabled, and there are no o ther over- riding conditions. Alarm Speed Alarm speed is set by the four MSBs of the Fan 1 an d Fan 2 Minimum/Alarm Speed Registers (addresses 60h, 61h). Fan(s) will run at alarm speed if any of the following con ditions occurs, assuming the condition has not been masked out usin g the Fan Event Mask Registers:

• Setting Bit 0 of register 07h forces Fan 1 to run at alarm speed (Set Fan x Alarm Speed Register).
• Setting Bit 1 of register 07h forces Fan 2 to run at alarm speed (Set Fan x Alarm Speed Register). If monitoring is disabled by clearing Bit 4 of the Con- figuration Register, all fans controlled by the ADM 1029 will run at alarm speed.
• When a GPIO pin is configured as an input by settin g Bit 0 of the corresponding GPIO Behavior Register, and Bit 4 of the GPIO Behavior Register is also set, all fans contro lled by the ADM1029 will go to alarm speed when the logic input is asserted (high or low, depending on the polarity bi t, Bit 1 of the corresponding GPIO Behavior Register).
• If Bit 7 of a Fan Fault Action Register is set (18h —Fan 1, 19h —Fan 2) the corresponding fan will go to alarm spee d when CFAULT is pulled low by an external source.
• If a tach measurement exceeds the set limit, all fa ns controlled by the ADM1029 will run at alarm speed.
• If a fan fault input pin is asserted (low), all fan s controlled by the ADM1029 will run at alarm speed.
• If Bit 1 of a Temp. Fault Action Register is set (4 0h—Local Sensor, 41h—Remote 1, 42h—Remote 2), all fans contr olled by the ADM1029 will go to alarm speed if the corres ponding temperature high limit is exceeded.
• If Bit 5 of a Temp. Fault Action Register is set, a ll fans con- trolled by the ADM1029 will go to alarm speed if a temperature input crosses the corresponding temperature low lim it, the direction depending on the setting of Bit 3 of the Temp. Con- trol register. (0 = alarm when input goes below low limit, 1 = alarm when input goes above low limit).
• If Bit 1 of an AIN Behavior Register is set (50h—AI N0, 51h—AIN1), all fans controlled by the ADM1029 will go to alarm speed if the corresponding AIN high limit is exceeded.
• If Bit 5 of an AIN Behavior Register is set, all fa ns controlled by the ADM1029 will go to alarm speed if an analog input crosses the corresponding AIN low limit, the direction depend- ing on the setting of Bit 3 of the AIN control regi ster. (0 = alarm when input goes below low limit, 1 = alarm wh en input goes above low limit).
• If a thermal override occurs while the ADM1029 is i n sleep mode, all fans controlled by the ADM1029 will run a t alarm speed. Hot-Plug Speed Hot-plug speed is set by the four LSBs of the Fan 1 and Fan 2 Configuration Registers (addresses 68h and 69h). Th e PWM frequency is set by Bits 4 and 5 of these registers , while Bits 6 and 7 set the number of pulses per revolution for f an speed measurement. Fan(s) will run at hot-plug speed if any of the fol lowing condi- tions occur, assuming the condition has not been ma sked using the Fan Event Mask Registers:
• If a fan is unplugged, the other fan (if any) contr olled by the ADM1029 will run at hot-plug speed.
• Setting Bit 0 of register 08h forces Fan 1 to run a t hot-plug speed (Set Fan x Hot-Plug Speed).
• Setting Bit 1 of register 08h forces Fan 2 to run a t hot-plug speed (Set Fan x Hot-Plug Speed).
• When a GPIO pin is configured as an input by settin g Bit 0 of the corresponding GPIO Behavior Register, and Bit 5 of the GPIO Behavior Register is also set, all fans contro lled by the ADM1029 will go to hot-plug speed when the logic in put is asserted (high or low, depending on the polarity bi t, Bit 1 of the corresponding GPIO Behavior Register).
• If Bit 6 of a Fan Fault Action Register is set (18h for Fan 1, 19h for Fan 2) the corresponding fan will go to hot-plug speed when CFAULT is pulled low by an external source. Note: If operating conditions and register settings are such that both alarm speed and hot-plug speed would be trigge red, which one takes priority is determined by Bit 5 of the Fa n 1 and Fan 2 Status Registers (addresses 10h and 11h). If this bit is set, hot-plug speed takes priority. If it is cleared, alarm speed takes priority. Full Speed Fans will run at full speed if the corresponding bi ts in the Set Fan x Full Speed Register (address 09h) are set: Bi t 0 for Fan 1 and Bit 1 for Fan 2. Fan Mask Registers The effect of various conditions on fan speed can b e enabled or disabled by mask registers. In all these registers, setting Bit 0 of the register enables Fan 1 to go to alarm speed or hot-plug speed if the corresponding event occurs, while setting Bit 1 enables Fan 2. Clearing these bits masks the effect of the corr esponding event on fan speed. Registers 20h and 21h are Fan Event Mask Registers. Bits 0 and 1 of register 20h enable (bit set) or mask (bit cle ar) the effect of a Fan 1 fault (underspeed or fault input) on Fan 1 and Fan 2 speed. Similarly, Bits 0 and 1 of register 21h enab le (bit set) ADM1029

Rev. 1 | Page 17 of 50 | www.onsemi.com ADM1029 or mask (bit clear) the effect of a Fan 2 Fault on Fan 1 and Fan 2 speed. Registers 38h to 3Eh are GPIO X Event Mask Register s. Bits 0 and 1 of these registers enable or mask the effect of a GPIO assertion on Fan 1 and Fan 2 speed. Note: Registers 48h to 4Ah are Temp. Cooling Action Regis- ters. Bits 0 and 1 of these registers enable or mas k the effect of Local, Remote 1, and Remote 2 temperature faults on Fan 1 and Fan 2 speed. These registers also determine whi ch tempera- ture channel controls each fan in automatic fan spe ed control mode, as described later. Registers 58h and 59h are AIN Event Mask Registers. Bits 0 and 1 of these registers enable or mask the effect of an AIN out- of-limit event on Fan 1 and Fan 2 speed. MODES OF OPERATION The ADM1029 has three different modes of operation. These modes determine the behavior of the system. 1. PWM Duty Cycle Select Mode (directly sets fan spe ed under software control). 2. Thermal Trip Mode 3. Automatic Fan Speed Control Mode PWM DUTY CYCLE SELECT MODE The ADM1029 may be operated under software control by clearing bits <1:0> of the three Temp Cooling Actio n Registers (Reg 0x48, 0x49, 0x4A). Once under Software Control , each fan speed may be controlled by programming values o f PWM Duty Cycle in to the device. Values of PWM Duty Cycle between 0% to 100% may be written to the four LSBs of the F an 1 and Fan 2 Minimum/Alarm Speed Registers (addresses 60h, 61h). to control the speed of each fan. Table IV shows th e relationship between hex values written to the Minimum/Alarm Spe ed Reg- isters and PWM duty cycle obtained. Table IV. PWM Duty Cycle Select Mode Hex Value PWM Duty Cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% Recommended 06 40% 07 47% 08 53% 09 60% 0A 67% 0B 73% 0C 80% 0D 87% 0E 93% 0F 100% (Default) It is recommended that the minimum PWM duty cycle b e set to 33% (0x05). This has been determined to be the lowe st PWM duty cycle that most fans will run reliably at. Note that the PWM duty cycle values programmed in to these registers also define the PWM duty cycle that the fans will turn on at, i n Automatic Fan Speed Control Mode. It is recommended that afte r power- up, the PWM duty cycle is set to 33% before enabling Automatic Fan Speed Control. THERMAL TRIP MODE The ADM1029 can thermally trip the fan(s) for simpl e on/off fan control, or 2-speed fan control. For example, a fan can be programmed to run at 33% duty cycle. If the temperature exceeds the high temperature limit set for that temperature channel, the fan can automatically trip and run at Alarm Speed. The fan will continue to run at Alarm Speed even if the temperat ure error condition subsides, until the Latch Temp Fault bit (Bit 7 of the Temp x Fault Action Reg) is cleared in software by writing a 0 to it. To configure Fan 1 normally, run at 33% but to thermally trip to Alarm Speed for a Remote 2 measured tempera ture of 70 °C, set up the following registers: 1. Configure the normal PWM duty cycle for Fan 1 to 33%. Fan 1 Minimum/Alarm Speed Reg (0 x60) = 0xF 5 2. Set the Remote 2 High Temperature Limit = 70 °C. Remote 2 Temp High Limit Reg (0 x92) = 0x46 3. Configure Alarm Speed on Overtemperature function for Remote 2 Temperature channel. Set Bit 1 of Temp 2 Fault Action Reg (0 x42) 4. Enable Fan 1 to be controlled by Remote 2 Tempera ture. Set Bit 0 of Temp 2 Cooling Action Reg (0 x4A) Once the fan thermally trips to Alarm Speed, it wil l continue to run at Alarm Speed until the temperature drops belo w the High Temperature Limit and the Latch Temp Fault bit (Bit 7 of the Temp 2 Fault Action Reg) is cleared to 0. EVENT LATCH BITS Certain events that occur will cause latch bits to be set in vari- ous registers on the ADM1029. Once a latch bit is s et, it will need to be cleared by software for the system to re turn to nor- mal operation. To detect if a latch bit has been se t, the INT pin can be used to signal a latch event to the system s upervisor. Alternatively, the Status Registers can be polled p eriodically, and any latch bits that are set can be cleared. The events that cause latch bits to be set are: 1. Thermal Events. If the fan is run at Alarm Speed on Over- temperature or Undertemperature, this will set the Latch Temp Fault bit (Bit 7 of the Temp x Fault Action Re gisters 0x40–0x42). 2. Missing Fan. If a fan is missing, i.e., has been unplugged, the Missing Latch bit (Bit 1 of Fan x Status Registers) is set. 3. Hotplugged Fan. If a new fan is inserted into the system, Bit 7 (Hotplug Latch bit) of the Fan x Status Register is set. 4. FAULT Asserted. If the fan becomes stuck and its FAULT output asserts low, Bit 2 (Fault Latch bit) of the Fan x Status register is set. 5. TACH Failure. If the fan runs underspeed or becom es stuck, then Bit 6 (Tach Fault Latch Bit) of the Fan x Stat us Regis- ter is set. *Bits <3:0> set the Minimum PWM duty cycle, bits <7: 4> set the Alarm Speed PWM duty cycle for each fan.

of this register, when set, disables fan spin-up fo r both fans.

1 Bit 0 Register 0x49 and/or Bit 1 Reg 0x4A =

2 Bit 0 Register 0x48 and Bit 1 Register 0x48 = 1

3 Bit 0 Register 0x49 and Bit 1 Register 0x49 =

4 Bit 0 Register 0x4A and Bit 1 Register 0x4A =

5 Bits 0, 1 Reg 0x48, 0x49, 0x4A = 1 Max Speed

programmed control loops with different control par ameters. the temperature being measured, drives both fans. been programmed to 20 °C, and its T RANGE value is 40 °C. Figure 13. Max Speed Calculated by Local and Remote fore, the Remote 1 Temperature’s T MAX value will be 80 °C. fans will be driven at 66% duty cycle. temperature on another channel.

1. Program a value for T MIN .
2. Program a value for the slope T RANGE .
3. T MAX = T MIN + T RANGE .
4. Program a value for Fan Spin-up Time.
5. Program the desired Automatic Fan Speed Control M ode

Behavior, i.e., which temperature channel controls each fan. duty cycle affects the control loop behavior. Figure 14. Effect of Changing Minimum Duty Cycle on mum/Alarm Speed Registers and PWM duty cycle obtain ed. set the Alarm Speed PWM duty cycle.

Figure 15. Configuring Automatic Fan Speed Control

Rev. 1 | Page 22 of 50 | www.onsemi.com FAN-RELATED REGISTERS Table IX is a list of registers on the ADM1029 that are specific to fan speed measurement and control: Table IX. Fan-Specific Registers Address Description 0x02 Fans Supported By Controller 0x03 Fans Supported In System 0x07 Set Fan x Alarm Speed 0x08 Set Fan x Hot-Plug Speed 0x09 Set Fan x Full Speed 0x10 Fan 1 Status 0x11 Fan 2 Status 0x18 Fan 1 Fault Action 0x19 Fan 2 Fault Action 0x20 Fan 1 Event Mask 0x21 Fan 2 Event Mask 0x48 Local Temp Cooling Action 0x49 Remote 1 Cooling Action 0x4A Remote 2 Cooling Action 0x60 Fan 1 Minimum/Alarm Speed 0x61 Fan 2 Minimum/Alarm Speed 0x68 Fan 1 Configuration 0x69 Fan 2 Configuration 0x70 Fan 1 Tach Value 0x71 Fan 2 Tach Value 0x78 Fan 1 Tach High Limit 0x79 Fan 2 Tach High Limit FAN CONFIGURATION REGISTERS Registers 0x68 and 0x69 are the Fan 1 and Fan 2 Con figuration Registers. These allow the PWM output frequencies to be selected for each fan. The default PWM drive frequency is 25 0 Hz. Bits <7:6> adjust the fan tach oscillator frequency for fan tach mea- surements. Bits <3:0> allow the Hot Plug PWM duty cycle value for each fan to be programmed. Figures 16 and 17 show how to configure the fans to handle thermal or fault events. Table VIII. Resistor Ratios for Setting T MIN and Number of Fans Installed Using TMIN/INSTALL Pin (Pin 18)

3 MSBs Ideal Ratio R1 R2 Actual Error Fans

of ADC R2/(R1 + R2) (k /H9024) (k /H9024) R2/(R1 + R2) (%) T MIN Installed

111 N/A 0 /H11009 1 0 Disabled 2

110 0.8125 18 82 0.82 0.75 48 °C 2 101 0.6875 22 47 0.6812 –0.63 40 °C 2 100 0.5625 12 15 0.5556 –0.69 32 °C 2 011 0.4375 15 12 0.4444 0.69 32 °C 1 010 0.3125 47 22 0.3188 0.63 40 °C 1 001 0.1875 82 18 0.18 –0.75 48 °C 1

000 N/A /H11009 0 0 0 Disabled 1

In this case, since the Minimum Duty Cycle is the d efault 33%, the equation for T MAX reduces to: TMAX = T MIN + ((Max DC – Min DC) × T RANGE /10) TMAX = T MIN + ((15 – 5) × T RANGE /10) TMAX = T MIN + (10 × T RANGE /10) TMAX = T MIN + T RANGE ENABLING AUTOMATIC FAN SPEED CONTROL USING TMIN/INSTALL PIN (PIN 18) Automatic fan control can also be enabled in hardwa re by Pin 18 (TMIN/INSTALL). This is an 8-level input with mu ltiple functions, which is sampled only at power-up. If only one fan is installed, the voltage on Pin 18 should be kept at less than V CC /2, which clears Bit 1 of register 03h. Within this voltage range, four voltage levels define the minimum temperature at which the fan will operate in automatic speed co ntrol mode. If two fans are installed, the voltage on Pin 18 should be between VCC /2 and V CC , which sets Bit 1 of register 03h. Within this voltage range, four voltage levels define the minimum temperature at which the fans will operate in automatic speed control mode. Resistor values for setting the voltage on Pin 18 a re given in Table VIII. If automatic fan speed control is not used, Pin 18 can simply be strapped to ground (one fan) or V CC (two fans), depending on how many fans are installed. Under thi s condi- tion, the fans will run full speed until the device is written to by software to change fan speed. When automatic fan speed control is enabled at powe r-up by the TMIN/INSTALL pin, Bit 4 of the Configuration re gister is set to enable monitoring, and Bits 0 and 1 of all T emp. Cooling Action Registers are set, so any temperature channe l will auto- matically control all fans that are installed. Note: if automatic fan speed control is enabled and an event occurs that would cause a fan to go to alarm or hot -plug speed (e.g., temperature fault), that event will override the automatic fan speed control. If the event affects only one fa n, the other fan will remain under automatic control. ADM1029

Figure 16. Fan Configuration Flowchart

Figure 17. Fan Configuration Flowchart (Continued)

Rev. 1 | Page 25 of 50 | www.onsemi.com ADM1029 RESET INPUT Pin 12 is an active-low system RESET input. Taking this pin low will generate a system reset, which will reset all registers to their default values. ANALOG INPUTS Pins 19 and 20 of the ADM1029 are dual-function pin s. They may be configured as general-purpose logic I/O pins by setting Bits 0, 1 of the GPIO Present/AIN Register (address 05h) or as 0 V to 2.5 V analog inputs by clearing these bit s. In the analog input mode, Pins 19 and 20 have an in put range of 0 V to 2.5 V. By suitable input scaling, the ana log input may be configured to measure other voltage ranges such as system power supply voltages. If more than one ADM1029 is used in a system, several such voltages may be monitored. The measured values of AIN0 and AIN 1 are stored in the AIN0 and AIN1 Value Registers (addresses B8h and B9 h) and are compared to high and low limits stored in the A IN0 and AIN1 High and Low Limit Registers (addresses A8h, A 9h and B0h, B1h). The response of the ADM1029 to an out-of-limit meas urement on AIN0 or AIN1 depends on the status of the AIN0 a nd AIN1 Behavior Registers (Registers 50h, 51h). The respon se of CFAULT , INT , and fan speed to temperature events depends on the setting of these registers, as detailed in t he register tables later in this data sheet. Figure 18 shows how the A IN pins can be configured to respond to different events. ANALOG MONITORING CYCLE The ADM1029 performs a sequential “round-robin,” mo nitor- ing cycle on all analog inputs and temperature inpu ts that are enabled. A conversion on AIN0 or AIN1 typically takes 11.6 ms, while an external temperature conversion takes 185. 6 ms. INTERRUPT (INT ) OUTPUT The INT output is an open-drain output with selectable pol ar- ity, intended to communicate fault conditions to th e host processor. The polarity is set to active low by cle aring Bit 7 of the Configuration Register (address 01h) or to acti ve high by setting this bit. INT can be asserted if any of the following conditions occur:

• A hot-plug event.
• Setting Bit 6 of the Configuration Register (addres s 01h) forces INT to be asserted.
• When a GPIO pin is configured as an input by settin g Bit 0 of the corresponding GPIO Behavior Register and Bit 3 of the GPIO Behavior Register is also set, INT will be asserted when the logic input is asserted (high or low, depending on the polar- ity bit, Bit 1 of the corresponding GPIO Behavior Register).
• If Bit 2 of a Temp. Fault Action Register is set (4 0h—Local Sensor, 41h—Remote 1, 42h—Remote 2), INT will be asserted if the corresponding temperature high limit is exce eded.
• If Bit 6 of a Temp. Fault Action Register is set, INT will be asserted if a temperature input crosses the corresp onding temperature low limit, the direction depending on t he setting of Bit 3 of the Temp. Fault Action register. (0 = INT when temperature goes below low limit, 1 = INT when temperature goes above low limit).
• If Bit 1 of a Fan Fault Action Register (18h or 19h ) is set, INT will be asserted when a tach measurement for the c orre- sponding fan exceeds the set limit .
• If Bit 1 of a Fan Fault Action Register (18h or 19h ) is set, INT will be asserted when the fan fault input pin for the cor- responding fan is asserted (low).
• If Bit 2 of an AIN Behavior Register is set (50h—AI N0, 51h— AIN1), INT will be asserted if the corresponding AIN high limit is exceeded.
• If Bit 6 of an AIN Behavior Register is set, INT will be asserted if the corresponding analog input crosses its AIN l ow limit, the direction depending on the setting of Bit 3 of the AIN Behavior register. (0 = INT when input goes below low limit, 1 = INT when input goes above low limit). FAN FREE-WHEELING TEST The Fan Free Wheeling Test is used to diagnose fans connected to the ADM1029 to ensure that they are operating co rrectly. Large fans tightly coupled in a duct can affect eac h other’s air- flow. If one fan has failed it may not be apparent, as the other fan moving can suck air through the faulty fan caus ing it to spin. The ADM1029 will spin each fan up separately with t he other powered down and measure the fan speed of both. Whe n it tries to spin the failed fan with the working fan off, th e fan speed measurement will fail, and the faulty fan will be d etected. The Fan Free-Wheel Test can be invoked at any time in s oftware by setting Bit 3 of the Configuration Register (Reg. 0 x01). The Fan Free-Wheel Test normally takes about 10 seconds. On ce the Fan Free-Wheel test has completed, Bit 3 will autom atically clear to 0. Automatic Fan Free-Wheel Test Whenever a fan is hot-plugged, the Fan Free-Wheel T est is automatically invoked. Bit 3 gets set high automatically and once the test has completed, self-clears to 0. If 2 fans are installed in the system, the Fan Free-Wheel Test is invoked by r emoving the suspect fan and hotplugging a new one. When the sus pect fan (e.g., Fan 1) is removed, the Missing bit (Bit 0) a nd Missing Latch bit (Bit 1) of the Fan 1 Status Register are set. Fan 2 will then automatically run at HotPlug Speed. If the fau lty fan is replaced, the HotPlug Latch bit (Bit 7) is set and the Missing bit (Bit 0) self-clears. (However, the Missing Latc h bit remains set.) Fan 2 will return to its previous value autom atically and the Fan Free-Wheel Test is invoked. Fan 1 is run at 100% while Fan 2 is turned off. Fan 2 is then run at 100% with Fan 1 turned off. Both fans are then spun-up for the Fan Spin-up time. Note that the Hotplug Latch bit and Missing Latch bit re mains set (Bits 7 and 1). These need to be cleared to 0 befor e a subse- quent Fan Free-Wheel Test can occur. Otherwise, sub sequent fan removals and insertions are ignored.

Figure 18. Configuring AIN0 and AIN1 Pins

Rev. 1 | Page 27 of 50 | www.onsemi.com ADM1029 GENERAL PURPOSE LOGIC INPUT/OUTPUTS The ADM1029 has six dual-function pins (see Pin Fun ction Descriptions section) that may be configured as general-purpose Logic I/O pins by setting the appropriate bit(s) of the GPIO Present/AIN Register (address 05h) or as their alte rnate func- tions by clearing these bits. When configured as GPIO pins, each GPIO pin has a B ehavior Register associated with it (Registers 28h to 2Eh) that may be used to configure the operation of the pin. The GPIO pins may be configured as inputs or output s. When used as inputs, they may be configured to:

• Be active high or active low.
• Set/clear a bit in the Behavior Register when GP in put is asserted/deasserted.
• Latch a bit in the Behavior Register when GP input is asserted (must be cleared by software).
• Assert CFAULT when GP input asserted.
• Assert INT when GP input asserted.
• Set fan(s) to alarm speed when GP input asserted.
• Set fan(s) to hot-plug speed when GP input asserted . When used as outputs, they may be configured to:
• Be active high or low
• Be asserted if a High Temperature Limit is exceeded .
• Be asserted if a temperature measurement falls belo w a low limit.
• Be asserted if a fan fault is detected.
• Be asserted if a fan tach limit is exceeded.
• Be asserted if an AIN high limit is exceeded.
• Be asserted if an analog input falls below a low li mit. Figure 19 shows how to configure the GPIO pins to h andle different out-of-limit and fault events. CFAULT OUTPUT The Cascade Fault output ( CFAULT ), is an open-drain, active low output, intended to communicate fault condition s to other ADM1029s in a system, without the intervention of the host pro- cessor. The other ADM1029’s may then adjust their f ans’ speed to compensate, depending on the settings of various registers. CFAULT is asserted if any of the following conditions occ urs:
• A hot-plug event.
• Setting Bit 5 of the Configuration Register (addres s 01h) forces CFAULT to be asserted.
• When a GPIO pin is configured as an input by settin g Bit 0 of the corresponding GPIO Behavior Register and Bit 2 of the GPIO Behavior Register is also set, CFAULT will be asserted when the logic input is asserted (high or low depen ding on the polarity bit, Bit 1 of the corresponding GPIO Behavior Register).
• If Bit 0 of a Temp. Fault Action Register is set (4 0h—Local Sensor, 41h—Remote 1, 42h—Remote 2), CFAULT will be asserted if the corresponding temperature high limit is exceeded.
• If Bit 4 of a Temp. Fault Action Register is set, CFAULT will be asserted if a temperature input crosses the corr esponding temperature low limit, the direction depending on t he setting of Bit 3 of the Temp. Fault Action Register. (0 = CFAULT when input goes below low limit, 1 = CFAULT when input goes above low limit).
• If Bit 0 of a Fan Fault Action Register (18h or 19h ) is set, CFAULT will be asserted when a tach measurement for the corresponding fan exceeds the set limit.
• If Bit 0 of a Fan Fault Action Register (18h or 19h ) is set, CFAULT will be asserted, when the fan fault input pin for the corresponding fan is asserted (low).
• If Bit 0 of an AIN Behavior Register is set (50h—AI N0, 51h—AIN1), CFAULT will be asserted if the corresponding AIN high limit is exceeded.
• If Bit 4 of an AIN Behavior Register is set, CFAULT will be asserted if an analog input crosses the correspondi ng AIN low limit, the direction depending on the setting of Bi t 3 of the AIN Behavior Register. (0 = CFAULT when input goes below low limit, 1 = CFAULT when input goes above low limit).

BIT 2 = 1 IF GPIO PIN IS CONFIGURED AS AN INPUT, CFAULT IS ASSERTED WHEN GPIO IS ASSERTED. PIN IS AN OUTPUT, GPIO IS ASSERTED IF A TEMPERATURE LOW LIMIT IS EXCEEDED. GPIO PIN IS AN OUTPUT, GPIO IS ASSERTED IF A FAN TACH LIMIT IS EXCEEDED. BIT 5 = 1 IF GPIO PIN IS CONFIGURED AS AN INPUT, FANS GO TO HOT-PL UG SPEED IF GPIO IS ASSERTED. IF GPIO PIN IS AN OUTPUT, GPIO IS ASSERTED IF A FAN FAULT IS DETECTED (FAULT PIN). OUTPUT, GPIO IS ASSERTED IF AN AIN HIGH LIMIT IS EXCEEDED. WRITING A '0.' IF GPIO PIN IS AN INPUT, GPIO IS ASSERTED IF AN AI N LOW LIMIT IS EXCEEDED. Figure 19. Configuring GPIO Pins

Rev. 1 | Page 29 of 50 | www.onsemi.com ADM1029 Table X. Register Map Address Name Default Value Description 00 Status Register 00h Contains the status of various fault conditions. 01 Config Register 0000 0000 Configures the operation of the device. 02 Fan Supported By Controller 03h Contains the number of fans the device can support. 03 Fans Supported In System 0000 00?1 Contains the num ber of fans actually supported by the device in the application. 04 GPIOs Supported By Controller 7Fh Contains the numb er of GPIO pins the device can support. 05 GPIO Present/AIN 0????111 Used to configure GPIO pi ns as GPIO or as their alternate analog input function. 06 Temp Devices Installed 0000 0??1 Contains number of temperature sensors installed. 07 Set Fan x Alarm Speed 00h Writing to appropriate bi t(s) makes fan(s) run at alarm speed. 08 Set Fan x Hot-Plug Speed 00h Writing to appropriate bit(s) makes fan(s) run at hot-plug speed. 09 Set Fan x Full Speed 00h Writing to appropriate bit (s) makes fan(s) run at full speed. 0B S/W RESET 00h Writing A6h to this register causes a software reset. 0C Fan Spin-Up 03h Configures fan spin-up time. 0D Manufacturer’s ID 41h This register contains the ma nufacturer’s ID code for the device. 0E Major/Minor Revision 00h Contains the manufacturer’ s code for major and minor revi- sions to the device in two nibbles. 0F Manufacturer’s Test Register 00h This register is u sed by the manufacturer for test purposes. It should not be read from or written to in normal ope ration. 10 Fan 1 Status 0000 0?0? Contains status information for FAN 1. 11 Fan 2 Status 0000 0?0? Contains status information for FAN 2. 18 Fan 1 Fault Action BFh Sets operation of INT , CFAULT , etc., for FAN 1 fault. 19 Fan 2 Fault Action BFh Sets operation of INT , CFAULT , etc., for FAN 2 fault.

20 Fan 1 Event Mask FFh Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed

in response to a fault or hot-plug event on FAN 1.

21 Fan 2 Event Mask FFh Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed

in response to a fault or hot-plug event on FAN 2. 28 GPIO0 Behavior 00h Configures the operation of GPIO 0. 29 GPIO1 Behavior 00h Configures the operation of GPIO 1. 2A GPIO2 Behavior 00h Configures the operation of GPIO 2. 2B GPIO3 Behavior 00h Configures the operation of GPIO 3. 2C GPIO4 Behavior 00h Configures the operation of GPIO 4. 2D GPIO5 Behavior 00h Configures the operation of GPIO 5. 2E GPIO6 Behavior 00h Configures the operation of GPIO 6. 30 Local Temperature Offset 00h Offset register for lo cal temperature measurement. The value in this register is added to the local temperature value to reduce system offset effects. 31 Remote 1 Temperature Offset 00h Offset register for first remote temperature channel (D1). The value in this register is added to the temperature value to reduce system offset effects. 32 Remote 2 Temperature Offset 00h Offset register for second remote temperature channel (D2). The value in this register is added to the temperat ure value to reduce system offset effects.

38 GPIO0 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed

in response to GPIO0 being asserted.

39 GPIO1 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed

in response to GPIO1 being asserted. 3A GPIO2 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed in response to GPIO2 being asserted. 3B GPIO3 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed in response to GPIO3 being asserted.

Rev. 1 | Page 30 of 50 | www.onsemi.com Table X. Register Map (Continued) Address Name Default Value Description 3C GPIO4 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed in response to GPIO4 being asserted. 3D GPIO5 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed in response to GPIO5 being asserted. 3E GPIO6 Event Mask 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed in response to GPIO6 being asserted. 40 Local Temp Fault Action 08h Configures the operatio n of INT , CFAULT , etc. for a Local Temp fault (internal temperature sensor). 41 Remote 1 Temp Fault Action 08h Configures the opera tion of INT , CFAULT , etc. for a Remote 1 Temp fault (D1 Temperature Sensor). 42 Remote 2 Temp Fault Action 08h Configures the opera tion of INT , CFAULT , etc. for a Remote 2 Temp fault (D2 Temperature Sensor).

48 Local Temp Cooling Action 00h Enables/disables FAN 1 and/or FAN 2 alarm/hot-plug speed

in response to a Local Temp event (internal temperature sensor).

49 Remote 1 Temp Cooling Action 00h Enables/disables F AN 1 and/or FAN 2 alarm/hot-plug speed

in response to a Remote 1 Temp event (D1 temperature sensor). 4A Remote 2 Temp Cooling Action 00h Enables/disables F AN 1 and/or FAN 2 alarm/hot-plug speed in response to a Remote 2 Temp event (D2 temperature sensor). 50 AIN0 Behavior 00h Configures the operation of INT , CFAULT , etc. for a fault on Analog Channel 0. 51 AIN1 Behavior 00h Configures the operation of INT , CFAULT , etc. for a fault on Analog Channel 1.

58 AIN0 Event Mask 00h Enables/disables FAN 1 and/or F AN 2 alarm/hot-plug speed

in response to a fault on Channel 0.

59 AIN1 Event Mask 00h Enables/disables FAN 1 and/or F AN 2 alarm/hot-plug speed

in response to a fault on Channel 1. 60 Fan 1 Minimum/Alarm Speed FFh Contains the Minimum/ Alarm speeds for Fan 1. 61 Fan 2 Minimum/Alarm Speed FFh Contains the Minimum/ Alarm speeds for Fan 2. 68 Fan 1 Configuration 2Fh Configures hot-plug speed, PWM and tach frequency. 69 Fan 2 Configuration 2Fh Configures hot-plug speed, PWM and tach frequency. 70 Fan 1 Tach Value 00h Contains the measured value fr om the FAN 1 tachometer output. 71 Fan 2 Tach Value 00h Contains the measured value fr om the FAN 2 tachometer output. 78 Fan 1 Tach High Limit FFh Contains the high limit f or FAN 1 tachometer measurement. 79 Fan 2 Tach High Limit FFh Contains the high limit f or FAN 2 tachometer measurement.

80 Local Temp T

MIN ??h Defines the starting temperature for the fan whe n controlled by the local temperature channel, under Automatic F an Speed Control. 81 Remote 1 Temp T MIN ??h Defines the starting temperature for the fan whe n controlled by the Remote 1 temperature channel, under Automati c Fan Speed Control. (D1 Temp Sensor). 82 Remote 2 Temp T MIN ??h Defines the starting temperature for the fan whe n controlled by the Remote 2 temperature channel, under Automati c Fan Speed Control. (D2 Temp Sensor).

88 Local Temp T RANGE /T HYST 51h This register programs the control range for the local tempera-

ture control loop. It also defines the amount of te mperature hysteresis applied to the loop.

89 Remote 1 Temp T RANGE /T HYST 51h This register programs the control range for the Remote 1

temperature control loop. It also defines the amoun t of tem- perature hysteresis applied to the loop. ADM1029

Rev. 1 | Page 31 of 50 | www.onsemi.com ADM1029 Table X. Register Map (Continued) Address Name Default Value Description 8A Remote 2 Temp T RANGE /T HYST 51h This register programs the control range for the Remote 2 temperature control loop. It also defines the amoun t of tem- perature hysteresis applied to the loop. 90 Local Temp High Limit 50h (80 °C) High limit for Local measurement (internal sensor ). 91 Remote 1 Temp High Limit 64h (100 °C) High limit for Remote 1 measurement (D1 Sensor). 92 Remote 2 Temp High Limit 64h (100 °C) High limit for Remote 2 measurement (D2 Sensor). 98 Local Temp Low Limit 3Ch (60 °C) Low limit for Local Temp measurement (internal se nsor). 99 Remote 1 Temp Low Limit 46h (70 °C) Low limit for Remote 1 measurement (D1 Sensor). 9A Remote 2 Temp Low Limit 46h (70 °C) Low limit for Remote 2 measurement (D2 Sensor). A0 Local Temp Value 00h Measured value from local temp sensor. A1 Remote 1 Temp Value 00h Measured value from D1 Remo te Sensor. A2 Remote 2 Temp Value 00h Measured value from D2 Remo te Sensor. A8 AIN0 High Limit FFh High limit for measurement on a nalog Channel 0. A9 AIN1 High Limit FFh High limit for measurement on a nalog Channel 1. B0 AIN0 Low Limit 00h Low limit for measurement on ana log Channel 0. B1 AIN1 Low Limit 00h Low limit for measurement on ana log Channel 1. B8 AIN0 Measured Value 00h Measured value of analog Ch annel 0. B9 AIN1 Measured Value 00h Measured value of analog Ch annel 1. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up.

Rev. 1 | Page 32 of 50 | www.onsemi.com CONFIGURATION REGISTERS Register 01h — Config Register (Power-On Default 00 0? 000?) Bit Name R/W Description 0 Install = ? R/W This bit reflects Bit 1 of Register 0x03 (Fans Supported In System). 1 Global INT mask = 0 R/W Setting this bit to 1 will disable the INT output for all interrupt sources. 2 ARA Disable = 0 R/W Setting this bit to 1 will disab le the SMBus Alert Response Address feature. 3 Perform Free-Wheel R/W Setting this bit to 1 will in itiate the Fan Free-Wheeling Test. While this test Test = 0 is being performed normal monitoring of fan speeds, temperature and volt- ages will be temporarily halted. This bit will auto matically reset to 0 once the test is complete which will take about 10 seconds. 4 Start Monitoring = 0 R/W Set to 1 to start round rob in monitoring cycle of voltage temperature and fan speeds, fault detection, etc. While this bit is 0, all fans will run at Alarm Speed. This bit is set at power-up; otherwise, if a utomatic fan speed control is enabled by Pin 18. 5 Force CFAULT = 0 R/W Setting this bit to 1 forces CFAULT to be asserted (Low). 6 Force INT = 0 R/W Setting this bit to 1 forces INT to be asserted (Polarity depends on Bit 7). 7 INT Polarity = 0 R/W Polarity of INT when asserted. 1 means High and 0 means Low. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 05h – GPIO Present / AIN (Power-On Default 0????111) Bit Name R/W Description 0 GPIO 0 = 1 R/W Indicates that GPIO0 is being used. S et to 1 on power-up, but can be over- written by software. Setting this bit to 0 means AI N0 is being used. 1 GPIO 1 = 1 R/W Indicates that GPIO1 is being used. S et to 1 on power-up, but can be over- written by software. Setting this bit to 0 means AI N1 is being used. 2 GPIO 2 = 1 R/W Indicates that GPIO2 is being used. S et to 1 on power-up, but can be over- written by software. 3 GPIO 3 = ? R/W Indicates that GPIO3 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if T DM1 is connected. If so, this bit is set to 0, otherwise it is set to 1. The default setting can be overwritten by software. 4 GPIO 4 = ? R/W Indicates that GPIO4 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if T DM1 is connected. If so, this bit is set to 0, otherwise it is set to 1. The default setting can be overwritten by software. 5 GPIO 5 = ? R/W Indicates that GPIO5 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if T DM2 is connected. If so, this bit is set to 0, otherwise it is set to 1. The default setting can be overwritten by software. 6 GPIO 6 = ? R/W Indicates that GPIO6 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if T DM2 is connected. If so, this bit is set to 0, otherwise it is set to 1. The default setting can be overwritten by software. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. ADM1029

Rev. 1 | Page 33 of 50 | www.onsemi.com ADM1029 Register 07h – Set Fan x * Alarm Speed (Power-On Default 00h) Bit Name R/W Description 0 Fan 1 Alarm Speed = 0 R/W When set to 1, Fan 1 will run at Alarm Speed. 1 Fan 2 Alarm Speed = 0 R/W When set to 1, Fan 2 will run at Alarm Speed. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTES *“x” denotes the fan number. Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 08h – Set Fan x * Hot-Plug Speed (Power-On Default 00h) Bit Name R/W Description 0 Fan 1 Hot-Plug Speed = 0 R/W W hen set to 1, Fan 1 will run at Hot-Plug Speed. 1 Fan 2 Hot-Plug Speed = 0 R/W W hen set to 1, Fan 2 will run at Hot-Plug Speed. 2 0 R Unused. Will read back 0. 3 0 R Unused. Will read back 0. 4 0 R Unused. Will read back 0. 5 0 R Unused. Will read back 0. 6 0 R Unused. Will read back 0. 7 0 R Unused. Will read back 0. NOTES *“x” denotes the fan number. Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 09h – Set Fan x * Full Speed (Power-On Default 00h) Bit Name R/W Description 0 Fan 1 Full Speed = 0 R/W When set to 1 Fan 1 will ru n at Full Speed. 1 Fan 2 Full Speed = 0 R/W When set to 1 Fan 2 will ru n at Full Speed. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTES *“x” denotes the fan number. Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up.

Rev. 1 | Page 34 of 50 | www.onsemi.com STATUS REGISTERS Register 00h – Status Register (Power-On Default 00 h) Bit Name R/W Description 0 INT R This bit is set to 1 when the device is asserting INT low. This bit is the logical OR of several bits in other registers and is cleare d when these bits are cleared. 1 CFAULT_in R This bit is set to 1 when the device is receiving CFAULT low from another device. 2 CFAULT_out R This bit is set to 1 when the device is asserting CFAULT low. This bit is the logical OR of several bits in other registers a nd is cleared when these bits are cleared. 3 In Alarm_speed R This bit is set to 1 when either fa n is running at Alarm Speed. This bit is the logical OR of several bits in other registers and i s cleared when these bits are cleared. 4 In Hot-Plug Speed R This bit is set to 1 when either fan is running at Hot-Plug Speed. This bit is the logical OR of several bits in other registers a nd is cleared when these bits are cleared.

5 GPIO/AIN Event R This bit is a logical OR of Bits 1, 3, 6, and 7 in the GPIO Behavior Registers

at 28h to 2Eh while they are configured as inputs, and Bit 7 in the AIN Behavior Registers at 50h and 51h. It will be set w hen any of these bits are set and cleared when all of these bits are cleared.

6 Hot Plug/Fan Fault R This bit is a logical OR of Bit s 1, 3, 6, and 7 in the Fan Status Registers at

10h and 11h. It will be set when any of these bits are set and cleared when all of these bits are cleared.

7 Thermal Event R This bit is a logical OR of Bit 7 in the Temp Fault Action Registers at 40h,

41h, and 42h. It will be set when any of these bits are set and cleared when all of these bits are cleared. Register 02h – Fan Supported By Controller (Power-O n Default 03h) Bit Name R/W Description 0 Fan 1 = 1 R This bit set to 1 means the ADM1029 can support Fan 1. 1 Fan 2 = 1 R This bit set to 1 means the ADM1029 can support Fan 2. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. Register 03h – Fans Supported In System (Power-On D efault 0000 00?1) Bit Name R/W Description 0 Fan 1 = 1 R/W Indicates that Fan 1 is being used. Se t to 1 on Power-up, but can be over- written by software. 1 Fan 2 = ? R/W Indicates that Fan 2 is being used. Se t by Pin 18 (TMIN/INSTALL) on Power-up, but can be overwritten by software. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. ADM1029

Rev. 1 | Page 35 of 50 | www.onsemi.com ADM1029 Register 04h – GPIOs Supported By Controller (Power -On Default 7Fh) Bit Name R/W Description

0 GPIO 0 = 1 (Pin 19) R This bit set to 1 means the AD M1029 can support GPIO0, available on

Pin 19.

1 GPIO 1 = 1 (Pin 20) R This bit set to 1 means the AD M1029 can support GPIO1, available on

Pin 20.

2 GPIO 2 = 1 (Pin 11) R This bit set to 1 means the AD M1029 can support GPIO2, available on

Pin 11.

3 GPIO 3 = 1 (Pin 13) R This bit set to 1 means the AD M1029 can support GPIO3, available on

Pin 13.

4 GPIO 4 = 1 (Pin 14) R This bit set to 1 means the AD M1029 can support GPIO4, available on

Pin 14.

5 GPIO 5 = 1 (Pin 16) R This bit set to 1 means the AD M1029 can support GPIO5, available on

Pin 16.

6 GPIO 6 = 1 (Pin 17) R This bit set to 1 means the AD M1029 can support GPIO6, available on

Pin 17. 7 Reserved R Unused. Will read back 0. Register 06h – Temp Devices Installed (Power-On Def ault 0000 0??1) Bit Name R/W Description

0 Local Temp = 1 R This bit is permanently set to 1 si nce the local temperature sensor is

always available. 1 Remote 1 Temp = ? R This bit is set to 1 if the Remo te 1 temperature sensor (TDM1) is installed. (Automatically detected on power-up.) 2 Remote 2 Temp = ? R This bit is set to 1 if the Remo te 2 temperature sensor (TDM2) is installed. (Automatically detected on power-up.) 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up.

Rev. 1 | Page 36 of 50 | www.onsemi.com Register 10h, 11h – Fan x * Status (Power-On Default 0000 0?0?) Bit Name R/W Description 0 Missing = x R Reflects the state of Pins 4/21. Low m eans Fan x * is installed, High means it is missing. This bit will automatically re turn Low if a missing fan is replaced.

1 Missing _L = 0 R/W This bit is edge-triggered and la tches a Fan x * missing event on removal

of Fan x. This bit is cleared by writing a 0 to it. 2 Fault_ = x R Inverse of Pin 2/23. Low on pin means F an x * has a fault (Pins 2/23 Low), High on pin means it is OK. This bit will aut omatically return Low if Pins 2/23 goes high. 3 Fault_L_ = 0 R/W This bit is edge-triggered and latc hes a Fan x * fault event on Pins 2/23. This bit is cleared by writing a 0 to it. If the PRESENT pin for a fan input is high (fan not installed) this bit will be cleared automatically.

4 Sleep = 0 R/W When this bit is set, Fan x * will be stopped and no Fan x * faults will be

monitored. If Bit 4 in Fan x * Fault Action Register is set, Fan x * will go to Alarm Speed if an overtemperature event is detec ted as per settings in the Temp Fault Action Registers.

5 Hot Plug Priority R/W This bit indicates whether Fan x runs at Hot-Plug Speed (bit set to 1) or

Alarm Speed (bit set to 0) if both modes are trigge red. 6 Tach_Fault_L R/W Latches a Fan x Tach Fault. This bi t is cleared by writing a 0 to it. If the PRESENT pin for a fan input is high (fan not installed), t his bit will be cleared automatically.

7 Hot_Plug_L R/W This bit is edge-triggered and latche s a Fan x Hot-plug event which is the

insertion of Fan x. (Note difference to Bit 1.) Thi s bit is cleared by writ- ing a 0 to it. If a fan is Hot-Plug installed, it w ill run at Normal Speed. NOTES *“x” denotes the fan number. Register 10h is for Fan 1 and Register 11h is for Fan 2. Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. ADM1029

Rev. 1 | Page 37 of 50 | www.onsemi.com ADM1029 TEMPERATURE REGISTERS Register 06h – Temp Devices Installed (Power-On Def ault 0000 0??1) Bit Name R/W Description

0 Local Temp = 1 R This bit is permanently set to 1 si nce the local temperature sensor is always

available. 1 Remote 1 Temp = ? R This bit is set to 1 if the Remo te 1 temperature sensor (TDM1) is installed. (Automatically detected on power-up.) 2 Remote 2 Temp = ? R This bit is set to 1 if the Remo te 2 temperature sensor (TDM2) is installed. (Automatically detected on power-up.) 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 30h, 31h, 32h – Temp x * Offset Registers (Power-On Default 00h) Bit Name R/W Description <7:0> Offset R/W This register contains an offset valu e that is automatically added to the tem- perature value to reduce the effects of systemic of fset errors. *“x” denotes the number of the temperature channel. Register 30h is for Local temperature channel, 31h is for Remote 1 Temp (D1), 32h is for Remote 2 Temp (D2). Register 40h, 41h, 42h – Temp x * Fault Action (Power-On Default 08h) Bit Name R/W Description

0 Assert CFAULT on R/W When this bit is set, CFAULT will be asserted when the Temp x * tempera-

OT = 0 ture exceeds the Temp x * Temperature High Limit, not otherwise.

1 Alarm speed on OT = 0 R/W When this bit is set, the fans(s) will go to alarm speed when the Temp x *

temperature exceeds the Temp x * Temperature High limit, not otherwise.

2 INT on OT = 0 R/W When this bit is set, INT will be asserted when the Temp x * temperature

exceeds the Temp x * Temperature High Limit, not otherwise.

3 Alarm below low = 0 R/W This bit indicates whether a n alarm ( INT , CFAULT , or Alarm Speed) is

asserted when temperature goes above or below the L ow Limit. 1 = above, 0 = below. This bit is set to 1 at power-up if auto matic fan speed control is enabled by Pin 18, cleared otherwise.

4 Assert CFAULT on R/W When this bit is set, CFAULT will be asserted when the Temp x * temperature

UT = 0 crosses the Temp x * Temperature Low Limit, not otherwise. Bit 3 decide s whether CFAULT is asserted for going above or below the Low Limit. This bit is set to 1 if Automatic Fan Speed Control is enabled on power-up.

5 Alarm speed on UT = 0 R/W When this bit is set, the fans(s) will go to alarm speed when the Temp x *

temperature crosses the Temp x * Temperature Low Limit, not otherwise. Bit 3 decides whether Alarm Speed is asserted for going above or below the Low Limit.

6 INT on UT = 0 R/W When this bit is set, INT will be asserted when the Temp x * temperature

crosses the Temp x * Temperature Low Limit, not otherwise. Bit 3 decide s whether INT is asserted for going above or below the Low Limit . 7 Latch Temp Fault = 0 R/W This bit latches a temperat ure out-of-limit event (i.e., when the temperature goes above the high limit or crosses the low limit) on the Temp x * channel. This bit is cleared by writing a 0 to it. *“x” denotes the number of the temperature channel. R egister 40h is for the Local temperature channel, 4 1h is for Remote 1 Temp (D1), 42h is for Remote 2 Temp (D2).

Rev. 1 | Page 38 of 50 | www.onsemi.com Register 48h, 49h, 4Ah – Temp x * Cooling Action (Power-On Default 00h) Bit Name R/W Description

0 Fan 1 = 0 R/W If a Temp x * out-of-limit event is generated such that fans should be driven at

Alarm Speed, Fan 1 will be set to this speed when this bit is set. If no Temp x * out-of-limit event is present, Fan 1 will be set to the speed determined by the automatic fan speed control circuit as a result of temperature measurements on the Temp x * channel when this bit is set. If this bit is not set, Temp x * tem- perature measurements will have no effect on the speed of Fan 1.

1 Fan 2 = 0 R/W If a Temp x * out-of-limit event is generated such that fans sho uld be driven

at Alarm Speed, Fan 2 will be set to this speed when this bit is set. If no Temp x* out-of-limit event is present, Fan 2 will be set t o the speed determined by the automatic fan speed control circuit as a result of temperature measure- ments on the Temp x * channel when this bit is set. If this bit is not s et, Temp x temperature measurements have no effect on t he speed of Fan 2. While in theory it is possible, through setting of Bits 0 and 1 in registers 48h to 4Ah, to have any temperature channel controlling any fan, in practice this is not feasible. A subset of possibilities only are supported as follows: Case 1: TDM1 controlling Fan 1 (Bit 0 in 49h set and/ or TDM2 controlling Fan 2 Bit 1 in 4Ah set, only) Case 2: Local controlling Fan 1 and/or Fan 2 (Bits 0, 1 in 48h only set) Case 3: TDM1 controlling Fan 1 and/or Fan 2 (Bits 0, 1 in 49h only set) Case 4: TDM2 controlling Fan 1 and/or Fan 2 (Bits 0, 1 in 4Ah only set) Case 5: Fan 1 and/or Fan 2 set to max speed (Bits 0, 1 in 48h, 49h, (Default) determined by temperature 4Ah all set) measurements on all three channels. Other: If Bits 0,1 in registers 48h, 49h, 4Ah are set inconsistent with these cases, fans will run at the speeds determined by the normal speed registers. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. *“x” denotes the number of the temperature channel. R egister 48h is for the Local temperature channel. 4 9h is for Remote 1 Temp (D1), 4Ah is for Remote 2 Temp (D2). ADM1029

Rev. 1 | Page 39 of 50 | www.onsemi.com ADM1029 Register 80h, 81h, 82h – Temp x * T MIN (Power-On Default 001??000) Bit Name R/W Description <7:0> Temp x * T MIN R/W This register contains the minimum temperature v alue for automatic fan speed control based on the Temp x * temperature. On power-up Pin 18 is sampled by the ADC to determine the default value for Temp x * T MIN . If Pin 18 is strapped to GND or V CC , this register defaults to 32 °C, but Automatic Fan Speed Control is disabled. There are eight strappab le options on Pin 18. These options are used to set Temp x * T MIN and the Install bit in the Config Register (Reg 01h, Bit 0). The options are as follo ws: ADC MSBs R1 R2 Install Temp x * T MIN 111 0 ∞ 1 Disabled 101 18 k Ω 82 k Ω 1 48 °C 110 22 k Ω 47 k Ω 1 40 °C 100 12 k Ω 15 k Ω 1 32 °C 011 15 k Ω 12 k Ω 0 32 °C 010 47 k Ω 22 k Ω 0 40 °C 001 82 k Ω 18 k Ω 0 48 °C 000 ∞ 0 0 Disabled *“x” denotes the number of the temperature channel. R egister 80h is for the Local temperature channel, 8 1h is for Remote 1 Temp (D1), 82h is for Remote 2 Temp (D2). Register 88h, 89h, 8Ah Temp x * T RANGE /T HYST (Power-On Default 51h) Bit Name R/W Description <3:0> Temp x * T RANGE R/W This nibble contains the temperature range over which automatic fan speed control operates based on the Temp x * measured temperature. Only a limited number of temperature ranges are supported as follo ws: Bits <3:0> T RANGE 0000 5 °C 0001 10 °C 0010 20 °C 0011 40 °C 0100 80 °C <7:4> Temp x * T HYST R/W This nibble allows programmability of the Hyster esis level around the temperature at which the fan being controlled by Temp x * will switch on in automatic fan speed control mode. Values from 0 °C to 15 °C are possible. If a value other than 0°C is programmed as a Hysteresis value, the fan will switch on when Temp x * goes above T MIN , but will remain on until Temp x * falls below T MIN –T HYST . Between T MIN –T HYST and T MIN the fan will run at the programmed minimum pulsewidth in the Fan x * Speed 1 register. *“x” denotes the number of the temperature channel. Register 88h is for the Local temperature channel , 89h is for Remote 1 Temp (D1), 8Ah is for Remote 2 T emp (D2).

Rev. 1 | Page 40 of 50 | www.onsemi.com Register 90h, 91h, 92h – Temp x * High Limit (Power-On Default 80 /H11543C for Local Sensor, 100 /H11543C for Remote Sensors) Bit Name R/W Description <7:0> Temp x * High Limit R/W This register contains the high limit value for the Temp x * measurement. *“x” denotes the number of the temperature channel. R egister 90h is for the Local temperature channel. 9 1h is for Remote 1 Temp (D1), 92h is for Remote 2 Temp (D2). Register 98h, 99h, 9Ah – Temp x * Low Limit (Power-On Default 60 /H11543C for Local Sensor, 70 /H11543C for Remote Sensors) Bit Name R/W Description <7:0> Temp x * Low Limit R/W This register contains the low limit v alue for the Temp x * measurement. *“x” denotes the number of the temperature channel. R egister 98h is for the Local temperature channel. 9 9h is for Remote 1 Temp (D1), 9Ah is for Remote 2 Temp (D2). Register A0h, A1h, A2h – Temp x * Measured Value (Power-On Default 00h) Bit Name R/W Description <7:0> Temp x * Value R This register contains the actual Temp x * measured value. *“x” denotes the number of the temperature channel. R egister A0h is for the Local temperature channel. A 1h is for Remote 1 Temp (D1), A2h is for Remote 2 Temp (D2). ADM1029

Rev. 1 | Page 41 of 50 | www.onsemi.com ADM1029 FAN REGISTERS Register 02h – Fan Supported By Controller (Power-O n Default 03h) Bit Name R/W Description 0 Fan 1 = 1 R This bit set to 1 means the ADM1029 can support Fan 1. 1 Fan 2 = 1 R This bit set to 1 means the ADM1029 can support Fan 2. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. Register 03h – Fans Supported In System (Power-On D efault 0000 00?1) Bit Name R/W Description 0 Fan 1 = 1 R/W Indicates that Fan 1 is being used. Se t to 1 on power-up, but can be overwrit- ten by software. 1 Fan 2 = ? R/W Indicates that Fan 2 is being used. Se t by Pin 18 (TMIN/INSTALL) on power-up, but can be overwritten by software. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 07h – Set Fan x Alarm Speed (Power-On Defa ult 00h) Bit Name R/W Description 0 Fan 1 Alarm Speed = 0 R/W When set to 1, Fan 1 will run at Alarm Speed. 1 Fan 2 Alarm Speed = 0 R/W When set to 1, Fan 2 will run at Alarm Speed. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. Register 08h – Set Fan x Hot-Plug Speed (Power-On D efault 00h) Bit Name R/W Description 0 Fan 1 Hot-Plug Speed = 0 R/W W hen set to 1, Fan 1 will run at Hot-Plug Speed. 1 Fan 2 Hot-Plug Speed = 0 R/W W hen set to 1, Fan 2 will run at Hot-Plug Speed. 2 0 R Unused. Will read back 0. 3 0 R Unused. Will read back 0. 4 0 R Unused. Will read back 0. 5 0 R Unused. Will read back 0. 6 0 R Unused. Will read back 0. 7 0 R Unused. Will read back 0.

Rev. 1 | Page 42 of 50 | www.onsemi.com Register 09h – Set Fan x Full Speed (Power-On Defau lt 00h) Bit Name R/W Description 0 Fan 1 Full Speed = 0 R/W When set to 1 Fan 1 will ru n at Full Speed. 1 Fan 2 Full Speed = 0 R/W When set to 1 Fan 2 will ru n at Full Speed. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. Register 0Ch – Fan Spin-Up Register (Power-On Defau lt 03h) Bit Name R/W Description <7:4> Reserved R Unused 3 Spin-up Disable R/W When this bit is set to 1, fan s pin-up to full speed will be disabled. <2:0> Fan Spin-up Time R/W These bits select the spin- up time for the fans 000 = 16 seconds 001 = 8 seconds 010 = 4 seconds 011 = 2 seconds (default) 100 = 1 second 101 = 0.25 seconds 110 = 1/16 second 111 = 1/64 second Register 10h, 11h – Fan x * Status (Power-On Default 0000 0?0?) Bit Name R/W Description 0 Missing = x R Reflects the state of Pins 4/21. Low m eans Fan x * is installed, High means it is missing. This bit will automatically return Low if a missing fan is replaced.

1 Missing _L = 0 R/W This bit is edge-triggered and la tches a Fan x * missing event on removal of

Fan x *. This bit is cleared by writing a 0 to it. 2 Fault_ = x R Inverse of Pin 2/23. Low on pin means F an x * has a fault (Pins 2/23 Low), High on pin means it is OK. This bit will automatic ally return Low if Pin 2/23 goes high. 3 Fault_L_ = 0 R/W This bit is edge-triggered and latc hes a Fan x * fault event on Pin 2/23. This bit is cleared by writing a 0 to it. If the PRESENT pin for a fan input is high (fan not installed) this bit will be cleared automatical ly. monitored. If Bit 4 in Fan x * Fault Action Register is set then Fan x * will go to Alarm Speed if an overtemperature event is detec ted as per settings in the Temp Fault Action Registers.

5 Hot Plug Priority R/W This bit indicates whether Fan x * runs at Hot-Plug Speed (bit set to 1) or

Alarm Speed (bit set to 0) if both modes are trigge red. 6 Tach_Fault_L R/W Latches a Fan x * Tach fault. This bit is cleared by writing a 0 to it. If the PRESENT pin for a fan input is high (fan not instal led) this bit will be cleared automatically.

7 Hot_Plug_L R/W This bit is edge-triggered and latche s a Fan x * Hot-Plug event which is the

insertion of Fan x *. (Note difference to Bit 1) This bit is cleared by writing a 0 to it. If a fan is Hot-Plug installed, it will run at Normal Speed. NOTES *“x” denotes the fan number. Register 10h is for Fan 1 and Register 11h is for Fan 2. Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. ADM1029

Rev. 1 | Page 43 of 50 | www.onsemi.com ADM1029 Register 18h, 19h – Fan x * Fault Action (Power-On Default BFh) Bit Name R/W Description

0 Assert CFAULT on R/W If this bit is set, CFAULT will be asserted when there is a fault (Tach or

Fault = 1 Pins 2/23) on Fan x *. 1 Assert INT on Fault = 1 R/W If this bit is set, INT will be asserted when there is a fault (Tach or Pi ns 2 23) on Fan x *.

2 Assert CFAULT on R/W If this bit is set, CFAULT will be asserted when there is a hot unplug event

Hot Unplug = 1 on Fan x *.

3 Assert INT on R/W If this bit is set, INT will be asserted when there is a hot unplug event

Hot Unplug = 1 on Fan x *. 4 Thermal Override in R/W If Bit 4 in Fan x * Status Register is set then Fan x * will go to Alarm Speed if Sleep = 1 an overtemperature event is detected as pe r settings in Temp x * Fault Action Registers, while this bit is set. 5 Drive Fault_ on R/W If Bit 3 or Bit 6 of Reg 10 is s et, drive Pins 2, 23 low if a fault is generated. Fault_L = 1

6 Hot-Plug Speed on R/W When this bit is set, Fan x * will go to Hot-Plug Speed when CFAULT is

CFAULT in = 0 pulled low externally.

7 Alarm on CFAULT = 1 R/W When this bit is set, Fan x * will go to Alarm Speed when CFAULT is pulled

low externally. *“x” denotes the fan number. Register 18h is for Fan 1 and Register 19h is for Fan 2. Register 20h, 21h – Fan x * Event Mask (Power-On Default FFh) Bit Name R/W Description

0 Fan 1 = 1 R/W If a fault (Tach or Pins 2/23) is dete cted on Fan x *, Fan 1 will be driven to

Alarm Speed when this bit is set.

1 Fan 2 = 1 R/W If a fault (Tach or Pins 2/23) is dete cted on Fan x *, Fan 2 will be driven to

Alarm Speed when this bit is set. 2 Reserved R Unused. Will read back 1. 3 Reserved R Unused. Will read back 1. 4 Reserved R Unused. Will read back 1. 5 Reserved R Unused. Will read back 1. 6 Reserved R Unused. Will read back 1. 7 Reserved R Unused. Will read back 1. *“x” denotes the fan number. Register 20h is for Fan 1 and Register 21h is for Fan 2. Register 60h, 61h – Fan x * Minimum/Alarm Speed (Power-On Default FFh) Bit Name R/W Description 3–0 Fan x Minimum Speed R/W This nibble contains the N ormal speed value for Fan x *. When in automatic fan this nibble will contain the minimum speed at w hich Fan x * will run. The power-up default for the Min Speed should be 5hex w hich corresponds to 33% PWM duty cycle. 7–4 Fan x Alarm Speed R/W This nibble contains the Ala rm speed value for Fan x *. *“x” denotes the fan number. Register 60h is for FAN 1 and 61h is for FAN 2.

Rev. 1 | Page 44 of 50 | www.onsemi.com Register 68h, 69h – Fan x * Configuration (Power-On Default 2Fh) Bit Name R/W Description <3:0> Fan x * Hot-Plug Speed R/W This nibble contains the Hot-Plug speed value for Fan x *. This is the speed the other fan(s) runs at if Fan x * is Hot-Plug removed. If a fan is Hot-Plug installed, it will run at Normal Speed. <5:4> PWM Frequency R/W These bits allow programmabili ty of the Nominal PWM Frequency for Fan x *. The following options are supported: Bits 5–4 PWM Freq 00 15.625 Hz 01 62.5 Hz 10 250 Hz – Default 11 1000 Hz <7:6> Oscillator Frequency R/W These bits contain the oscillator frequency for the Fan x * tach measurement. If set to 00, tach measurement is disabled for Fan x *. Bit 7 Bit 6 Oscillator Frequency (Hz) 0 0 Measurement disabled 0 1 470 1 0 940 1 1 1880 *“x” denotes the fan number. Register 68h is for FAN 1 and 69h is for FAN 2. Register 70h, 71h – Fan x * Tach Value (Power-On Default 00h) Bit Name R/W Description <7:0> Fan x * Tach Value R This register contains the value of the Fan x * tachometer measurement. *“x” denotes the fan number. Register 70h is for FAN 1 and 71h is for FAN 2. Register 78h, 79h – Fan x * Tach High Limit (Power-On Default FFh) Bit Name R/W Description <7:0> Fan x * Tach High Limit R/W This register contains the limit value for the Fan x * tachometer measure- ment. Since the tachometer circuit counts between t ach pulses, a slow fan will result in a larger measured value, so exceeding the limit is the way to detect a slow or stopped fan. *“x” denotes the fan number. Register 78h is for FAN 1 and 79h is for FAN 2. ADM1029

Rev. 1 | Page 45 of 50 | www.onsemi.com ADM1029 GPIO REGISTERS Register 04h–GPIOs Supported by Controller (Power-O n Default 7Fh) Bit Name R/W Description 0 GPIO 0 = 1 (Pin 19) R This bit set to 1 means the AD M1029 can support GPIO0, available on Pin 19. 1 GPIO 1 = 1 (Pin 20) R This bit set to 1 means the AD M1029 can support GPIO1, available on Pin 20. 2 GPIO 2 = 1 (Pin 11) R This bit set to 1 means the AD M1029 can support GPIO2, available on Pin 11. 3 GPIO 3 = 1 (Pin 13) R This bit set to 1 means the AD M1029 can support GPIO3, available on Pin 13. 4 GPIO 4 = 1 (Pin 14) R This bit set to 1 means the AD M1029 can support GPIO4, available on Pin 14. 5 GPIO 5 = 1 (Pin 16) R This bit set to 1 means the AD M1029 can support GPIO5, available on Pin 16. 6 GPIO 6 = 1 (Pin 17) R This bit set to 1 means the AD M1029 can support GPIO6, available on Pin 17. 7 Reserved R Unused. Will read back 0. Register 05h–GPIO Present/AIN (Power-On Default 0?? ??111) Bit Name R/W Description 0 GPIO 0 = 1 R/W Indicates that GPIO0 is being used. S et to 1 on power-up, but can be over- written by software. Setting this bit to 0 means AI N0 is being used. 1 GPIO 1 = 1 R/W Indicates that GPIO1 is being used. S et to 1 on power-up, but can be over- written by software. Setting this bit to 0 means AI N1 is being used. 2 GPIO 2 = 1 R/W Indicates that GPIO2 is being used. S et to 1 on power-up, but can be over- written by software. 3 GPIO 3 = ? R/W Indicates that GPIO3 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if T DM1 is connected. If so then this bit is set to 0, otherwise it is set t o 1. The default setting can be overwritten by software. 4 GPIO 4 = ? R/W Indicates that GPIO4 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if T DM1 is connected. If so then this bit is set to 0, otherwise it is set t o 1. The default setting can be overwritten by software. 5 GPIO 5 = ? R/W Indicates that GPIO5 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if T DM2 is connected. If so then this bit is set to 0, otherwise it is set t o 1. The default setting can be overwritten by software. 6 GPIO 6 = ? R/W Indicates that GPIO6 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if T DM2 is connected. If so then it is set to 1. The default setting can be overwritten by software. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up.

Rev. 1 | Page 46 of 50 | www.onsemi.com Register 28h, 29h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh – GPIOx * Behavior (Power-On Default 00h) Bit Name R/W Description 0 Direction = 0 R/W This bit indicates the direction f or GPIOx * pin. When set to 1 GPIOx * will function as an input, when 0 GPIOx * will function as an output. 1 Polarity = 0 R/W This bit indicates the polarity of the GPIOx * pin. When set to 1 GPIOx * will be active high, when 0 GPIOx * will be active low.

2 Bit 2 = 0 R/W If GPIOx * is configured as an input, CFAULT will be asserted if GPIOx *

pin is asserted while this bit is set. If GPIO2 is configured as an output, GPIO2 will be asserted if a temperature High limit is exceeded while this bit is set. If automatic fan speed control is enabled, this bit wi ll be set by default. This can be used as a SHUTDOWN signal for a catastrophic ove rtemperature event.

3 Bit 3 = 0 R/W If GPIOx * is configured as an input, INT will be asserted if GPIOx * pin is

asserted while this bit is set. If GPIOx * is configured as an output, GPIOx * will be asserted if a temperature Low limit is exceeded while this bit is set.

4 Bit 4 = 0 R/W If GPIOx * is configured as an input, Fans will go to Alarm S peed if GPIOx *

pin is asserted while this bit is set. If GPIOx * is configured as an output, GPIOx * will be asserted if a Fan Tach limit is exceeded w hile this bit is set.

5 Bit 5 = 0 R/W If GPIOx * is configured as an input, Fans will go to Hot-Plu g Speed if

GPIOx * pin is asserted while this bit is set. If GPIOx * is configured as an output, GPIOx * will be asserted if a Fan Fault (Pins 2/23) is det ected while this bit is set. 6 Bit 6 = 0 R If GPIOx * is configured as an input, this bit will reflect state of GPIOx * pin. R/W If GPIOx * is configured as an output, GPIOx will be asserted if an AIN high limit is exceeded while this bit is set.

7 Bit 7 = 0 R/W If GPIOx * is configured as an input, this bit will latch a G PIOx * assertion

event. This bit is cleared by writing a 0 to it. If GPIOx * is configured as an output, GPIOx * will be asserted if an AIN Low limit is exceeded w hile this bit is set. *“x” denotes the number of the GPIO pin. Register 28 h controls GPIO0, 29h controls GPIO1, etc. Register 38h, 39h, 3Ah, 3Bh, 3Ch, 3Dh, 3Eh – GPIOx * Event Mask (Power-On Default 00h) Bit Name R/W Description

0 Fan 1 = 0 R/W If GPIOx * is asserted such that fans should be driven at Ala rm or Hot-Plug

Speed, Fan 1 will be set to this speed when this bi t is set.

1 Fan 2 = 0 R/W If GPIOx * is asserted such that fans should be driven at Ala rm or Hot-Plug

Speed, Fan 2 will be set to this speed when this bi t is set. 2 Reserved R Unused. Will read back 0. 3 Reserved R Unused. Will read back 0. 4 Reserved R Unused. Will read back 0. 5 Reserved R Unused. Will read back 0. 6 Reserved R Unused. Will read back 0. 7 Reserved R Unused. Will read back 0. *“x” denotes the number of the GPIO pin. Register 38 h is for GPIO0, 39h is for GPIO1 etc. ADM1029

Rev. 1 | Page 47 of 50 | www.onsemi.com ADM1029 AIN REGISTERS Register 05h – GPIO Present/AIN (Power-On Default 0 ????111) Bit Name R/W Description 0 GPIO 0 = 1 R/W Indicates that GPIO0 is being used. S et to 1 on power-up, but can be over- written by software. Setting this bit to 0 means AI N0 is being used. 1 GPIO 1 = 1 R/W Indicates that GPIO1 is being used. S et to 1 on Power-up, but can be over- written by software. Setting this bit to 0 means AI N1 is being used. 2 GPIO 2 = 1 R/W Indicates that GPIO2 is being used. S et to 1 on power-up, but can be over- written by software. 3 GPIO 3 = ? R/W Indicates that GPIO3 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if TDM1 is connected. If so, this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit- ten by software. 4 GPIO 4 = ? R/W Indicates that GPIO4 is being used. S etting this bit to 0 means TDM1 is being used. The ADM1029 can detect on power-up if TDM1 is connected. If so, this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit- ten by software. 5 GPIO 5 = ? R/W Indicates that GPIO5 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if TDM2 is connected. If so, this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit- ten by software. 6 GPIO 6 = ? R/W Indicates that GPIO6 is being used. S etting this bit to 0 means TDM2 is being used. The ADM1029 can detect on power-up if TDM2 is connected. If so, this bit is set to 0; otherwise it is set to 1. The default setting can be overwrit- ten by software. 7 Reserved R Unused. Will read back 0. NOTE Question marks on this and following pages indicate bit settings that depend on the state of certain p ins on power-up. Register 50h, 51h – AINx * Behavior (Power-On Default 00h) Bit Name R/W Description

0 Assert CFAULT on R/W When this bit is set, CFAULT is asserted when AINx * exceeds the AINx *

HI_LIM = 0 high limit.

1 Alarm speed on R/W When this bit is set, the fans go to alarm speed wh en AINx * exceeds the

HI_LIM = 0 AINx * high limit. 2 INT on HI_LIM = 0 R/W When this bit is set, INT is asserted when AINx * exceeds the AINx * high limit.

3 Alarm below low = 0 R/W This bit indicates whether an alarm ( INT , CFAULT or Alarm Speed) is

asserted when AINx * goes above or below the Low Limit. 1 = above. 0 = below.

4 Assert CFAULT on R/W When this bit is set, CFAULT is asserted when AINx * crosses the AINx *

LO_LIM = 0 low limit. Bit 3 decides whether CFAULT is asserted for going above or below the Low Limit.

5 Alarm speed on R/W When this bit is set, the fans go to alarm speed when AINx * crosses the AINx *

LO_LIM = 0 low limit. Bit 3 decides whether Alarm Sp eed is asserted for going above or below the Low Limit. 6 INT on LO_LIM = 0 R/W When this bit is set, INT is asserted when AINx * crosses the AINx * low limit. Bit 3 decides whether INT is asserted for going above or below the Low Limit . 7 Latch AIN Fault = 0 R/W This bit latches an out-of-l imit event (i.e., when AINx * goes above the high limit or crosses the low limit) on the AINx * channel. This bit is cleared by writing a 0 to it. *“x” denotes the number of the AIN channel. Register 50h controls AIN0 and 51h controls AIN1.

Rev. 1 | Page 48 of 50 | www.onsemi.com Register 58h, 59h – AINx * Event Mask (Power-On Default 00h) Bit Name R/W Description

0 Fan 1 = 0 R/W If an AINx * out-of-limit event is generated such that fans sho uld be driven at

Alarm Speed, Fan 1 will be set to this speed when t his bit is set.

1 Fan 2 = 0 R/W If an AINx * out-of-limit event is generated such that fans sho uld be driven at

Alarm Speed, Fan 2 will be set to this speed when t his bit is set.

2 Reserved R/W Undefined

3 Reserved R/W Undefined

4 Reserved R/W Undefined

5 Reserved R/W Undefined

6 Reserved R/W Undefined

7 Reserved R/W Undefined

*“x” denotes the number of the AIN channel. Register 58h is for AIN0 and 59h is for AIN1. Register A8h, A9h – AINx * High Limit (Power-On Default FFh) Bit Name R/W Description <7:0> AINx * High Limit R/W This register contains the high limit value for the AINx * analog input channel. *“x” denotes the number of the AIN channel. Register A8h is for AIN0 and A9h is for AIN1. Register B0h, B1h – AINx * Low Limit (Power-On Default 00h) Bit Name R/W Description <7:0> AINx * Low Limit R/W This register contains the low limit v alue for the AINx * analog input channel. *“x” denotes the number of the AIN channel. Register B0h is for AIN0 and B1h is for AIN1. Register B8h, B9h – AINx * Measured Value (Power-On Default 00h) Bit Name R/W Description <7:0> AINx * value R This register contains the measured value of the AINx * analog input channel. *“x” denotes the number of the AIN channel. Register B8h is for AIN0 and B9h is for AIN1. ADM1029

Rev. 1 | Page 49 of 50 | www.onsemi.com ADM1029 MISCELLANEOUS REGISTERS Register 0Bh – S/W RESET (Power-On Default 00h) Bit Name R/W Description <7:0> S/W Reset R/W Writing A6 hex to this register lo cation causes a software reset identical to a power-on reset. This register is self-clearing so r eading from it after the soft- ware reset has completed will result in 00 hex bein g read. Register 0Dh – Manufacturer’s ID (Power-On Default 41h) Bit Name R/W Description <7:0> Manufacturer’s ID Code R This register contains the manufacturer’s ID code for the device. Register 0Eh – Revision (Power-On Default 00h) Bit Name R/W Description <3:0> Minor Revision Code R This nibble contains the manuf acturer’s code for minor revisions to the device. <7:4> Major Revision Code R This nibble contains the m anufacturer’s code for major revisions to the devic e which would likely require a S/W revision. Register 0Fh – Manufacturer’s Test Register (Power- On Default 00h) Bit Name R/W Description <7:0> Manufacturer’s Test R/W This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. Model Temperature Range Package Description Package Option ADM1029ARQZ 1 0°C to 100°C Shrink Small Outline Package (QSOP) RQ-24 ADM1029ARQZ-R7 1 0°C to 100°C Shrink Small Outline Package (QSOP) RQ-24 1Z = Pb-Free part ORDERING GUIDE

SCALE 2:1 E M0.25 C A C DETAIL A DETAIL A h x 45 /C0095 DIM MAX MIN MILLIMETERS A 1.35 1.75 b 0.20 0.30 L 0.40 1.27 e 0.635 BSC h 0.22 0.50 C 0.19 0.25 A1 0.10 0.25 M 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. /C0095 /C0095 b L 6.40 24X 0.42 24X 1.12 0.635 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT 1 12 D D 24X SEATING PLANE 0.10 C A A-B D 0.20 C e 1 12 24 13 24X C M xxx = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week xxxxxxxxx AWLYWW GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. Pb /g239Free indicator, “G”, may or not be present. D 8.65 BSC E 6.00 BSC E1 3.90 BSC L2 0.25 BSC D

0.25 C D

B

0.20 C D

0.10 C H

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