ADM1028

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM1028 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Remote Thermal Diode Monitor with Linear Fan Control FUNCTIONAL BLOCK DIAGRAM 2.5V BANDGAP REFERENCE ANALOG SIGNAL CONDITIONING ALERT STATUS REGISTER ADC ADM1028 R_OFF R_RST SDA SCL RST 10k/H9024 VCC3AUX FAN_SPD/NTEST_IN INT FAN_OFF SERIAL BUS INTERFACE LIMIT COMPARATORS INTERRUPT STATUS REGISTERS MASK GATING CONFIGURATION REGISTER INT MASK REGISTER ANALOG O/P REGISTER, COUNTER AND 8-BIT DAC VALUE AND LIMIT REGISTERS VCC3AUX POWER-ON RESET FAN_SPD SHUTOFF AND R_OFF RESET 10k/H9024 VCC3AUX THERMA/NTEST_OUT AUXRST RESET THERMB GPI GND ADDRESS POINTER REGISTER REMOTE FUNCTION REGISTER

FEATURES

On-Chip Temperature Sensor External Temperature Measurement with Remote Diode Interrupt and Over-Temperature Outputs Fault-Tolerant Fan Control with Auto Hardware Trip Point Remote Reset and Power-Down Functions LDCM Support System Management Bus (SMBus) Communications Standby Mode to Minimize Power Consumption Limit Comparison of all Monitored Values DAC Output for Linear Fan Speed Control Ramp Rate Register for Control of Rate of Change of Fan Speed, Reduction of Fan Acoustics

APPLICATIONS

Network Servers and Personal Computers Microprocessor-Based Office Equipment Test Equipment and Measuring Instruments GENERAL DESCRIPTION The ADM1028 is a low-cost temperature monitor and fan controller for microprocessor-based systems. The temperature of a remote sensor diode may be measured, allowing monitoring of processor temperature in single processor systems. An on-chip temperature sensor monitors ambient system temperature. Measured values can be read out via the System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. The ADM1028 also contains a DAC for fan speed control. An automatic hardware temperature trip point is provided and the fan will be driven to full speed if it is exceeded. A Ramp Rate Register is provided to control the rate with which fan speed is increased or decreased. This is to eliminate sudden changes in fan speed, thereby reducing fan acoustics and prolonging the fan’s life. Finally, the chip has remote reset and power-down functionality, allowing it to be remotely shut down via the SMBus. The ADM1028’s 3.0 V to 5.5 V supply voltage range, low supply current, and SMBus make it ideal for a wide range of applications. These include hardware monitoring applications in PCs, electronic test equipment, and office electronics.

REV. A–2– ADM1028–SPECIFICATIONS1, 2 (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions POWER SUPPLY Supply Voltage, VCC 3.0 3.30 5.5 V Supply Current, ICC 2 3.2 mA Interface Inactive, ADC Active TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ±3 °C ±2 °C6 0 °C ≤ TA ≤ 100°C Resolution 1 °C External Diode Sensor Accuracy ±5 °C ±3 °C6 0 °C ≤ TA ≤ 100°C Resolution 1 °C Remote Sensor Source Current 120 µA High Level (D+ = D– + 0.65 V) 7 µA Low Level (D+ = D– + 0.65 V) ANALOG OUTPUT Output Voltage Range 0 2.5 V Total Unadjusted Error, TUE ±3% I L = 2 mA Full-Scale Error ±1 ±3% Zero Error ±2 LSB No Load Differential Nonlinearity, DNL ±1 LSB Monotonic by Design Integral Nonlinearity ±1 LSB Output Source Current 2 mA Output Sink Current 1 mA THERMA OUTPUT THERMA Pull-Up Resistance 9 12 14 k Ω DIGITAL OUTPUT THERMA/NTEST_OUT, R_OFF Output High Voltage, V OH 2.4 V I OUT = 3.0 mA Output Low Voltage, V OL 0.4 V OPEN-DRAIN DIGITAL OUTPUTS (INT, THERMB, FAN_OFF, R_RST) Output Low Voltage, V OL 0.4 V I OUT = –3.0 mA High Level Output Leakage Current, I OH 0.1 1 µAV OUT = VCC FAN SPEED RAMP RATES Counter Frequency 1 ± 50% 16 ± 50% Hz OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, V OL 0.4 V I OUT = –3.0 mA High Level Output Leakage Current, I OH 0.1 1 µAV OUT = VCC SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, V IH 2.1 V Input Low Voltage, V IL 0.8 V Input Leakage Current ±5 µA Hysteresis 500 mV Note 4 DIGITAL INPUT LOGIC LEVELS (FAN_SPD/TEST_IN, GPI) Input High Voltage, V IH 2.2 V Input Low Voltage, V IL 0.8 V DIGITAL INPUT LEAKAGE CURRENT (ALL DIGITAL INPUTS) Input High Current, I IH –1 –0.005 µAV IN = VCC Input Low Current, I IL +0.005 +1 µAV IN = 0 Input Capacitance, CIN 3 6 9 pF Note 4

1Typicals are at T A = 25°C and represent most likely parametric norm. Standby current typ is measured with V CC = 3.3 V. 2Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.2 V for a rising edge. 3IOH for FAN_OFF guaranteed by design, not production tested. 4Guaranteed by design, not production tested. Specifications subject to change without notice. conditions for extended periods may affect device reliability. Figure 1. Serial Bus Timing Diagram

REV. A ADM1028 –4– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 FAN_OFF Digital Output (Open Dra in) Fan Off Request. When asserted low, this indi cates a request to shut off the fan independent of the FAN_SPD output. When negated (output FET off) it indicates that the fan may be turned on. 2 GPI Digital Input (12 V tolerant). This pin is a general-purpose logic input with 12 V toler- ance. It can be programmed as an active high or active low input that sets Bit 4 of the Interrupt Status Register. A voltage >2.2 V on this pin, represents a Logic “1,” while a floating condition is interpreted as Logic “0.” 3 AUXRST Digital Input. This pin can be driven low as an input to reset the ADM1028. 4 GND Ground. Power and signal ground. CC3AUX Power 3.3 V Aux. Power source and voltage monitor input for power-on reset. 6 RST Digital Input. This pin can be pulled low externally to indicate to the ADM1028 that the main system power has been removed. The ADM1028 will shut off the FAN_SPD out- put and reset its R_OFF output. 7 R_RST Digital Output (Open Drain). This pin is a remote reset output that pu lses low on receipt of a specific SMBus message. 8 FAN_SPD/NTEST_IN Analog Output/ Test Input. An active-high input that enables NAND board-level connectivity testing. Refer to section on NAND testing. Used as an analog output for fan speed control when NAND test is not selected. 9 D– Remote Thermal Diode Negative Input. This is the negative input (current sink) from the remote thermal diode. This also serves as the negative input into the A/D. 10 D+ Remote Thermal Diode Positive Input. This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. 11 THERMA/NTEST_OUT Digital Output (Open Drain with Integrated V CC3AUX Pull-Up). An active low thermal overload output that indicates a violation of a temperature setpoint (over temperature). The fan is on full-speed whenever this pin is asserted low. Acts as the output of the NAND Tree when the ADM1028 is in NAND Tree Test Mode. 12 THERMB Digital Output (Open Drain). This pin is a second THERM signal. It can be used to drive external circuitry with a different external pull-up supply rail. 13 R_OFF Digital Output or Open Drain with Integrated V CC3AUX Pull-Up. Remote off (power- down) output. This pin is driven high on receipt of a specific SMBus message. The pin (and its associated register bit) remain high until the RST input is asserted low. 14 INT Digital Output (Open Drain), System Interrupt Output. This signal indicates a violation of a set trip point. The output is enabled when Bit 1 of the Configuration Register is set to 1. The default state is disabled. 15 SCL Digital Input. SMBus Clock. 16 SDA Digital I/O (Open Drain). SMBus Bidirectional Data. PIN CONFIGURATION TOP VIEW (Not to Scale) FAN_OFF GPI AUXRST GND VCC3AUX RST R_RST FAN_SPD/NTEST_IN SDA SCL INT R_OFF THERMB THERMA/NTEST_OUT ADM1028

REV. A –5– Typical Performance Characteristics–ADM1028 LEAKAGE RESISTANCE – M/H9024 TEMPERATURE ERROR – /H11543C –20 10 100 –30 –10 D+ TO VDD D+ TO GND TPC 1. Temperature Error vs. PC Board Track Resistance (D+ to VDD) FREQUENCY – Hz TEMPERATURE ERROR – /H11543C 10 100k 1000M 10k 100M1k 10M100 1M VIN = 250mV p-p VIN = 100mV p-p TPC 2. Temperature Error vs. Power Supply Noise Frequency FREQUENCY – Hz 14TEMPERATURE ERROR – /H11543C 1 10 100 1k 10k 100k 1M 10M 100M 1G VIN = 25mV p-p VIN = 50mV p-p VIN = 100mV p-p TPC 3. Temperature Error vs. Common-Mode Noise Frequency TEMPERATURE – /H11543C ERROR – /H11543C 0 1 02 03 04 05 06 07 08 09 0 100 LOWER SPEC LEVEL UPPER SPEC LEVEL TPC 4. Temperature Error of ADM1028 vs. Pentium® III Temperature CAPACITANCE – nF TEMPERATURE ERROR – /H11543C 01 02 03 0 4 05 06 0 7 0 TPC 5. Temperature Error vs. Capacitance Between D+ and D– SCLK FREQUENCY – kHz SUPPLY CURRENT – mA 1.77 1 5 10 25 50 75 100 1.67 1.72 1.82 1.87 1.92 1.97 2.02 250 500 750 1000 VDD = 5V VDD = 3.3V TPC 6. Standby Current vs. Clock Frequency

REV. A ADM1028 –6– FREQUENCY – Hz TEMPERATURE ERROR – /H11543C 1k 1M10 100 10k 100k 10M 100M 1B VIN = 10mV p-p TPC 7. Temperature Error vs. Differential-Mode Noise Frequency TEMPERATURE – /H11543C 2.3STANDBY SUPPLY CURRENT – mA 1.7 –40 1.5 1.6 1.8 1.9 2.0 2.1 2.2 –20 0 20 40 60 80 100 130–10–30 10 30 50 70 90 120 VDD = 5.5V VDD = 3.0V VDD = 3.3V TPC 8. Standby Supply Current vs. Temperature FUNCTIONAL DESCRIPTION The ADM1028 is a low-cost temperature monitor and fan con- troller for microprocessor-based systems. The temperature of a remote sensor diode may be measured, allowing monitoring of processor temperature in a single-processor system. An on- chip temperature sensor allows monitoring of system ambient temperature. Measured values can be read out via the serial System Manage- ment Bus, and values for limit comparisons can be programmed in over the same serial bus. The ADM1028 also contains a DAC for fan speed control. An automatic hardware temperature trip point is provided for fault tolerant fan control and the fan will be driven to full speed if this is exceeded. Two interrupt outputs are provided, which will be asserted if the software or hardware limits are exceeded. Finally, the chip has remote reset and shutdown capabilities. INTERNAL REGISTERS OF THE ADM1028 A brief description of the ADM1028’s principal internal registers is given below. More detailed information on the function of each register is given in Tables III to IX. Configuration Register: Provides control and configuration. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1028, the first byte of data is always a register address, which is written to the Address Pointer Register. Interrupt (INT) Status Register: This register provides sta- tus of each Interrupt event. Interrupt (INT) Mask Register: Allows masking of individual interrupt sources. Value and Limit Registers: The results of temperature mea- surements are stored in these registers, along with their limit values. Analog Output Register: The code controlling the analog output DAC is stored in this register. Alert Status Register: Indicates the status of the THERM signal and GPI pin. Remote Function Register: This register allows control of the R_RST and R_OFF outputs. Fan Speed Ramp Register: This register allows enabling/ disabling of DAC ramp, as well as providing control of fan speed ramp rate. SERIAL BUS INTERFACE Control of the ADM1028 is carried out via the serial bus. The ADM1028 is connected to this bus as a slave device, under the control of a master device, e.g. the 810 chipset. The ADM1028 has a 7-bit serial bus address. When the device powers up, it will do so with a default serial bus address. The SMBus address for the ADM1028 is 0101110 binary. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/ W bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowl- edge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The num- ber of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop condi- tions are established. In WRITE mode, the master will pull the data line high during the tenth clock pulse to assert a

only be exited once the ADM1028 is powered down. typical propagation delay of 500 ns. Figure 10. NAND Tree On power-up, the Interrupt functionality of the device is disabled. the Register should be set to 1. by reading the Status Register. be to write limits into the Limit Registers.

• Configuration Register
• Interrupt Status Register
• Interrupt Mask Register
• Analog Output Register
• Programmable Trip Point Registers The ADM1028 can also be reset by taking AUXRST low as an input. All registers will be reset to their default values and the ADC will remain inactive as long as AUXRST is below the reset threshold. Taking the RST pin low will cause the following registers to be reset.
• Bit 3 of the Configuration Register (Programmable THERM Limit Lock Bit)
• DAC Output, Fan Speed INITIALIZATION (SOFT RESET) Soft reset performs a similar, but not identical, function to power-on reset. It restores the power-on default values to the Configuration Register, the Interrupt Status Register and the Interrupt Mask Register. The Limit Registers remain unchanged. It rearms the INT structure but not the THERM structure. Soft reset is accomplished by setting Bit 4 of the Configuration Register high. This bit automatically clears after being set. Unlike clearing INT, where the temperature must fall back within the set limits for three conversions before the INT function is rearmed, the soft reset allows INT to be pulled low immediately after the soft reset.

REV. A ADM1028 –13– Table III. ADM1028 Registers Register Name Address A7–A0 in Hex Comments Value Registers 0x14–0x38 See Table IV Company ID 0x3E This location will contain the company identification number. This register is read only. Revision 0x3F This location will contain the revision number of the part in the lower four bits of the register [3:0]. The upper four bits reflect the ADM1028 Version Number [7:4]. The first version is 1101. The next version of ADM1028 would be 1110, etc. For instance, if the stepping were A0 and this part is an ADM1028, this register would read 1101 0000. This register is read only. Configuration Register 0x40 See Table V. Power-on value = 0010 0001. Interrupt Status Register 0x41 See Table VI. Power-on value = 0000 0000. Interrupt Mask Register 0x43 See Table VII. Power-on value = 0000 0000. Manufacturer Test 0x44–0x4A Test Registers for manufacturer’s use only. Do not write to these registers. Remote Function 0x4B See Table VIII. Power-on value = 0000 0000. Alert Status 0x4C See Table IX. Power-on value = 0000 0000. Fan Speed Ramp Register 0xCO See Table X. Power-on value = 0000 0000. Table IV. Registers 0x13–0x3A Value Registers Address Read/Write Description 0x13 Read/Write Programmable Internal Therm Automatic Trip Point—Default 127 °C. This register can only be written to if the write once bit in the Configuration Register (0x40, Bit 3) has not been set. 0x14 Read/Write Program mable Remote Thermal Diode Automatic Trip Point—Default 100 °C. This register can only be written to if the write once bit in the Configuration Register (0x40, Bit 3) has not been set. 0x15 Read/Write Test register for manufacturer’s use only. Do not write to this register. 0x17 Read Only Default Internal Therm Automatic Trip Point—Default 70 °C. Cannot be changed. Disabled when Bit 3 of Configuration Register is set. 0x18 Read Only Default Remote Thermal Diode Automatic Trip Point—Default 100 °C. Cannot be changed. Disabled when Bit 3 of Configuration Register is set. 0x19 Read/Write Analog Output, FAN_SPD (Defaults to 0x00h). 0x26 Read Only External/Remote Temperature Value. 0x27 Read Only Internal Temperature Value. 0x37 Read/Write External/Remote Temperature High Limit—Default +127 °C. 0x38 Read/Write External/Remote Temperature Low Limit—Default –128 °C. 0x39 Read/Write Internal Temperature High Limit—Default +127 °C. 0x3A Read/Write Internal Temperature Low Limit—Default –128 °C.

REV. A ADM1028 –14– Table V. Register 0x40 Configuration Register Power-On Default <7:0> = 21h Bit Name R/ W Description

0 START Read/Write Setting this bit to a “1” enables startup of ADM1028; clearing this bit to “0”

places ADM1028 in standby mode. At startup, temperature monitoring and limit checking functions begin. Note, all limit values should be programmed into ADM1028 prior to using the standard thermal interrupt mechanism based upon high and low limits. (Power-Up Default = 1.) 1 INT Enable Read/Write Setting this bit to a “1” enables the INT output. 1 = Enabled 0 = Disabled (Power-Up Default = 0.) 2 Reserved Read Only Reserved (Default = 0). 3 Programmable Read/Write Once S etting this bit to a “1” will lock in the value set into the Programmable Remote Therm Limit Therm Limit Register (Value Register 0x14). Furthermore, if this bit is set, Lock Bit the values in the Default Remote Therm Limit Register Bit (Value Register 0x18) will no longer have an effect on the THERM, FAN_SPD, or FAN_OFF outputs. This bit cannot be written again until after RST has been asserted. (Power-Up Default = 0.)

4 Soft Reset Read/Write Setting this bit to a “1” will restore power-up default values to the Configu-

ration Register, Interrupt Status Register and Interrupt Mask Register. This also rearms INT structure but not the THERM structure. This bit automati- cally clears itself since the power-on default is zero. 5 FAN_OFF Read/Write Setting this bit to a “1” will cause the FAN_OFF pin to be floated. Clearing this bit to “0” will cause the FAN_OFF pin to be driven low which requests that the fan be turned off. This bit will be unconditionally set if the THERM pin is ever asserted; once THERM is negated this bit must be returned to its prior state (prior to THERM assertion). Reading this bit reflects the state of the FAN_OFF output buffer. Due to the open-drain nature of this pin the value read does not represent the actual state of the external circuit con- nected to it. (Power-Up Default = 1.)

6 GPI Invert Read/Write Setting this bit to a “1” will invert the GPI input for the purpose of level

detection and interrupt generation. Clearing this bit to “0” leaves the GPI input unmodified. (Power-Up Default = 0.) 7 Reserved Read Only Reserved. (Power-Up Default = 0). Table VI. Register 0x41. Interrupt Status Register. Power-On Default <7:0> = 00h Bit Name Read/Write Description 0 Int. Temp Error Read/Write A one indicates that one of the limits for the internal temperature sensor “1” to clear has been exceeded.

1 Flag 1 Read/Write This bit can be used as a general purpose flag with the capability of generat-

ing an interrupt. Writing a “1” to this bit causes it to be set to “1.” Writing a “0” clears this bit.

2 Flag 2 Read/Write This bit can be used as a general purpose flag with the capability of generat-

ing an interrupt. Writing a “1” to this bit causes it to be set to “1.” Writing a “0” clears this bit. 3 Int. THERM Read/Write A one indicates that the internal thermal overload ( THERM) limit has “1” to clear been exceeded. 4 GPI Input Read Only A “1” indicates that the GPI pin is asserted. The polarity of the GPI pin is determined by GPI Invert (Bit 6) in the Configuration Register. For ex- ample, if GPI Invert is cleared then this bit will be “1” when the GPI pin is high (“1”); this bit will be “0” when the GPI pin is low (“0”.) If GPI Invert is set then this bit will be “1” when the GPI pin is low (“0”); this bit will be “0” when the GPI pin is high (“1”). Note that the state of GPI is not latched; this bit simply reflects the state or inverted state of the GPI pin. Note: if this bit is “1” reading this register will NOT clear it to “0.” 5 Ext. Temp Error Read/Write A one indicates that one of the limits for the external temperature sensor “1” to clear has been exceeded. 6 Ext. THERM Read/Write A one indicates that the external thermal overload ( THERM) limit has “1” to clear been exceeded. 7 Ext Diode Fault Read/Write A one indicates either a short- or open-circuit fault on the remote sensor diode. “1” to clear

REV. A ADM1028 –15– Table VII. Register 0x43 Interrupt Mask Register. Power-On Default <7:0> = 00h Bit Name Read/Write Description 0 Int Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output. 1 Flag 1 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 2 Flag 2 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 3 Int THERM Read/Write A one disables the corresponding interrupt status bit for the INT output. 4 GPI Mask Read/Write A one disables the corresponding interrupt status bit for the INT output. 5 Ext Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output. 6 Ext THERM Read/Write A one disables the corresponding interrupt status bit for the INT output. 7 Ext Diode Fault Read/Write A one disables the corresponding interrupt status bit for the INT output. Table VIII. Register 0x4B Remote Function Register. Power-On Default <7:0> = 00h Bit Name Read/Write Description

0 R_RST Read/Write Writing a “1” to this bit causes the R_RST output to be pulsed low for a

minimum of 125 µs. This bit will self-clear to 0 when the R_RST pulse is complete. Writing a “0” to this bit has no effect. Reading this bit reflects the state of this register bit and not the state of the pin. The power-on default value is “0.” 1 R_OFF Read/Write Writing a “1” to this bit causes the R_OFF output to be driven high. This bit will be cleared, and the output driven low, when RST is asserted. Writing a “0” to this bit has no effect. The power-on default value is “0.” 2 Reserved Read/Write Reserved (Default = 0). 3 Reserved Read/Write Reserved (Default = 0). 4 Reserved Read/Write Reserved (Default = 0). 5 Reserved Read/Write Reserved (Default = 0). 6 Reserved Read/Write Reserved (Default = 0). 7 Reserved Read/Write Reserved (Default = 0). Table IX. Register 0x4C Alert Status Register. Power-On Default <7:0> = 00h Bit Name Read/Write Description 0 Ext THERM Alert Read Only A one indicates that the external thermal overload limit is currently exceeded.

1 GPI Alert Read Only This bit represents the logic level of the GPI pin if Bit 6 of the Configuration

Register is “0,” or the inverse logic level of the GPI pin if Bit 6 of the Con- figuration Register is “1.” 2 Int THERM Alert Read Only A one indicates that the internal thermal overload limit is currently exceeded. 3 Reserved Read Only Undefined. 4 Reserved Read Only Undefined. 5 Reserved Read Only Undefined. 6 Reserved Read Only Undefined. 7 Reserved Read Only Undefined.

REV. A–16– C02365–0–2/02(A) PRINTED IN U.S.A. ADM1028 Table X. Register 0xCO Fan Speed Ramp Register. Power-On Default <7:0> = 00h Bit Name Read/Write Description 0 Fan Speed Ramp Read/Write Setting this bit to a “1” will enable the fan speed ramping mechanism. Enable When this bit is a 1, writing to the Fan Speed Register will set the new target fan speed; the input to the DAC will then count, up or down as appropriate, to the new fan speed value at the rate specified in bits [1:2] of this register. Clearing this bit to “0” will disable the fan speed ramp- ing mechanism and will cause data written to the Fan Speed Register to be immediately reflected to the DAC. The DAC input may or may not continue ramping if this bit is changed from a “1” to a “0” while the fan speed is currently ramping. <2:1> Ramp Rate Read/Write Fan Speed Ramp Rate. The speed at which the fan speed ramp counter increments/decrements is selected as follows: Bits <2:1> Count Rate Counter Frequency 00 1.0s 1 Hz 01 0.25s 4 Hz 10 0.125s 8 Hz 11 0.0625s 16 Hz <7:3> Reserved Read/Write Reserved (Default = 0) 16-Lead Shrink Small Outline Package (QSOP) (RQ-16) 16 9 0.197 (5.00) 0.189 (4.80) 0.244 (6.20) 0.228 (5.79) PIN 1 0.157 (3.99) 0.150 (3.81) SEATING PLANE 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) BSC 0.059 (1.50) MAX 0.069 (1.75) 0.053 (1.35) 0.010 (0.20) 0.007 (0.18) 0.050 (1.27) 0.016 (0.41) 8/H11543 0/H11543 REF: JEDEC 0.150" SSOP – DRAWING NUMBER MO-137 OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

Revision History

Data Sheet changed from REV. 0 to REV. A.