ADM1027

ADM1027 ONSEMI | Alldatasheet

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ADM1027 * dB COOL ™ Remote Thermal Controller and Voltage Monitor *Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.

FEATURES

Monitors up to 5 Supply Voltages Controls and Monitors up to 4 Fan Speeds

1 On-Chip and 2 Remote Temperature Sensors

Monitors up to 5 Processor VID Bits Automatic Fan Speed Control Mode Controls System Cooling Based on Measured Temperature Enhanced Acoustic Mode Dramatically Reduces User Perception of Changing Fan Speeds 2-Wire and 3-Wire Fan Speed Measurement Limit Comparison of All Monitored Values Meets SMBus 2.0 Electrical Specifications (Fully SMBus 1.1 Compliant)

APPLICATIONS

Networking and Telecommunications Equipment FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The ADM1027 dB COOL controller is a complete systems monitor and multiple PWM fan controller for noise s ensitive applications requiring active system cooling. It ca n monitor 12 V, 5 V, 2.5 V CPU supply voltage, plus its own s upply volt- age. It can monitor the temperature of up to two re mote sensor diodes, plus its own internal temperature. It can m easure and control the speed of up to four fans so that they o perate at the lowest possible speed for minimum acoustic noise. T he auto- matic fan speed control loop optimizes fan speed fo r a given temperature. Once the control loop parameters are programmed, the ADM1027 can vary fan speed without CPU interven tion. BAND GAP REFERENCE 10-BIT ADC INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER GND SERIAL BUS INTERFACE SCL SDA VID REGISTER FAN SPEED COUNTER ADDRESS POINTER REGISTER ADM1027 VALUE AND LIMIT REGISTERS LIMIT COMPARATORS PWM CONFIGURATION REGISTERS INTERRUPT STATUS REGISTERS BAND GAP TEMP. SENSOR VID4 VID3 VID2 VID1 VID0 PWM REGISTERS AND CONTROLLERS PWM1 PWM2 V CC TO ADM1027 AUTOMATIC FAN SPEED CONTROL PWM3 TACH1 TACH2 TACH3 TACH4 INTERRUPT MASKING SMBALERT ACOUSTIC ENHANCEMENT CONTROL VCC D1+ D1– D2+ D2– +5V IN +12V IN +2.5V IN VCCP SMBUS ADDRESS SELECTION ADDR EN ADDR SELECT ©2010 SCILLC. All rights reserved. Publication Order Number: May 2010 - Rev. 3 ADM1027/D

REV. A –2– ADM1027–SPECIFICATIONS 1, 2, 3, 4 (T A = T MIN to T MAX (0 /H11543C to 105 /H11543C), V CC = V MIN to V MAX (3 V to 5.5 V), unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage 3.0 3.3 5.5 V Supply Current, I CC 1.4 3 mA Interface Inactive, ADC Active TEMP-TO-DIGITAL CONVERTER Local Sensor Accuracy ± 3 oC 0 oC /H11349 T A /H11349 105 oC ± 2 oC 0 oC /H11349 T A /H11349 70 oC ± 1 oC T A = 40 oC Resolution 0.25 oC Remote Diode Sensor Accuracy ± 3 oC 0 oC /H11349 T D /H11349 120 oC ±1.5 oC 0 oC /H11349 T D /H11349 120 oC; 0 oC /H11349 T A /H11349 70 oC ± 1 oC T A = 40 oC oC 0 oC /H11349 T D /H11349 120 oC; T A = 40 oC Resolution 0.25 oC Remote Sensor Source Current 200 mA High Level 12 mA Low Level ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE ±0.5 ± 1 % All ADC Inputs except 12 V ±1.5 % 12 V Input Differential Nonlinearity, DNL ± 1 LSB 8 Bits Power Supply Sensitivity ±0.1 %/V Conversion Time (Voltage Input) 11.38 12.29 ms Averagin g Enabled Conversion Time (Local Temperature) 12.09 13.05 ms Aver aging Enabled Conversion Time (Remote Temperature) 25.59 27.64 ms Ave raging Enabled Total Monitoring Cycle Time 120.17 129.78 ms Averaging Enabled Total Monitoring Cycle Time 13.51 14.59 ms Averaging Di sabled Input Resistance 80 140 250 k /H9024 FAN RPM-TO-DIGITAL CONVERTER Accuracy ± 6 % 0 oC /H11349 T A /H11349 70 oC ± 8 % 3.0 V /H11349 V CC /H11349 3.6 V Full-Scale Count 65,535 Nominal Input RPM 109 RPM Fan Count = 0xBFFF

329 RPM Fan Count = 0x3FFF

5,000 RPM Fan Count = 0x0438 10,000 RPM Fan Count = 0x021C Internal Clock Frequency 82.8 90 97.2 kHz OPEN-DRAIN DIGITAL OUTPUTS, PWM1–PWM3, XTO Current Sink, I OL 8.0 mA Output Low Voltage, V OL 0.4 V I OUT = –8.0 mA, V CC = 3.3 V High Level Output Current, I OH 0.1 1 mA V OUT = V CC Rev. 3 | Page 2 of 56 | www.onsemi.com

REV. A ADM1027 –3– Parameter Min Typ Max Unit Test Conditions/Comment OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, V OL 0.4 V I OUT = –4.0 mA, V CC = 3.3 V High Level Output Current, I OH 0.1 1 mA V OUT = V CC SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, V IH 2.0 V Input Low Voltage, V IL 0.4 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (VID0–4) Input High Voltage, V IH 1.7 V Input Low Voltage, V IL 0.8 V DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, V IH 2.0 V

5.5 V Maximum Input Voltage

Input Low Voltage, V IL 0.8 V –0.3 V Minimum Input Voltage Hysteresis 0.5 V p-p DIGITAL INPUT CURRENT Input High Current, I IH –1 mA V IN = V CC Input Low Current, I IL 1 mA V IN = 0 Input Capacitance, C IN 5 pF SERIAL BUS TIMING Clock Frequency, f SCLK 10 100 kHz See Figure 1 Glitch Immunity, t SW 50 ns See Figure 1 Bus Free Time, t BUF 4.7 ms See Figure 1 Start Setup Time, t SU;STA 4.7 ms See Figure 1 Start Hold Time, t HD;STA 4.0 ms See Figure 1 SCL Low Time, t LOW 4.7 ms See Figure 1 SCL High Time, t HIGH 4.0 50 ms See Figure 1 SCL, SDA Rise Time, t r 1000 ns See Figure 1 SCL, SDA Fall Time, t f 300 ms See Figure 1 Data Setup Time, t SU;DAT 250 ns See Figure 1 Data Hold Time, t HD;DAT 300 ns See Figure 1 Detect Clock Low Timeout, t TIMEOUT 15 35 ms Can Be Optionally Disabled NOTES 1All voltages are measured with respect to GND, unle ss otherwise specified. 2Typicals are at T A = 40 /g114C and represent the most likely parametric norm. 3Logic inputs will accept input high voltages up to V MAX even when the device is operating down to V MIN . 4Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.0 V for a rising edge. Specifications subject to change without notice. Rev. 3 | Page 3 of 56 | www.onsemi.com

conditions for extended periods may affect device r eliability. to avoid performance degradation or loss of functio nality. Figure 1. Diagram for Serial Bus Timing

REV. A ADM1027 –5– PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 SDA Digital I/O (Open-Drain). SMBus bidirectional s erial data. Requires SMBus pull-up. 2 SCL Digital Input (Open-Drain). SMBus serial clock input. Requires SMBus pull-up. 3 GND Ground Pin for the ADM1027. 4 V CC Power Supply. Can be powered by 3.3 V standby if mo nitoring in low power states is required. VCC is also monitored through this pin. The ADM1027 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x4 0) rescales the V CC input attenuators to correctly measure a 5 V supply. 5 VID0 Digital Input (Open-Drain). Voltage supply rea douts from CPU. This value is read into the VID register (Reg. 0x43). 6 VID1 Digital Input (Open-Drain). Voltage supply rea douts from CPU. This value is read into the VID register (Reg. 0x43). 7 VID2 Digital Input (Open-Drain). Voltage supply rea douts from CPU. This value is read into the VID register (Reg. 0x43). 8 VID3 Digital Input (Open-Drain). Voltage supply rea douts from CPU. This value is read into the VID register (Reg. 0x43). 9 TACH3 Digital Input (Open-Drain). Fan tachometer in put to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure t he speed of 2-wire fans. 10 PWM2/ SMBALERT Digital Output (Open-Drain). Requires 10 k W typical pull-up. Pulsewidth modulated output to control Fan 2 speed. This pin may be reconfigure d as an SMBALERT interrupt output to signal out-of-limit conditions. 11 TACH1 Digital Input (Open-Drain). Fan tachometer i nput to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure t he speed of 2-wire fans. 12 TACH2 Digital Input (Open-Drain). Fan tachometer i nput to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure t he speed of 2-wire fans. 13 PWM3/ ADDRESS ENABLE Digital I/O (Open-Drain). Pulsewidth modulated outp ut to control Fan 3 speed. Requires 10 k W typical pull-up. If pulled low on power-up, this p laces the ADM1027 into address select mode, and the state of Pin 14 will determine the ADM1027’s slave address. 14 TACH4/ADDRESS SELECT Digital Input (Open-Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2 -wire fans. If in address select mode, this pin determines the SMBus device address. 15 D2– Cathode Connection to Second Thermal Diode. 16 D2+ Anode Connection to Second Thermal Diode. 17 D1– Cathode Connection to First Thermal Diode. 18 D1+ Anode Connection to First Thermal Diode. 19 VID4 Digital Input (Open-Drain). Voltage supply re adouts from CPU. This value is read into the VID register (Reg. 0x43). 20 5V IN Analog Input. Monitors 5 V power supply. 21 12V IN Analog Input. Monitors 12 V power supply. 22 2.5V IN Analog Input. Monitors 2.5 V supply, typically a ch ipset voltage. 23 V CCP Analog Input. Monitors processor core voltage (0 V to 3 V). 24 PWM1/XTO Digital Output (Open-Drain). Pulsewidth m odulated output to control Fan 1 speed. Requires 10 k W typical pull-up. Also functions as the output from the XOR tree in XOR test mode. Rev. 3 | Page 5 of 56 | www.onsemi.com

REV. A –6– ADM1027 FUNCTIONAL DESCRIPTION General Description The ADM1027 is a complete systems monitor and multiple fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial sy stem management bus. The serial bus controller has an op tional address line for device selection (Pin 14), a seria l data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and prog ramming functions of the ADM 1027 are performed over the serial bus. In addition, one of the pins can be reconfigured as an SMBALERT output to indicate out-of-limit conditions. Measurement Inputs The device has six measurement inputs, four for vol tage and two for temperature. It can also measure its own su pply voltage and can measure ambient temperature with its on-chi p tempera- ture sensor. Pins 20 to 23 are analog inputs with on-chip attenu ators, configured to monitor 5 V, 12 V, 2.5 V, and the pro cessor core voltage (2.25 V input), respectively. Power is supplied to the chip via Pin 4, which the system also uses to monitor V CC . In PCs, this pin is normally connected to a 3.3 V standby supply. This pin can, however, be con nected to a 5 V supply and monitor it without overranging. Remote temperature sensing is provided by the D1+/– and D2+/– inputs, to which diode-connected, external te mperature- sensing transistors such as a 2N3906 or CPU thermal diode may be connected. The ADC also accepts input from an on-chip band gap tem- perature sensor that monitors system ambient temper ature. Sequential Measurement When the ADM1027 monitoring sequence is started, it cycles sequentially through the measurement of analog inpu ts and the temperature sensors. Measured values from these inp uts are stored in value registers. These can be read out ov er the serial bus, or can be compared with programmed limits stor ed in the limit registers. The results of out-of-limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions. Processor Voltage ID Five digital inputs (VID0 to VID4 — Pins 5 to 8 and 19) read the processor Voltage ID code and store it in the V ID register, from which it can be read out by the management sys tem over the serial bus. The VID code monitoring function is compatible with both VRM9.x and future VRM10 solutions. The VI D code monitoring function is compatible with VRM9.x. ADM1027 Address Selection Pin 13 is the dual function PWM3/ ADDRESS ENABLE pin. If Pin 13 is pulled low on power-up, the ADM1027 will read the state of Pin 14 (TACH4/ADDRESS SELECT pin) to determine the ADM1027 slave address. If Pin 13 is high on power-up, then the ADM1027 will default to SMBus slave address 0x5 C. This function is described later in more detail. Internal Registers of the ADM1027 A brief description of the ADM1027’s principal inte rnal regis- ters follows. More detailed information on the func tion of each register is given in Tables IV to XXXVI. Configuration Registers Provide control and configuration of the ADM1027, i ncluding alternate pinout functionality. Address Pointer Register Contains the address that selects one of the other internal registers. When writing to the ADM1027, the first byte of data is always a register address, which is written to the Address Pointer Register. Status Registers Provide the status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. If Pin 10 is configured as SMBALERT , then this pin will assert low whenever a status bit gets set. Interrupt Mask Registers Allow each interrupt status event to be masked when Pin 10 is configured as an SMBALERT output. This affects only the SMBALERT output and not the bits in the status register. VID Register The status of the VID0 to VID4 pins of the processo r can be read from this register. Value and Limit Registers The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along w ith their limit values. Offset Registers Allow each temperature channel reading to be offset by a twos complement value written to these registers. TMIN Registers Program the starting temperature for each fan under automatic fan speed control. TRANGE Registers Program the temperature-to-fan speed control slope in automatic Fan Speed Control Mode for each PWM output. Enhance Acoustics Registers Allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics. Rev. 3 | Page 6 of 56 | www.onsemi.com

REV. A Typical Performance Characteristics–ADM1027 –7– LEAKAGE RESIST ANCE (M /H9024) REMOTE TEMPERA TURE ERROR ( /H11543C) –20 1.0 3.3 100.0 10.0 30.0 –10 –15 DXP TO GND DXP TO V CC (3.3V) TPC 1. Remote Temperature Error vs. Leakage Resistance FREQUENCY (Hz) REMOTE TEMPERA TURE ERROR ( /H11543C) 14.0 12.0 –2.0 100k 550k 50M 6.0 4.0 2.0 10.0 8.0 100mV 250mV TPC 4. Remote Temperature Error vs. Power Supply Noise Frequency FREQUENCY (Hz) REMOTE TEMPERA TURE ERROR ( /H11543C) 16.0 60k 14.0 12.0 10.0 8.0 6.0 4.0 2.0 –2.0 110k 1M 10M 50M 10mV 20mV TPC 7. Remote Temperature Error vs. Differential Mode Noise Frequency DXP – DXN CAP ACIT ANCE (nF) REMOTE TEMPERA TURE ERROR ( /H11543C) –12 –15 –18 –21 –24 –27 –30 –33 –36 REMOTE TEMPERA TURE ERROR ( /H11543C) TPC 2. Remote Temperature Error vs. Capacitance between D+ and D– FREQUENCY (Hz) LOCAL TEMPERA TURE ERROR ( /H11543C) 12.5 10.0 –5.0 100k 550k 50M 5.0 2.5 –2.5 7.5 100mV 250mV TPC 5. Local Temperature Error vs. Power Supply Noise Frequency FREQUENCY (Hz) REMOTE TEMPERA TURE ERROR ( /H11543C) 40.0 10k 35.0 30.0 25.0 20.0 15.0 10.0 5.0 –5.0 –10.0 100k 1M 10M 20mV 40mV 100mV TPC 8. Remote Temperature Error vs. Common Mode Noise Frequency TEMPERA TURE ( /H11543C) REMOTE TEMPERA TURE ERROR ( /H11543C) –40 0 40 80 120 –3 SIGMA +3 SIGMA TPC 3. Remote Temperature Error vs. Actual Temperature 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 2.50 5.50 SUPPL Y CURRENT (mA) TPC 6. Supply Current vs. Supply Voltage Rev. 3 | Page 7 of 56 | www.onsemi.com

bus as a slave device, under the control of a master controller. then determines the device’s SMBus address.

0 Low (10 k W to GND) 0101100 (0x58)

0 High (10 k W pull-up) 0101101 (0x5A)

1 Don’t Care 0101110 (0x5C)

Figure 2. Default SMBus Address = 0x5C Figure 3. SMBus Address = 0x58 (Pin 14 = 0) thereafter will have no immediate effect. ADM1027 is used in a system). in and out the correct circuit at the correct time. Figure 4. SMBus Address = 0x5A (Pin 14 = 1) Figure 5. Unpredictable SMBus Address if Pin 13

1. The master initiates data transfer by establishin g a start

data line SDA while the serial clock line SCL remai ns high. will be written to or read from the slave device.

1. Data is sent over the serial bus in sequences of nine clock

when the clock is high may be interpreted as a stop signal. only by what the master and slave devices can handl e.

1. When all data bytes have been read or written, stop conditions

1. Once the ADM1027 has responded to the alert respo nse

the SMBus timeout feature, so it can be disabled. The ADM1027 has four external voltage measurement channels. It can also measure its own supply voltage, V CC .

3.3 V, 5 V, 12 V and the processor core voltage V CCP , without

has adequate headroom to cope with overvoltages. The internal structure for the analog inputs is shown in Figure 12. that gives the input immunity to high frequency noi se. can also generate SMBALERT interrupts. Figure 12. Structure of Analog Inputs codes of the 10-bit A/D converter. input in 711 ms, and averages 16 conversions to reduce noise. Therefore a measurement on any input takes nominally 11.38 ms.

REV. A –12– ADM1027 Table II. 10-Bit A/D Output Code vs. V IN Input Voltage A/D Output 12 V IN 5 V IN VCC (3.3 V IN )* 2.5 V IN VCCPIN Decimal Binary (10 Bits) *The V CC output codes listed assume that V CC is 3.3 V. If V CC input is reconfigured for 5 V operation (by settin g Bit 7 of Configuration Register 1), then the V CC output codes are the same as for the 5 V IN column. Rev. 3 | Page 12 of 56 | www.onsemi.com

REV. A ADM1027 –13– VID CODE MONITORING The ADM1027 has five dedicated voltage ID (VID code) inputs. These are digital inputs that can be read back thro ugh the VID register (Reg. 0x43) to determine the processor voltage required/being used in the system. Five VID code in puts support VRM9.x solutions. VID CODE REGISTER – Register 0x43 <0> = VID0 (reflects logic state of Pin 5) <1> = VID1 (reflects logic state of Pin 6) <2> = VID2 (reflects logic state of Pin 7) <3> = VID3 (reflects logic state of Pin 8) <4> = VID4 (reflects logic state of Pin 19) ADDITIONAL ADC FUNCTIONS A number of other functions are available on the AD M1027 to offer the systems designer increased flexibility: Turn Off Averaging For each voltage measurement read from a value regi ster, 16 readings have actually been made internally and t he results averaged before being placed into the value registe r. There may be an instance where the user would like to speed up conversions. Setting Bit 4 of Configuration Register 2 (Reg. 0x7 3) turns averaging off. This effectively gives a reading 16 ¥ faster than 711 ms, but the reading may be noisier. Bypass Voltage Input Attenuators Setting Bit 5 of Configuration Register 2 (Reg. 0x7 3) removes the attenuation circuitry from the 2.5 V, V CCP , V CC , 5 V, and 12 V inputs. This allows the user to directly conne ct external sensors or rescale the analog voltage measurement i nputs for other applications. The input range of the ADC with out the attenuators is 0 V to 2.25 V. Single-Channel ADC Conversions Setting Bit 6 of Configuration Register 2 (Reg. 0x7 3) places the ADM1027 into single-channel ADC conversion mode. In this mode, the ADM1027 can be made to read a single voltage channel only. If the internal ADM1027 clock is used, the se lected input will be read every 711 ms. The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1 minimum high byte register (0x55). Bits <7:5> Reg. 0x55 Channel Selected 000 2.5 V 001 V CCP

010 V CC

Configuration Register 2 (Reg. 0x73) <4> = 1 Averaging off <5> = 1 Bypass input attenuators <6> = 1 Single-channel convert mode TACH1 Minimum High Byte (Reg. 0x55) <7:5> Selects ADC channel for single-channel convert mod e Rev. 3 | Page 13 of 56 | www.onsemi.com

either limit can also generate SMBALERT interrupts. being updated while its two LSBs are being read, an d vice versa. a reading every 13 ms. The measurement itself takes 4 ms.

101 Remote 1 Temp

110 Local Temp

111 Remote 2 Temp

Figure 15. THERM Limit Operation

REV. A ADM1027 –17– SMBALERT , STATUS, AND MASK REGISTERS SMBALERT CONFIGURATION Pin 10 of the ADM1027 can be configured as either P WM2 or as an SMBALERT output. The SMBALERT output may be used to signal out-of-limit conditions as explained below. The default state of Pin 10 is PWM2. To configure Pin 1 0 as SMBALERT : Configuration Reg. 3 (Addr = 0x78), Bit 0 = 1 = SMBALERT Configuration Reg. 3 (Addr = 0x78), Bit 0 = 0 = PWM 2 = default LIMIT VALUES Associated with each measurement channel on the ADM 1027 are high and low limits. These can form the basis o f system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. Alter natively, SMBALERT interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. 8-BIT LIMITS The following is a list of 8-bit limits on the ADM1 027: Voltage Limit Registers Reg. 0x44 2.5 V Low Limit = 0x00 default Reg. 0x45 2.5 V High Limit = 0xFF default Reg. 0x46 VCCP Low Limit = 0x00 default Reg. 0x47 VCCP High Limit = 0xFF default Reg. 0x48 VCC Low Limit = 0x00 default Reg. 0x49 VCC High Limit = 0xFF default Reg. 0x4A 5 V Low Limit = 0x00 default Reg. 0x4B 5 V High Limit = 0xFF default Reg. 0x4C 12 V Low Limit = 0x00 default Reg. 0x4D 12 V High Limit = 0xFF default Temperature Limit Registers Reg. 0x4E Remote 1 Temp Low Limit = 0x81 default Reg. 0x4F Remote 1 Temp High Limit = 0x7F default Reg. 0x6A Remote 1 THERM Limit = 0x64 default Reg. 0x50 Local Temp Low Limit = 0x81 default Reg. 0x51 Local Temp High Limit = 0x7F default Reg. 0x6B Local THERM Limit = 0x64 default Reg. 0x52 Remote 2 Temp Low Limit = 0x81 default Reg. 0x53 Remote 2 Temp High Limit = 0x7F default Reg. 0x6C Remote 2 THERM Limit = 0x64 default 16-Bit Limits The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Since fans running underspeed or stalled are normal ly the only conditions of interest, only high limits exist for fan TACHs. Since fan TACH period is actually being measured, e xceeding the limit indicates a slow or stalled fan. Fan Limit Registers Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default Reg. 0x55 TACH1 Minimum High Byte = 0xFF default Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default Reg. 0x57 TACH2 Minimum High Byte = 0xFF default Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default Reg. 0x59 TACH3 Minimum High Byte = 0xFF default Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default Reg. 0x5B TACH4 Minimum High Byte = 0xFF default OUT-OF-LIMIT COMPARISONS The ADM1027 will measure all parameters in round-robin format and set the appropriate status bit for out-of-limit conditions. Comparisons are done differently depending on wheth er the measured value is being compared to a high or low l imit. HIGH LIMIT: > COMPARISON PERFORMED LOW LIMIT: < OR = COMPARISON PERFORMED Rev. 3 | Page 17 of 56 | www.onsemi.com

REV. A –18– ADM1027 ANALOG MONITORING CYCLE TIME The analog monitoring cycle begins when a 1 is writ ten to the start bit (Bit 0) of Configuration Register 1(Reg. 0x40). The ADC measures each analog input in turn and as each mea- surement is completed, the result is automatically stored in the appropriate value register. This round-robin monito ring cycle continues unless disabled by writing a 0 to Bit 0 o f Configura- tion Register 1. Since the ADC will normally be left to free-run in this manner, the time taken to monitor all the analog inputs wil l normally not be of interest as the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is /g121Four dedicated supply voltage inputs /g1213.3 V STBY or 5 V supply (V CC pin) /g121Local temperature /g121Two remote temperatures As mentioned previously, the ADC performs round-rob in con- versions and takes 11.38 ms for each voltage measur ement, 12 ms for a local temperature reading, and 25.5 ms for a remote temperature reading. The total monitoring cycle time for averaged voltag e and tem- perature monitoring is therefore nominally (5 /H11003 11.38) + 12 + (2 /H11003 25.5) = 120 ms Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any wa y. STATUS REGISTERS The results of limit comparisons are stored in Status Registers 1 and 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that c hannel. If a measurement is within limits, the correspondin g status register bit will be cleared to 0. If the measurement is out-of-limits, the corresponding status register bit will be set t o 1. The state of the various measurement channels may be polled by reading the status registers over the serial bus. W hen 1, Bit 7 (OOL) of Status Register 1 (Reg. 0x41) means that a n out-of- limit event has been flagged in Status Register 2. This means that the user need read only Status Register 2 when this bit is set. Alternatively, Pin 10 can be configured as an SMBALERT output. This will automatically notify the system superviso r of an out-of-limit condition. Reading the status register s clears the appropriate status bit as long as the error conditi on that caused the interrupt has cleared. Status register bits are “sticky.” Whenever a status bit gets set, indicating an out-o f-limit condition, it will remain set even if the event tha t caused it has gone away (until read). The only way to clear the s tatus bit is to read the status register after the event has gone away. Interrupt status mask registers (Reg. 0x74, 0x75) allow indiv idual inter- rupt sources to be masked from causing an SMBALERT . However, if one of these masked interrupt sources g oes out- of-limit, its associated status bit will get set in the interrupt status registers. STATUS REGISTER 1 (REG. 0x41) Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read. Bit 6 (R2T) = 1, Remote 2 temp high or low limit has been exceeded. Bit 5 (LT) = 1, Local temp high or low limit has been exceeded. Bit 4 (R1T) = 1, Remote 1 temp high or low limit has been exceeded. Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded. Bit 2 (V CC ) = 1, V CC high or low limit has been exceeded. Bit 1 (V CCP ) = 1, V CCP high or low limit has been exceeded. Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. STATUS REGISTER 2 (REG. 0x42) Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs. Bit 6 (D1) = 1, indicates an open or short on D2+/D2– inputs. Bit 5 (FAN4) = 1, indicates Fan 4 has dropped below mini- mum speed. Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below mini- mum speed. Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below mini- mum speed. Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below mini- mum speed. Bit 1 (OVT) = 1, indicates that a THERM overtemperature limit has been exceeded. Bit 0 (12 V) = 1, 12 V high or low limit has been exceeded. Rev. 3 | Page 18 of 56 | www.onsemi.com

REV. A –24– ADM1027 Fan Speed Measurement Registers The fan tachometer readings are 16-bit values consi sting of a 2-byte read from the ADM1027. Reg. 0x28 TACH1 Low Byte = 0x00 default Reg. 0x29 TACH1 High Byte = 0x00 default Reg. 0x2A TACH2 Low Byte = 0x00 default Reg. 0x2B TACH2 High Byte = 0x00 default Reg. 0x2C TACH3 Low Byte = 0x00 default Reg. 0x2D TACH3 High Byte = 0x00 default Reg. 0x2E TACH4 Low Byte = 0x00 default Reg. 0x2F TACH4 High Byte = 0x00 default Reading Fan Speed From the ADM1027 If fan speeds are being measured, this involves a 2 -register read for each measurement. The low byte should be read f irst. This causes the high byte to be frozen until both high a nd low byte registers have been read from. This prevents errone ous TACH readings. The fan tachometer reading registers report back th e number of 11.11 /H9262s period clocks (90 kHz oscillator) gated to the fa n speed counter, from the rising edge of the first fa n TACH pulse to the rising edge of the third fan TACH pulse (ass uming two pulses per revolution are being counted). Since the device is essentially measuring the fan TACH period, the high er the count value, the slower the fan is actually running . A 16-bit fan tachometer reading of 0xFFFF indicates that the fan either has stalled or is running very slowly (< 100 RPM). HIGH LIMIT: > COMPARISON PERFORMED Since actual fan TACH period is being measured, exc eeding a fan TACH limit by 1 will set the appropriate status bit and can be used to generate an SMBALERT . Fan Tach Limit Registers The fan TACH limit registers are 16-bit values cons isting of two bytes. Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default Reg. 0x55 TACH1 Minimum High Byte = 0xFF default Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default Reg. 0x57 TACH2 Minimum High Byte = 0xFF default Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default Reg. 0x59 TACH3 Minimum High Byte = 0xFF default Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default Reg. 0x5B TACH4 Minimum High Byte = 0xFF default Fan Speed Measurement Rate The fan TACH readings are normally updated once every second. The fast bit (Bit 3) of Configuration Register 3 (R eg. 0x78), when set, updates the fan TACH readings every 250 m s. If any of the fans are not being driven by a PWM ch annel but are powered directly from 5 V or 12 V, their associ ated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. Calculating Fan Speed Assuming a fan with 2 pulses/revolution (and 2 puls es/rev being measured), fan speed is calculated by: Fan Speed RPM Fan Tach Reading ( ) = ¥ ( ) 90 000 60 , where Fan Tach Reading = 16-bit fan tachometer reading. Example: TACH1 high byte (Reg. 0x29) = 0x17 TACH1 low byte (Reg. 0x28) = 0xFF What is Fan 1 speed in RPM? Fan 1 TACH reading = 0x17FF = 6143 decimal RPM = (f ¥ 60)/fan 1 TACH reading RPM = (90000 ¥ 60)/6143 Fan Speed = 879 RPM FAN PULSES PER REVOLUTION Different fan models can output either 1, 2, 3, or 4 TACH pulses per revolution. Once the number of fan TACH pulses has been determined, it can be programmed into the fan pulses per revolution register (Reg. 0x7B) for each fan. A lternatively, this register can be used to determine the number o r pulses/ revolution output by a given fan. By plotting fan s peed measure- ments at 100% speed with different pulses/rev setti ng, the smoothest graph with the lowest ripple determines t he correct pulses/rev value. Fan Pulses Per Revolution Register <1:0> FAN1 default = 2 pulses/rev <3:2> FAN2 default = 2 pulses/rev <5:4> FAN3 default = 2 pulses/rev <7:6> FAN4 default = 2 pulses/rev 00 = 1 pulse/rev 01 = 2 pulses/rev 10 = 3 pulses/rev 11 = 4 pulses/rev Rev. 3 | Page 24 of 56 | www.onsemi.com

REV. A ADM1027 –25– 2-Wire Fan Speed Measurements The ADM1027 is capable of measuring the speed of 2- wire fans, i.e., fans without TACH outputs. To do this, the fan must be interfaced as shown in the Fan Drive Circuitry s ection of the data sheet. In this case, the TACH inputs need to b e repro- grammed as analog inputs, AIN. CONFIGURATION REGISTER 2 (REG. 0x73) Bit 3 (AIN4) = 1, Pin 14 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 2 (AIN3) = 1, Pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 1 (AIN2) = 1, Pin 12 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 0 (AIN1) = 1, Pin 11 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. FAN SPIN-UP The ADM1027 has a unique fan spin-up function. It w ill spin the fan at 100% PWM duty cycle until two TACH pulse s are detected on the TACH input. Once two pulses have be en detected, the PWM duty cycle will go to the expecte d running value, e.g., 33%. The advantage of this is that fan s have dif- ferent spin-up characteristics and will take differ ent times to overcome inertia. The ADM1027 just runs the fans fa st enough to overcome inertia and will be quieter on spin-up than fans programmed to spin up for a given spin-up time. FAN START-UP TIMEOUT To prevent false interrupts being generated as a fa n spins up (since it is below running speed), the ADM1027 incl udes a fan start-up timeout function. This is the time limit a llowed for two TACH pulses to be detected on spin-up. For example, if 2 seconds fan start-up timeout is chosen, and no TACH pulses occur within 2 seconds of the start of spin-up, a f an fault is detected and flagged in the interrupt status regist ers. PWM1 CONFIGURATION (REG. 0x5C) <2:0> SPIN These bits control the start-up timeout for PWM1. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec PWM2 CONFIGURATION (REG. 0x5D) <2:0> SPIN These bits control the start-up timeout for PWM2. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec PWM3 CONFIGURATION (REG. 0x5E) <2:0> SPIN These bits control the start-up timeout for PWM3. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec Disabling Fan Start-Up Timeout Although fan start-up makes fan spin-ups much quieter than fixed-time spin-ups, the option is there to use fixed spin-up times. Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40) disables the spin-up for two TACH pulses. Instead, the fan will spin up for the fixed time as selected in registers 0x5C to 0x5E. Rev. 3 | Page 25 of 56 | www.onsemi.com

REV. A –26– ADM1027 MANUAL FAN SPEED CONTROL MODE PWM Logic State The PWM outputs can be programmed to be high for 10 0% duty cycle (noninverted) or low for 100% duty cycle (inverted). PWM1 Configuration (Reg. 0x5C) <4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM2 Configuration (Reg. 0x5D) <4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM3 Configuration (Reg. 0x5E) <4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM Drive Frequency The PWM drive frequency can be adjusted for the app lication. Registers 0x5F to 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61) <2:0> FREQ 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz Manual Fan Speed Control The ADM1027 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if you want t o change fan speed in software or want to adjust PWM duty cycle output for test purposes. Bits <7:5> of Registers 0x5C to 0x5E (PWM configuration) control the behavior of each PWM out put. PWM CONFIGURATION (REG. 0x5C to 0x5E) <7:5> BHVR 111 = Manual Mode Once under manual control, each PWM output may be manually updated by writing to Registers 0x30 to 0x32 (PWMx current duty cycle registers). Programming the PWM Current Duty Cycle Registers The PWM current duty cycle registers are 8-bit registers th at allow the PWM duty cycle for each output to be set anywhere from 0% to 100%. This allows the PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWM MIN register is given by Value decimal PWM MIN ( ) = 0 39 . Example 1: for a PWM duty cycle of 50%, Value (decimal) = 50/0.39 = 128 decimal Value = 128 decimal or 80 hex. Example 2: for a PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85 decimal Value = 85 decimal or 54 hex. PWM Duty Cycle Registers Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% default) Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% default) Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% default) By reading the PWMx current duty cycle registers, y ou can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. Rev. 3 | Page 26 of 56 | www.onsemi.com

REV. A –28– ADM1027 Step 1 Determine the Hardware Configuration Essentially this means choosing whether to use Pin 10 as a PWM2 output or as an SMBALERT output and deciding which SMBus address is to be used. To set Pin 10 as SMBALERT , set Bit 0 of Configuration Register 3 (Addr = 0x78) equal to 1 . The default state is PWM2, where this bit equals 0. It also refers to the layout recommendations of the ADM1027 on a motherboard, for example. ADM1027 Placement Considerations Motherboards are electrically noisy environments, and care must be taken to protect the analog inputs from noise, p articularly the D+/D – lines of a remote diode sensor. The following precautions should be taken: 1. Place the ADM1027 as close as possible to the rem ote sensing diode. Provided that the worst noise sources such a s clocks and data/address buses are avoided, this distance c an be 4 inches to 8 inches. 2. Route the D+ and D – tracks close together, in parallel, with grounded guard tracks on each side. Provide a groun d plane under the tracks if possible. Do NOT run the D+/D – lines in different directions. 3. Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. 4. Try to minimize the number of copper/solder joint s, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ an d D – path and at the same temperature. Avoid routing D+/ D – on multiple layers or through vias if possible. Thes e increase series resistance that will cause temperature error . 5. Place a 0.1 mF supply bypass capacitor close to the ADM1027. 6. If the distance to the remote sensor is more than 8 inches, the use of shielded twisted pair cable is recommend ed. This will work up to 100 feet. Connect the twisted pair to D+/D – and the shield to GND close to the ADM1027. Leave t he remote end of the shield unconnected to avoid groun d loops. Because the measurement technique uses switched cur rent sources, excessive cable (adds resistance) and/or filter capacitance can affect the measurement. A 1 W series resistance introduces about 0.8 oC error. Rev. 3 | Page 28 of 56 | www.onsemi.com

at the fastest speed calculated by multiple tempera ture channels. channels and the three PWM outputs. a temperature measurement channel to a PWM output. trol one PWM output based on multiple temperature c hannels. or local temp exceeds 45 /g114C. 011 = PWMx runs full-speed (default). writable and control the PWM outputs. Figure 28. Assigning Temperature Channels to Fan Ch annels

30 /g114C for VRM temperature, and 40 /g114C for processor temperature. the temperature be below T MIN . temperature is below T MIN – T HYST . temperature is below T MIN – T HYST . temperature is below T MIN – T HYST . Figure 29. Understanding T MIN Parameter

REV. A ADM1027 –33– Example: Calculate TMAX , given TMIN = 30 /g114C, TRANGE = 40 /g114C, and PWMMIN = 33% duty cycle = 85 decimal T T MaxD C MinD C T MAX MIN RANGE = + - ( ) ¥. . . . 170 T C C MAX = /g114+ - ( ) ¥ /g11430 100 33 40 170 % % T C C MAX = /g114+ - ( ) ¥ /g11430 255 85 40 170 TMAX = 70 /g114C ( effective T RANGE = 40 /g114C) Example: Calculate TMAX , given TMIN = 30 /g114C, TRANGE = 40 /g114C, and PWMMIN = 50% duty cycle = 128 decimal T T MaxD C MinD C T MAX MIN RANGE = + - ( ) ¥. . . . 170 T C C MAX = /g114+ - ( ) ¥ /g11430 100 50 40 170 % % T C C MAX = /g114+ - ( ) ¥ /g11430 255 128 40 170 TMAX = 60 /g114C ( effective T RANGE = 30 /g114C) Selecting a T RANGE Slope The T RANGE value can be selected for each temperature channel: Remote 1, Local and Remote 2 Temp. Bits <7:4> (TRAN GE) of Registers 0x5F to 0x61 define the T RANGE value for each temperature channel. Bits <7:4> * T RANGE (/g114C) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 * Register 0x5F configures remote 1 T RANGE . Register 0x60 configures local T RANGE . Register 0x61 configures remote 2 T RANGE . Rev. 3 | Page 33 of 56 | www.onsemi.com

system operating conditions. full speed) by setting T THERM to 70 /g114C. THERM hysteresis is 4 /g114C. Figure 35. Understanding How T THERM Relates to Automatic Fan Control

temperature is below T MIN – T HYST . temperature is below T MIN – T HYST . temperature is below T MIN – T HYST . Figure 36. The T HYST Value Applies to Fan On/Off Hysteresis and THERM H ysteresis

the core voltage of the processor will be lowered i n these states. SMBALERT s during the low power state. shows the signals that are exercised in the XOR tree test mode. XOR tree test enable register (Reg. 0x6F). Figure 43. XOR Tree Test

REV. A –40– ADM1027 Table IV. ADM1027 Registers Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable? 0x20 R 2.5 V Reading 9 8 7 6 5 4 3 2 0x00 0x21 R V CCP Reading 9 8 7 6 5 4 3 2 0x00 0x22 R V CC Reading 9 8 7 6 5 4 3 2 0x00 0x23 R 5 V Reading 9 8 7 6 5 4 3 2 0x00 0x24 R 12 V Reading 9 8 7 6 5 4 3 2 0x00 0x25 R Remote 1 Temperature 9 8 7 6 5 4 3 2 0x80 0x26 R Local Temperature 9 8 7 6 5 4 3 2 0x80 0x27 R Remote 2 Temperature 9 8 7 6 5 4 3 2 0x80 0x28 R TACH1 Low Byte 7 6 5 4 3 2 1 0 0x00 0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00 0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00 0x2C R TACH3 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2D R TACH3 High Byte 15 14 13 12 11 10 9 8 0x00 0x2E R TACH4 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2F R TACH4 High Byte 15 14 13 12 11 10 9 8 0x00 0x30 R/W PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x31 R/W PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x32 R/W PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x27 0x3E R Company ID Number 7 6 5 4 3 2 1 0 0x41 0x3F R Revision Number VER VER VER VER STP STP STP STP 0x60 0x40 R/W Configuration Register 1 V CC TODIS FSPDIS V ¥ I FSPD RDY LOCK STRT 0x00 Yes 0x41 R Interrupt Status Register 1 OOL R2T LT R1T 5 V V CC VCCP 2.5 V 0x00 0x42 R Interrupt Status Register 2 D2 D1 5 FAN3 FAN2 FAN1 OV T 12 V 0x00 0x43 R/W VID Register 7 6 5 VID4 VID3 VID2 VID1 VID0 0xFF 0x44 R/W 2.5 V Low Limit 7 6 5 4 3 2 1 0 0x00 0x45 R/W 2.5 V High Limit 7 6 5 4 3 2 1 0 0xFF 0x46 R/W V CCP Low Limit 7 6 5 4 3 2 1 0 0x00 0x47 R/W V CCP High Limit 7 6 5 4 3 2 1 0 0xFF 0x48 R/W V CC Low Limit 7 6 5 4 3 2 1 0 0x00 0x49 R/W V CC High Limit 7 6 5 4 3 2 1 0 0xFF 0x4A R/W 5 V Low Limit 7 6 5 4 3 2 1 0 0x00 0x4B R/W 5 V High Limit 7 6 5 4 3 2 1 0 0xFF 0x4C R/W 12 V Low Limit 7 6 5 4 3 2 1 0 0x00 0x4D R/W 12 V High Limit 7 6 5 4 3 2 1 0 0xFF 0x4E R/W Remote 1 Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x4F R/W Remote 1 Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x50 R/W Local Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x51 R/W Local Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x52 R/W Remote 2 Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x53 R/W Remote 2 Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x54 R/W TACH1 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF 0x55 R/W TACH1 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF 0x56 R/W TACH2 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF 0x57 R/W TACH2 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF 0x58 R/W TACH3 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF 0x59 R/W TACH3 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF 0x5A R/W TACH4 Minimum Low Byte 7 6 5 4 3 2 1 0 0xFF 0x5B R/W TACH4 Minimum High Byte 15 14 13 12 11 10 9 8 0xFF Rev. 3 | Page 40 of 56 | www.onsemi.com

REV. A ADM1027 –41– Table IV. ADM1027 Registers (continued) Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable? 0x5C R/W PWM1 Configuration Register BHVR BHVR BHVR INV 3 S PIN SPIN SPIN 0x62 Yes 0x5D R/W PWM2 Configuration Register BHVR BHVR BHVR INV 3 S PIN SPIN SPIN 0x62 Yes 0x5E R/W PWM3 Configuration Register BHVR BHVR BHVR INV 3 S PIN SPIN SPIN 0x62 Yes 0x5F R/W Remote 1 T RANGE /PWM 1 Freq RANGE RANGE RANGE RANGE 3 FREQ FREQ FREQ 0xC4 Yes 0x60 R/W Local T RANGE /PWM 2 Freq RANGE RANGE RANGE RANGE 3 FREQ FREQ FREQ 0xC4 Yes 0x61 R/W Remote 2 T RANGE /PWM 3 Freq RANGE RANGE RANGE RANGE 3 FREQ FREQ FREQ 0xC4 Yes 0x62 R/W Enhance Acoustics Reg 1 MIN3 MIN2 MIN1 4 EN1 ACOU A COU ACOU 0x00 Yes 0x63 R/W Enhance Acoustics Reg 2 EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0x00 Yes 0x64 R/W PWM1 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 Yes 0x65 R/W PWM2 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 Yes 0x66 R/W PWM3 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 Yes 0x67 R/W Remote 1 Temp T MIN 7 6 5 4 3 2 1 0 0x5A Yes 0x68 R/W Local Temp T MIN 7 6 5 4 3 2 1 0 0x5A Yes 0x69 R/W Remote 2 Temp T MIN 7 6 5 4 3 2 1 0 0x5A Yes 0x6A R/W Remote 1 THERM Limit 7 6 5 4 3 2 1 0 0x64 Yes 0x6B R/W Local THERM Limit 7 6 5 4 3 2 1 0 0x64 Yes 0x6C R/W Remote 2 THERM Limit 7 6 5 4 3 2 1 0 0x64 Yes 0x6D R/W Remote 1, Local Hysteresis HYSR1 HYSR1 HYSR1 HYS R1 HYSL HYSL HYSL HYSL 0x44 Yes 0x6E R/W Remote 2 Temp Hysteresis HYSR2 HYSR2 HYSR2 HYSR2 RES RES RES RES 0x40 Yes 0x6F R/W XOR Tree Test Enable RES RES RES RES RES RES RES XEN 0x00 Yes 0x70 R/W Remote 1 Temperature Offset 7 6 5 4 3 2 1 0 0x00 Yes 0x71 R/W Local Temperature Offset 7 6 5 4 3 2 1 0 0x00 Yes 0x72 R/W Remote 2 Temperature Offset 7 6 5 4 3 2 1 0 0x00 Yes 0x73 R/W Configuration Register 2 7 CONV ATTN AVG AIN4 AIN3 AIN2 AIN1 0x00 Yes 0x74 R/W Interrupt Mask 1 Register OOL R2T LT R1T 5 V V CC VCCP 2.5 V 0x00 0x75 R/W Interrupt Mask 2 Register D2 D1 5 FAN3 FAN2 FAN1 OV T 12 V 0x00 0x76 R/W Extended Resolution 1 5 V 5 V V CC VCC VCCP VCCP 2.5 V 2.5 V 0x00 0x77 R/W Extended Resolution 2 TDM2 TDM2 LTMP LTMP TDM1 TDM 1 12 V 12 V 0x00 0x78 R/W Configuration Register 3 DC4 DC3 DC2 DC1 FAST BOOS T 1 ALERT 0x00 Yes 0x7B R/W Fan Pulses per Revolution FAN4 FAN4 FAN3 FAN3 FAN 2 FAN2 FAN1 FAN1 0x55 Rev. 3 | Page 41 of 56 | www.onsemi.com

REV. A –42– ADM1027 Table V. Voltage Reading Registers (Power-On Default = 0x00) Register Address R/W Description 0x20 Read-Only 2.5 V Reading (8 MSBs of reading). 0x21 Read-Only V CCP Reading. Holds processor core voltage measurement (8 MSBs of reading). 0x22 Read-Only V CC Reading. Measures V CC through the V CC pin (8 MSBs of reading). 0x23 Read-Only 5 V Reading (8 MSBs of reading). 0x24 Read-Only 12 V Reading (8 MSBs of reading). If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution register is rea d, the associated MSB reading registers are frozen until read. Both the extended resolution register and the MSB registers are froze n. Table VI. Temperature Reading Registers (Power-On Default = 0x80) Register Address R/W Description 0x25 Read-Only Remote 1 Temperature Reading * (8 MSBs of reading). 0x26 Read-Only Local Temperature Reading (8 MSBs of r eading). 0x27 Read-Only Remote 2 Temperature Reading * (8 MSBs of reading). These temperature readings are in twos complement f ormat. *Note that a reading of 0x80 in a temperature readin g register indicates a diode fault (open or short) on that channel. If the extended resolution bits of these readings are also being read, the extended resolution regist ers (Reg. 0x76, 0x77) should be read first. Once th e extended resolution register is read, all associa ted MSB reading registers are frozen until read. Both the extended resolution register and the MSB registers are froze n. Table VII. Fan Tachometer Reading Registers (Power-On Default = 0x00) Register Address R/W Description 0x28 Read-Only TACH1 Low Byte 0x29 Read-Only TACH1 High Byte 0x2A Read-Only TACH2 Low Byte 0x2B Read-Only TACH2 High Byte 0x2C Read-Only TACH3 Low Byte 0x2D Read-Only TACH3 High Byte 0x2E Read-Only TACH4 Low Byte 0x2F Read-Only TACH4 High Byte These registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan tach pulses (default = 2). The number of tach p ulses used to count can be changed using the fan pu lses per revolution register (Reg. 0x7B). This allows the fan speed to be accura tely measured. Since a valid fan tachometer reading requires that two bytes are read; the low byte MUST be read first. Both the low and high bytes are then frozen until read. At powe r-on, these registers contain 0x0000 until such time as the first valid fan tach measurement is read in to these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is: 1. Stalled or Blocked (object jamming the fan) 2. Failed (internal circuitry destroyed) 3. Not Populated (The ADM1027 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should be set to 0xFFFF. ) 4. 2-Wire Instead of 3-Wire Fan Rev. 3 | Page 42 of 56 | www.onsemi.com

REV. A ADM1027 –43– Table VIII. Current PWM Duty Cycle Registers (Power-On Default = 0xFF) Register Address R/W Description 0x30 Read/Write PWM1 Current Duty Cycle (0% to 100% d uty cycle = 0x00 to 0xFF) 0x31 Read/Write PWM2 Current Duty Cycle (0% to 100% d uty cycle = 0x00 to 0xFF) 0x32 Read/Write PWM3 Current Duty Cycle (0% to 100% d uty cycle = 0x00 to 0xFF) These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADM1027 reports the PWM duty cycles back through these regi sters. The PWM duty cycle values will vary accordin g to temperature in automatic fan speed control mode. During fan startu p, these registers report back 0x00. In software mo de, the PWM duty cycle outputs can be set to any duty cycle value by writi ng to these registers. Table IX. Register 0x40 – Configuration Register 1 (Power-On Default = 0x00) Bit Name R/W Description <0> STRT Read/Write Logic 1 enables monitoring and PWM control outputs based on the limit settings pro- grammed. Logic 0 disables monitoring and PWM contro l based on the default power-up limit settings. Note that the limit values programm ed are preserved even if a LOGIC 0 is written to this bit and the default settings are en abled. This bit becomes read-only and cannot be changed once Bit 1 (lock bit) has been wr itten. All limit registers should be programmed by BIOS before setting this bit to 1 (lo ckable). <1> LOCK Write Once Logic 1 locks all limit values to their current settings. Once this bit is set, all l ockable registers become read-only and cannot be modified until the ADM1027 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings (lockable). <2> RDY Read-Only This bit gets set to 1 by the ADM102 7 to indicate that the device is fully powered up and ready to begin systems monitoring. <3> FSPD Read/Write When set to 1, this runs all fans at full speed. Power-on default = 0. This bit does not get locked at any time. <4> V ¥ I Read/Write BIOS should set this bit to 1 when the ADM1027 is configured to measure current from an ADI ADOPT ® VRM controller and measure the CPU’s core voltage. This will allow monitoring software to display CPU watts usag e (lockable). <5> FSPDIS Read/Write Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs will go high for the entire fan spin-up timeout selected. <6> TODIS Read/Write When this bit is set to 1, the SM Bus timeout feature is disabled. This allows the ADM1027 to be used with SMBus controllers that cannot handl e SMBus timeouts (lockable). <7> V CC Read/Write When this bit is set to 1, the ADM1027 re scales its V CC pin to measure a 5 V supply. If this bit is 0, the ADM1027 measures V CC as a 3.3 V supply (lockable). Rev. 2 | Page 3 of 56 | www.onsemi.com

Table X. Register 0x41 – Interrupt Status Register 1 (Power-On Default = 0x00) Bit Name Read/Write Description <0> 2.5 V Read-Only A 1 indicates the 2.5 V high or low limit has been exceeded. This bit is cl eared on a read of the status register only if the error condition has subsided. <1> V CCP Read-Only A 1 indicates the V CCP high or low limit has been exceeded. This bit is cl eared on a read of the status register only if the error condition has subsided. <2> V CC Read-Only A 1 indicates the V CC high or low limit has been exceeded. This bit is c leared on a read of the status register only if the error condition has subsided. <3> 5 V Read-Only A 1 indicates the 5 V high or low li mit has been exceeded. This bit is cleared on a rea d of the status register only if the error condition has subsided. <4> R1T Read-Only A 1 indicates the Remote 1 low or hi gh temp limit has been exceeded. This bit is cleared on a read of the status register only if th e error condition has subsided. <5> LT Read-Only A 1 indicates the local low or high t emp limit has been exceeded. This bit is cleared on a read of the status register only if the error con dition has subsided. <6> R2T Read-Only A 1 indicates the Remote 2 low or hi gh temperature limit has been exceeded. This bit is cleared on a read of the status register only if th e error condition has subsided. <7> OOL Read-Only A 1 indicates that an out-of-limit e vent has been latched in Status Register 2. This bi t is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit. This saves the need to read Status Register 2 every interrupt or polling cycle. Table XI. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00) Bit Name Read/Write Description <0> 12 V Read-Only A 1 indicates the 12 V high or low limit has been exceeded. This bit is cleared on a r ead of the status register only if the error condition has subsided. <1> OVT Read-Only A 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a read of the status register when the temperature drops below THERM – 4 /g114C <2> FAN1 Read-Only A 1 indicates that Fan 1 has droppe d below minimum speed or has stalled. This bit is NOT set when the PWM 1 output is off. <3> FAN2 Read-Only A 1 indicates that Fan 2 has droppe d below minimum speed or has stalled. This bit is NOT set when the PWM 2 output is off. <4> FAN3 Read-Only A 1 indicates that Fan 3 has droppe d below minimum speed or has stalled. This bit is NOT set when the PWM 3 output is off. <5> FAN4 Read-Only A 1 indicates that Fan 4 has droppe d below minimum speed or has stalled. This bit is NOT set when the PWM 3 output is off. <6> D1 Read-Only A 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. <7> D2 Read-Only A 1 indicates either an open or short circuit on the Thermal Diode 2 inputs. Rev. 3 | Page 44 of 56 | www.onsemi.com

Table XII. Register 0x43 – VID Register (Power-On D efault = 0x00 ) Bit Name R/W Description <4:0> VID[4:0] Read-Only The VID[4:0] inputs from the CPU to indicate the expected processor core voltage . On power-up, these bits reflect the state of the VID p ins, even if monitoring is not enabled. <7:5> Reserved Read-Only Reserved for future use. Table XIII. Voltage Limit Registers Register Address R/W Description Power-On Default 0x44 Read/Write 2.5 V Low Limit 0x00 0x45 Read/Write 2.5 V High Limit 0xFF 0x46 Read/Write V CCP Low Limit 0x00 0x47 Read/Write V CCP High Limit 0xFF 0x48 Read/Write V CC Low Limit 0x00 0x49 Read/Write V CC High Limit 0xFF 0x4A Read/Write 5 V Low Limit 0x00 0x4B Read/Write 5 V High Limit 0xFF 0x4C Read/Write 12 V Low Limit 0x00 0x4D Read/Write 12 V High Limit 0xFF Setting the Configuration Register 1 lock bit has n o effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit ( > comparison). Low Limits: An interrupt is generated when a value is equal to or below its low limit ( £ comparison). Table XIV. Temperature Limit Registers Register Address R/W Description Power-On Default 0x4E Read/Write Remote 1 Temperature Low Limit 0x81 0x4F Read/Write Remote 1 Temperature High Limit 0x7F 0x50 Read/Write Local Temperature Low Limit 0x81 0x51 Read/Write Local Temperature High Limit 0x7F 0x52 Read/Write Remote 2 Temperature Low Limit 0x81 0x53 Read/Write Remote 2 Temperature High Limit 0x7F Exceeding any of these temperature limits by 1 oC will cause the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock bit has no effect on these registers. High Limits: An interrupt is generated when a value exceeds its high limit ( > comparison). Low Limits: An interrupt is generated when a value is equal to or below its low limit ( £ comparison). Rev. 3 | Page 45 of 56 | www.onsemi.com

REV. A –46– ADM1027 Table XV. Fan Tachometer Limit Registers Register Address R/W Description Power-On Default 0x54 Read/Write TACH 1 Minimum Low Byte 0xFF 0x55 Read/Write TACH 1 Minimum High Byte 0xFF 0x56 Read/Write TACH 2 Minimum Low Byte 0xFF 0x57 Read/Write TACH 2 Minimum High Byte 0xFF 0x58 Read/Write TACH 3 Minimum Low Byte 0xFF 0x59 Read/Write TACH 3 Minimum High Byte 0xFF 0x5A Read/Write TACH 4 Minimum Low Byte 0xFF 0x5B Read/Write TACH 4 Minimum High Byte 0xFF Exceeding any of the TACH limit registers by 1 indi cates that the fan is running too slowly or has sta lled. The appropriate status bit will be set in Interrupt Status Register 2 to indic ate the fan failure. Setting the Configuration Regi ster 1 lock bit has no effect on these registers. Table XVI. PWM Configuration Registers Register Address R/W Description Power-On Default 0x5C Read/Write PWM1 Configuration 0x62 0x5D Read/Write PWM2 Configuration 0x62 0x5E Read/Write PWM3 Configuration 0x62 Bit Name Read/Write Description <2:0> SPIN Read/Write These bits control the startup t imeout for PWMx. The PWM output stays high until tw o (Fan Startup valid TACH rising edges are seen from t he fan. If there is not a valid TACH signal during Timeout) the fan TACH measurement directly after the fan startup timeout period, then the TACH measurement will read 0xFFFF and Status Register 2 will reflect the fan fault. If the TACH minimum high and low byte contains 0xFFFF or 0x0000, then the Status Register 2 bit will not be set, even if the fan has not star ted. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec Note: Do not program 100. <3> Reserved Read-Only Reserved for future use. <4> INV Read/Write This bit inverts the PWM output. Th e default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1, inverts the PWM output, so 100% duty cycle corresponds to a logic low output. <7:5> BHVR Read/Write These bits assign each fan to a particular temperature sensor for localized cooling . 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = Local temperature controls PWMx (automatic fa n control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs full speed (default). 100 = PWMx disabled. 101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = Fastest speed calculated by all three tempera tures controls PWMx. 111 = Manual mode. PWM duty cycle registers (Reg. 0 x30 to 0x32) become writable. These registers become read-only when the configura tion register 1 lock bit is set to 1. Any subsequen t attempts to write to these registers will fail. Rev. 3 | Page 46 of 56 | www.onsemi.com

REV. A ADM1027 –47– Table XVII. TEMP T RANGE /PWM Frequency Registers Register Address R/W Description Power-On Default 0x5F Read/Write Remote 1 T RANGE /PWM 1 Frequency 0xC4 0x60 Read/Write Local Temperature T RANGE /PWM 2 Frequency 0xC4 0x61 Read/Write Remote 2 T RANGE /PWM 3 Frequency 0xC4 Bit Name Read/Write Description <2:0> FREQ Read/Write These bits control the PWMx freq uency. 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz <3> Reserved Read/Write Reserved for future use. <7:4> RANGE Read/Write These bits determine the PWM du ty cycle versus temperature slope for automatic fan control. 0000 = 2 oC 0001 = 2.5 oC 0010 = 3.33 oC 0011 = 4 oC 0100 = 5 oC 0101 = 6.67 oC 0110 = 8 oC 0111 = 10 oC 1000 = 13.33 oC 1001 = 16 oC 1010 = 20 oC 1011 = 26.67 oC 1100 = 32 oC (default) 1101 = 40 oC 1110 = 53.33 oC 1111 = 80 oC These registers become read-only when the Configura tion Register 1 lock bit is set. Any further attemp ts to write to these registers will have no effect. Rev. 3 | Page 47 of 56 | www.onsemi.com

REV. A –48– ADM1027 Table XVIII. Register 0x62 – Enhance Acoustics Register 1 (Power-On Default = 0x00) Bit Name R/W Description <2:0> ACOU Read-Only These bits select the ramp rate a pplied to the PWM1 output. Instead of PWM1 jump- ing instantaneously to its newly calculated speed, PWM1 will ramp gracefully at the rate determined by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output. Time slot increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 1.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec <3> EN1 Read/Write When this bit is 1, acoustic enhanc ement is enabled on PWM1 output. When acoustic enhancement is enabled, fan spin-up time s hould be disabled. <4> Reserved Read-Only Reserved for future use. <5> MIN1 Read/Write When the ADM1027 is in automatic f an control mode, this bit defines whether PWM 1 is off (0% duty cycle) or at PWM 1 minimum duty cycle when the controlling temperature is below its T MIN – hysteresis value. 0 = 0% duty cycle below T MIN – hysteresis 1 = PWM 1 minimum duty cycle below T MIN – hysteresis <6> MIN2 Read/Write When the ADM1027 is in automatic f an speed control mode, this bit defines whether PWM 2 is off (0% duty cycle) or at PWM 2 minimum du ty cycle when the controlling temperature is below its T MIN – hysteresis value. 0 = 0% duty cycle below T MIN – hysteresis 1 = PWM 2 minimum duty cycle below T MIN – hysteresis <7> MIN3 Read/Write When the ADM1027 is in automatic f an speed control mode, this bit defines whether PWM 3 is off (0% duty cycle) or at PWM 3 minimum du ty cycle when the controlling temperature is below its T MIN – hysteresis value. 0 = 0% duty cycle below T MIN – hysteresis 1 = PWM 3 minimum duty cycle below T MIN – hysteresis This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Rev. 3 | Page 48 of 56 | www.onsemi.com

REV. A ADM1027 –49– Table XIX. Register 0x63 – Enhance Acoustics Register 2 (Power-On Default = 0x00) Bit Name R/W Description <2:0> ACOU3 Read/Write These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumpin g instantaneously to its newly calculated speed, PWM3 will ramp gracefully at the rate determined by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output. Time slot increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec <3> EN3 Read/Write When this bit is 1, acoustic enhanc ement is enabled on PWM3 output. When acoustic enhancement is enabled, fan spin-up time should be disabled. <6:4> ACOU2 Read/Write These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumpin g instantaneously to its newly calculated speed, PWM2 will ramp gracefully at the rate determined by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output. Time slot increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec <7> EN2 Read/Write When this bit is 1, acoustic enhanc ement is enabled on PWM2 output. When acoustic enhancement is enabled, fan spin-up time should be disabled. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Rev. 3 | Page 49 of 56 | www.onsemi.com

REV. A –50– ADM1027 Table XX. PWM Minimum Duty Cycle Registers Register Address R/W Description Power-On Default 0x64 Read/Write PWM1 Minimum Duty Cycle 0x80 (50% duty cycle) 0x65 Read/Write PWM2 Minimum Duty Cycle 0x80 (50% duty cycle) 0x66 Read/Write PWM3 Minimum Duty Cycle 0x80 (50% duty cycle) Bit Name Read/Write Description <7:0> PWM Duty Read/Write These bits define the PWM MIN duty cycle for the PWMx output. 0x00 = 0% duty cycle (fan off) 0x40 = 25% duty cycle 0x80 = 50% duty cycle 0xFF = 100% duty cycle (fan full speed) These registers become read-only when the ADM1027 i s in automatic fan control mode. Table XXI. T MIN Registers Register Address R/W Description Power-On Default 0x67 Read/Write Remote 1 Temperature T MIN 0x5A (90 oC) 0x68 Read/Write Local Temperature T MIN 0x5A (90 oC) 0x69 Read/Write Remote 2 Temperature T MIN 0x5A (90 oC) These are the T MIN registers for each temperature channel. When the t emperature measured exceeds T MIN , the appropriate fan will run at minimum speed and increase with temperature according to T RANGE . These registers become read-only when the Configura tion Register 1 lock bit is set. Any further attemp ts to write to these registers will have no effect. Table XXII. Therm Limit Registers Register Address R/W Description Power-On Default 0x6A Read/Write Remote 1 THERM Limit 0x64 (100 oC) 0x6B Read/Write Local THERM Limit 0x64 (100 oC) 0x6C Read/Write Remote 2 THERM Limit 0x64 (100 oC) If any temperature measured exceeds its THERM limit , all PWM outputs will drive their fans at 100% dut y cycle. This is a fail-safe mechanism incorporated to cool the system in the ev ent of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output wil l remain at 100% until the temperature drops below THERM limit – 4 /g114C . These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers will have no effect. Table XXIII. Temperature Hysteresis Registers Register Address R/W Description Power-On Default 0x6D Read/Write Remote 1, Local Temperature Hysteresi s 0x44 0x6E Read/Write Remote 2 Temperature Hysteresis 0x40 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature cha nnel. Once the temperature for that channel falls below its T MIN value, the fan will remain running at PWM MIN duty cycle until the temperature = T MIN – hysteresis. Up to 15 oC of hysteresis may be assigned to any temperature channel. Setting the hysteresis value lower than 4 oC will cause the fan to switch on and off regularly when the temperature is close to T MIN . These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to these registers will have no effect. Rev. 3 | Page 50 of 56 | www.onsemi.com

REV. A ADM1027 –51– Table XXIV. XOR Tree Test Enable Register Address R/W Description Power-On Default 0x6F Read/Write XOR Tree Test Enable Register 0x00 <0> XEN If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit removes the device from the XOR tree test mode. <7:1> Reserved Unused. Do not write to these bits. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Table XXV. Remote 1 Temperature Offset Register Address R/W Description Power-On Default 0x70 Read/Write Remote 1 Temperature Offset 0x00 <7:0> Read/Write Allows a twos complement offset valu e to be automatically added to or subtracted from the Remote 1 temperature reading. This is to compen sate for any inherent system offsets such as PCB trace resistance. LSB value = 1 oC. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Table XXVI. Local Temperature Offset Register Address R/W Description Power-On Default 0x71 Read/Write Local Temperature Offset 0x00 <7:0> Read/Write Allows a twos complement offset valu e to be automatically added to or subtracted from the local temperature reading. LSB value = 1 oC. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Table XXVII. Remote 2 Temperature Offset Register Address R/W Description Power-On Default 0x72 Read/Write Remote 2 Temperature Offset 0x00 <7:0> Read/Write Allows a twos complement offset valu e to be automatically added to or subtracted from the Remote 2 temperature reading. This is to compen sate for any inherent system off- sets such as PCB trace resistance. LSB value = 1 oC. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Rev. 3 | Page 51 of 56 | www.onsemi.com

REV. A –52– ADM1027 Table XXVIII. Register 0x73 – Configuration Register 2 (Power-On Default = 0x00) Bit Name R/W Description 0 AIN1 Read/Write AIN1 = 0, speed of 3-wire fans measu red using the TACH output from the fan. AIN1 = 1, Pin 11 is reconfigured to measure the spe ed of 2-wire fans using an external sensing resistor and coupling capacitor. 1 AIN2 Read/Write AIN2 = 0, speed of 3-wire fans measu red using the TACH output from the fan. AIN2 = 1, Pin 12 is reconfigured to measure the spe ed of 2-wire fans using an external sensing resistor and coupling capacitor. 2 AIN3 Read/Write AIN3 = 0, speed of 3-wire fans measu red using the TACH output from the fan. AIN3 = 1, Pin 9 is reconfigured to measure the spee d of 2-wire fans using an external sensing resistor and coupling capacitor. 3 AIN4 Read/Write AIN4 = 0, speed of 3-wire fans measu red using the TACH output from the fan. AIN4 = 1, Pin 14 is reconfigured to measure the spe ed of 2-wire fans using an external sensing resistor and coupling capacitor. 4 AVG Read/Write AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster. 5 ATTN Read/Write ATTN = 1, the ADM1027 removes the at tenuators from the 2.5 V, V CCP , 5 V, and 12 V inputs. The inputs can be used for other funct ions such as connecting up external sensors. 6 CONV Read/Write CONV = 1, the ADM1027 is put into a single-channel ADC conversion mode. In this mode, the ADM1027 can be made to read conti nuously from one input only, e.g., Remote 1 temperature. It is also possible to start ADC conversions using an external clock on Pin 11 by setting Bit 2 of Test R egister 2 (Reg. 0x7F). This mode could be useful if, for example, the user wanted to characterize/profile CPU temperature quickly. The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1 minimum high byte register (0x55). Bits <7:5> Reg. 0x55 Channel Selected \` 000 2.5 V 001 V CCP 010 V CC (3.3 V) 011 5 V 100 12 V

7 Reserved Read/Write Reserved for future use

This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Rev. 3 | Page 52 of 56 | www.onsemi.com

REV. A ADM1027 –53– Table XXIX. Register 0x74 – Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00) Bit Name R/W Description 0 2.5 V Read/Write A 1 masks SMBALERT for out-of-limit conditions on the 2.5 V channel. 1 V CCP Read/Write A 1 masks SMBALERT for out-of-limit conditions on the V CCP channel. 2 V CC Read/Write A 1 masks SMBALERT for out-of-limit conditions on the V CC channel. 3 5 V Read/Write A 1 masks SMBALERT for out-of-limit conditions on the 5 V channel. 4 R1T Read/Write A 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temper ature channel. 5 LT Read/Write A 1 masks SMBALERT for out-of-limit conditions on the local temperatu re channel. 6 R2T Read/Write A 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temper ature channel. 7 OOL Read/Write This bit needs to be set to 1 to allo w masking in the Interrupt Mask Register 2. If this bit is not set to 1, then setting a bit in Mask Registe r 2 will have no effect. Table XXX. Register 0x75 – Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00) Bit Name R/W Description 0 12 V Read/Write A 1 masks SMBALERT for out-of-limit conditions on the 12 V channel. 1 OVT Read-Only A 1 masks SMBALERT for overtemperature THERM conditions. 2 FAN1 Read/Write A 1 masks SMBALERT for a Fan 1 fault. 3 FAN2 Read/Write A 1 masks SMBALERT for a Fan 2 fault. 4 FAN3 Read/Write A 1 masks SMBALERT for a Fan 3 fault. 5 FAN4 Read/Write A 1 masks SMBALERT for a Fan 4 fault. 6 D1 Read/Write A 1 masks SMBALERT for a diode open or short on Remote 1 channel. 7 D2 Read/Write A 1 masks SMBALERT for a diode open or short on Remote 2 channel. Table XXXI. Register 0x76 – Extended Resolution Register 1 Bit Name R/W Description <3:2> V CCP Read-Only V CCP LSBs. Holds the 2 LSBs of the 10-bit V CCP measurement. <5:4> V CC Read-Only V CC LSBs. Holds the 2 LSBs of the 10-bit V CC measurement. <7:6> 5 V Read-Only 5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement. If this register is read, this register and the reg isters holding the MSB of each reading are frozen u ntil read. Table XXXII. Register 0x77 – Extended Resolution Register 2 Bit Name R/W Description <1:0> 12 V Read-Only 12 V LSBs. Holds the 2 LSBs of th e 10-bit 12 V measurement. <3:2> TDM1 Read-Only Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. <5:4> LTMP Read-Only Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. <7:6> TDM2 Read-Only Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement. If this register is read, this register and the reg isters holding the MSB of each reading are frozen u ntil read. Rev. 3 | Page 53 of 56 | www.onsemi.com

REV. A –54– ADM1027 Table XXXIII. Register 0x78 – Configuration Register 3 (Power-On Default = 0x00) Bit Name R/W Description <0> ALERT Read/Write ALERT = 1, Pin 10 (PWM2/ SMBALERT ) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. D efault = 0 = PWM2. <1> Reserved Read/Write Reserved for future use. <2> Reserved Read/Write Reserved for future use. <3> FAST Read/Write FAST = 1 enables fast TACH measure ments on all channels. This increases the TACH measurement rate from once per second, to once per 250 ms (4 /H11003). <4> DC1 Read/Write DC1 = 1 enables TACH measurements t o be continuously made on TACH1. <5> DC2 Read/Write DC2 = 2 enables TACH measurements t o be continuously made on TACH2. <6> DC3 Read/Write DC3 = 1 enables TACH measurements t o be continuously made on TACH3. <7> DC4 Read/Write DC4 = 1 enables TACH measurements t o be continuously made on TACH4. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Table XXXIV. Register 0x7B – Fan Pulses Per Revolution Register (Power On Default = 0x55) Bit Name R/W Description <1:0> FAN1 Read/Write Sets number of pulses to be coun ted when measuring FAN1 speed. Can be used to determine fan’s pulses per revolution number for un known fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <3:2> FAN2 Read/Write Sets number of pulses to be coun ted when measuring FAN2 speed. Can be used to determine fan’s pulses per revolution number for un known fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <5:4> FAN3 Read/Write Sets number of pulses to be coun ted when measuring FAN3 speed. Can be used to determine fan’s pulses per revolution for unknown f an type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 <7:6> FAN4 Read/Write Sets number of pulses to be coun ted when measuring FAN4 speed. Can be used to determine fan’s pulses per revolution for unknown f an type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 Rev. 3 | Page 54 of 56 | www.onsemi.com

REV. A ADM1027 –55– Table XXXV. Register 0x7E – Manufacturer’s Test Register 1 (Power-On Default = 0x00) Bit Name Read/Write Description <7:0> Reserved Read-Only Manufacturer’s Test Register. These bits are reserved for the manufacturer’s tes t purposes and should NOT be written to under normal operation. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Table XXXVI. Register 0x7F – Manufacturer’s Test Register 2 (Power-On Default = 0x00) Bit Name Read/Write Description <7:0> Reserved Read-Only Manufacturer’s Test Register. These bits are reserved for the manufacturer’s tes t purposes and should NOT be written to under normal operation. This register becomes read-only when the Configurat ion Register 1 lock bit is set to 1. Any further at tempts to write to this register will have no effect. Rev. 3 | Page 55 of 56 | www.onsemi.com

24-Lead Shrink Small Outline Package [QSOP] (RQ-24) Dimensions shown in millimeters and (inches) 24 13 12 1 0.236 BSC PIN 1 0.154 BSC SEATING PLANE 0.010 0.004 0.012 0.008 0.025 BSC 0.069 0.053 0.010 0.006 0.050 0.016 8/H11543 0/H11543 0.065

0.049 COPLANARITY

0.004 0.341 BSC COMPLIANT TO JEDEC STANDARDS MO-137AE Model Temperature Range Package Description Package Option ADM1027ARQ 0°C to 105°C 24-Lead QSOP RQ-24 ADM1027ARQ-REEL 0°C to 105°C 24-Lead QSOP RQ-24 ADM1027ARQ-REEL7 0°C to 105°C 24-Lead QSOP RQ-24 ADM1027ARQZ 0°C to 105°C 24-Lead QSOP RQ-24 ADM1027ARQZ-REEL 0°C to 105°C 24-Lead QSOP RQ-24 ADM1027ARQZ-RL7 1 0°C to 105°C 24-Lead QSOP RQ-24 1Z = Pb-Free part ON Semiconductor and the ON logo are registered trademarks o f Semiconductor Components Industries, LLC (SCILLC). SCIL LC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suita bility of its products for any particular purpose, nor doe s SCILLC assume any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation special, c onsequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifi cations can and do vary in different applications and actua l performance may vary over time. All operating parameter s, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC do es not convey any license under its patent rights nor the ri ghts of others. SCILLC products are not designed, intended, or a uthorized for use as components in systems intended for surg ical implant into the body, or other applications intended t o support or sustain life, or for any other application in which the failure of the SCILLC product could create a situat ion where personal injury or death may occur. Should Buye r purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its offi cers, employees, subsidiaries, affi liates, and distributors harmless against all claims, cos ts, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized us e, even if such claim alleges that SCILLC was negligent regar ding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affi rmative Action Employer. This literature is subject to all applicable copyright laws and is not for resal e in any manner. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email : orderlit@onsemi.com N. American Technical Support : 800-282-9855 Toll Free USA/Canada. Europe, Middle East and Africa Technical Support : Phone: 421 33 790 2910 Japan Customer Focus Cente r Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative PUBLICATION ORDERING INFORMATION