ADM1026 ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 3

1 Publication Order Number:

The ADM1026 is a complete system hardware monitor for microprocessor−based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, five of which are dedicated to monitoring +3.3 V , +5.0 V , and ±12 V power supplies, and the processor core voltage. The ADM1026 can monitor two other power supply voltages by measuring its own V CC and the main system supply. One input (two pins) is dedicated to a remote temperature −sensing diode. Two additional pins can be configured as general−purpose analog inputs to measure 0 V to 2.5 V , or as a second temperature sensing input. The eight remaining inputs are general−purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3.0 V . The ADM1026 also has an on −chip temperature sensor. The ADM1026 has eight pins that can be configured for fan speed measurement or as general−purpose logic I/O pins. Another eight pins are dedicated to general −purpose logic I/O. An additional pin can be configured as a general−purpose I/O or as the bidirectional THERM pin. Measured values can be read out via a 2 −wire serial system management bus, and values for limit comparisons can be programmed over the same serial bus. The high speed, successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out−of−limit measurement.

FEATURES

  • Up to 19 Analog Measurement Channels (Including Internal Measurements)
  • Up to 8 Fan Speed Measurement Channels
  • Up to 17 General−Purpose Logic I/O Pins
  • Remote Temperature Measurement with Remote Diode (Two Channels)
  • On−Chip Temperature Sensor
  • Analog and PWM Fan Speed Control Outputs
  • 2−Wire Serial System Management Bus (SMBus)
  • 8 kB On−Chip EEPROM
  • Full SMBus 1.1 Support Includes Packet Error Checking (PEC)
  • Chassis Intrusion Detection
  • Interrupt Output (SMBAlert)
  • Reset Input, Reset Outputs
  • Thermal Interrupt (THERM) Output
  • Limit Comparison of All Monitored Values
  • Pb−Free Packages are Available

APPLICATIONS

  • Network Servers and Personal Computers
  • Telecommunications Equipment
  • Test Equipment and Measuring Instruments http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 54 of this data sheet.

ORDERING INFORMATION

x = Refer to list of PNs in Ordering Info Table #= P b −Free Package YYWW = Date Code MARKING DIAGRAM LQFP−48 CASE 932 ADM1026 JSTx #YYWW

Figure 1. Functional Block Diagram

http://onsemi.com ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Positive Supply Voltage (VCC) 6.5 V Voltage on +12 VIN Pin +20 V Voltage on −12 VIN Pin −20 V Voltage on Analog Pins −0.3 to (VCC +0.3) V Voltage on Open−Drain Digital Pins −0.3 to +6.5 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJMAX) 150 °C Storage Temperature Range −65 to +150 °C Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 215 200 ESD Rating −12 VIN Pin All Other Pins 1000 2000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. THERMAL CHARACTERISTICS Package Type /C0113JA /C0113JC Unit 48−lead LQFP 50 10 °C/W PIN ASSIGNMENT Pin No. Mnemonic Type Description 1 GPIO9 Digital I/O† General−purpose I/O pin that can be configured as digital inputs or outputs. 2 GPIO8 Digital I/O† General−purpose I/O pin that can be configured as digital inputs or outputs. 3 FAN0/GPIO0 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 4 FAN1/GPIO1 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 5 FAN2/GPIO2 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 6 FAN3/GPIO3 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 7 3.3 V MAIN Analog Input Monitors the main 3.3 V system supply. Does not power the device. 8 DGND Ground Ground pin for digital circuits. 9 FAN4/GPIO4 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 10 FAN5/GPIO5 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 11 FAN6/GPIO6 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 12 FAN7/GPIO7 Digital I/O Fan tachometer input with internal 10 k/C0087 pullup resistor to 3.3 V STBY. Can be reconfigured as a general−purpose, open drain, digital I/O pin. 13 SCL Digital Input Open Drain Serial Bus Clock. Requires a 2.2 k/C0087 pullup resistor. 14 SDA Digital I/O Serial Bus Data. Open drain I/O. Requires a 2.2 k/C0087 pullup resistor. 15 ADD/NTESTOUT Digital Input This is a three−state input that controls the two LSBs of the serial bus address. It also functions as the output for NAND tree testing.

16 CI Digital Input An active high input that captures a chassis intrusion event in Bit 6 of Status

Register 4. This bit remains set until cleared, as long as battery voltage is applied to the V BAT input, even when the ADM1026 is powered off.

http://onsemi.com Pin No. DescriptionTypeMnemonic 17 INT Digital Output Interrupt Request (Open Drain). The output is enabled when Bit 1 of the configuration register is set to 1. The default state is disabled. It has an on−chip 100 k/C0087 pullup resistor. 18 PWM Digital Output Open drain pulse width modulated output for control of the fan speed. This pin defaults to high for the 100% duty cycle for use with NMOS drive circuitry. If a PMOS device is used to drive the fan, the PWM output may be inverted by setting Bit 1 of Test Register 1 = 1. 19 RESETSTBY Digital Output Power−On Reset. 5 mA driver (weak 100 k/C0087 pullup), active low output (100 k/C0087 pullup) with a 180 ms typical pulse width. RESETSTBY is asserted whenever 3.3 V STBY is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V STBY rises above the reset threshold. 20 RESETMAIN Digital I/O Power−On Reset. 5 mA driver (weak 100 k/C0087 pullup), active low output (100 k/C0087 pullup) with a 180 ms typical pulse width. RESETMAIN is asserted whenever 3.3 V MAIN is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V MAIN rises above the reset threshold. If, however, 3.3 V STBY rises with or before 3.3 V MAIN, then RESETMAIN remains asserted for 180 ms after RESETSTBY is deasserted. Pin 20 also functions as an active low RESET input. 21 AGND Ground Ground pin for analog circuits. 23 DAC Analog Output 0 V to 2.5 V output for analog control of the fan speed. 24 VREF Analog Output Reference Voltage Output. Can be selected as 1.8 V (default) or 2.5 V. 25 D1–/NTESTIN Analog Input Connected to a cathode of the first remote temperature sensing diode. If it is held high at power−on, it activates the NAND tree test mode. 26 D1+ Analog Input Connected to the anode of the first remote temperature sensing diode.

27 D2–/AIN9 Programmable Connected to the cathode of the second remote temperature sensing diode or the

analog input may be reconfigured as a 0 V− 2.5 V analog input.

28 D2+/AIN8 Programmable Connected to the anode of the second remote temperature sensing diode, or the

analog input may be reconfigured as a 0 V − 2.5 V analog input. 29 VBAT Analog Input Monitors battery voltage, nominally +3.0 V. 30 +5.0 VIN Analog Input Monitors the +5.0 V supply. 31 −12 VIN Analog Input Monitors the −12 V supply. 32 +12 VIN Analog Input Monitors the +12 V supply. 33 +VCCP Analog Input Monitors the processor core voltage (0 V to 3.0 V). 34 AIN7 Analog Input General−purpose 0 V to 2.5 V analog inputs. 35 AIN6 Analog Input General−purpose 0 V to 2.5 V analog inputs. 36 AIN5 Analog Input General−purpose 0 V to 3.0 V analog inputs. 37 AIN4 Analog Input General−purpose 0 V to 3.0 V analog inputs. 38 AIN3 Analog Input General−purpose 0 V to 3.0 V analog inputs. 39 AIN2 Analog Input General−purpose 0 V to 3.0 V analog inputs. 40 AIN1 Analog Input General−purpose 0 V to 3.0 V analog inputs. 41 AIN0 Analog Input General−purpose 0 V to 3.0 V analog inputs. 42 GPIO16/THERM Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. Can also be configured as a bidirectional THERM pin (100 k/C0087 pullup). 43 GPIO15 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. 44 GPIO14 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. 45 GPIO13 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. 46 GPIO12 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. 47 GPIO11 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. 48 GPIO10 Digital I/O† General−purpose I/O pin that can be configured as a digital input or output. †GPIO pins are open drain and require external pullup resistors. Fan inputs have integrated 10 k/C0087 pullups, but these pins become open drain when reconfigured as GPIOs.

http://onsemi.com ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3) Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Supply Voltage, 3.3 V STBY 3.0 3.3 5.5 V Supply Current, ICC Interface inactive, ADC active 2.5 4.0 mA TEMPERATURE−TO−DIGITAL CONVERTER Internal Sensor Accuracy ±3.0 °C Resolution ±1.0 °C External Diode Sensor Accuracy 0°C < TD < 100°C ±3.0 °C Resolution ±1.0 °C Remote Sensor Source Current High level Low level 5.5 /C0109A ANALOG−TO−DIGITAL CONVERTER (Including MUX and ATTENUATORS) Total Unadjusted Error (TUE) (Note 4) ±2.0 % Differential Non−linearity (DNL) ±1.0 LSB Power Supply Sensitivity ±0.1 %/V Conversion Time (Analog Input or Internal Temperature) (Note 5) 11.38 12.06 ms Conversion Time (External Temperature) (Note 5) 34.13 36.18 ms Input Resistance (+5.0 VIN, VCCP, AIN0 − AIN5) 80 100 120 k/C0087 Input Resistance of +12 VIN pin 70 100 115 k/C0087 Input Resistance of −12 VIN pin 8.0 10 12 k/C0087 Input Resistance (AIN6 − AIN9) 5.0 M/C0087 Input Resistance of VBAT pin (Note 4) 80 100 120 k/C0087 VBAT Current Drain (when measured) CR2032 battery life >10 years 80 100 nA VBAT Current Drain (when not measured) 6.0 nA ANALOG OUTPUT (DAC) Output Voltage Range 0 –2.5 V Total Unadjusted Error (TUE) IL = 2 mA ±5.0 % Zero Error No load 1.0 LSB Differential Non−linearity (DNL) Monotonic by design ±1.0 LSB Integral Non−linearity ±0.5 LSB Output Source Current 2.0 mA Output Sink Current 1.0 mA REFERENCE OUTPUT Output Voltage Bit 2 of Register 07h = 0 Bit 2 of Register 07h = 1 1.8 2.47 1.82 2.50 1.84 2.53 V Load Regulation (ISINK = 2 mA) 0.15 % Load Regulation (ISOURCE = 2 mA) 0.15 % Short Circuit Current VCC = 3.3 V 25 mA Output Current Source 2.0 mA Output Current Sink 2.0 mA

http://onsemi.com ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3) Parameter UnitMaxTypMinTest Conditions/Comments FAN RPM−TO−DIGITAL CONVERTER (Note 6) Accuracy ±12 % Full−Scale Count 255 FAN0 to FAN7 Nominal Input RPM (Note 5) Divisor = 1, fan count = 153 Divisor = 2, fan count = 153 Divisor = 4, fan count = 153 Divisor = 8, fan count = 153 8800 4400 2200 1100 RPM Internal Clock Frequency 20 22.5 25 kHz OPEN DRAIN O/Ps, PWM, GPIO0 to 16 Output High Voltage, VOH IOUT = 3.0 mA, VCC = 3.3 V 2.4 V High Level Output Leakage Current, IOH VOUT = VCC 0.1 1.0 /C0109A Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V 0.4 V PWM Output Frequency 75 Hz DIGITAL OUTPUTS (INT, RESETMAIN, RESETSTBY) Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V 0.4 V RESET Pulse Width 140 180 240 ms OPEN DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL IOUT = –3.0 mA, VCC = 3.3 V 0.4 V High Level Output Leakage Current, IOH VOUT = VCC 0.1 1.0 /C0109A SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.2 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16) (Note 7 and 8) Input High Voltage, VIH VCC = 3.3 V 2.4 V Input Low Voltage, VIL VCC = 3.3 V 0.8 V Hysteresis (Fan 0 to 7) VCC = 3.3 V 250 mV RESETMAIN, RESETSTBY RESETMAIN Threshold Falling voltage 2.89 2.94 2.97 V RESETSTBY Threshold Falling voltage 3.01 3.05 3.10 V RESETMAIN Hysteresis 60 mV RESETSTBY Hysteresis 70 mV DIGITAL INPUT CURRENT Input High Current, IIH VIN = VCC –1.0 /C0109A Input Low Current, IIL VIN = 0 1.0 /C0109A Input Capacitance, CIN 20 pF EEPROM RELIABILITY Endurance (Note 9) 100 700 kcycles Data Retention (Note 10) 10 Years SERIAL BUS TIMING Clock Frequency, fSCLK See Figure 2 for all parameters. 400 kHz Glitch Immunity, tSW 50 ns Bus Free Time, tBUF 4.7 /C0109s Start Setup Time, tSU; STA 4.7 /C0109s

  1. All voltages are measured with respect to GND, unless otherwise specified.
  2. Typicals are at T A = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V.
  3. Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
  4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on−chip input attenuators. VBAT is accurate

only for VBAT voltages greater than 1.5 V (see Figure 14).

  1. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature

channels, and 2 ms × 34.13 ms measurements on external temperature channels.

  1. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number

of fans connected and the fan speed. See the Fan Speed Measurement section for more details.

  1. ADD is a three −state input that may be pulled high, low, or left open circuit.
  2. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.
  3. Endurance is qualif ied to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance

energy of 0.6 V derates with junction temperature as shown in Figure 15. Figure 2. Serial Bus Timing Diagram

be reconfigured as analog inputs with a range of 0 V to 2.5 V . +12 V , and the processor core voltage VCCP, respectively. separate pin to monitor the power supply voltage. (Pins 3 to 6 and Pins 9 to 12). appropriate programming of the interrupt mask registers. latched in a battery−backed register bit. 3.3 V MAIN or 3.3 V STBY fall below the reset threshold. also functions as an active−low RESET input. speed, though they can also be used for other purposes. temperature sensor or remote temperature sensors. Table 1 describes the principal registers of the ADM1026. For more detailed information, see Table 8 to Table 121. Table 1. Principle Registers the address pointer register. various operating parameters. along with their limit values.

  • An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased.
  • Writing to EEPROM is slower than writing to RAM.
  • Writing to the EEPROM should be restricted because its typical cycle life is 100,000 write operations, due to the usual EEPROM wear−out mechanisms. The EEPROM in the ADM1026 has been qualified for two key EEPROM memory characteristics: memory cycling endurance and memory data retention. Endurance qualifies the ability of the EEPROM to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events, as follows: 1. Initial page erase sequence 2. Read/verify sequence 3. Program sequence 4. Second read/verify sequence In reliability qualification, every byte is cycled from 00h to FFh until a first fail is recorded, signifying the endurance limit of the EEPROM memory. Retention quantifies the ability of the memory to retain its programmed data over time. The EEPROM in the ADM1026 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (T J = 55°C) to guarantee a minimum of 10 years retention time. As part of this qualification procedure, the EEPROM memory is cycled to its specified endurance limit described above before data retention is characterized. This means that the EEPROM memory is guaranteed to retain its data for its full specified retention lifetime every time the EEPROM is reprogrammed. Note that retention lifetime based on an activation energy of 0.6 V derates with T J, as shown in Figure 15.

Figure 15. Typical EEPROM Memory Retention

2 LSBs are determined by the logical states of Pin 15

Table 2. Address Pin Truth Table is on (and the address is locked) have no effect. one ADM1026 is used in a system.

  1. The master initiates data transfer by establishing a

device (0 = write, 1 = read). master reads from the slave device.

13h. EEPROM Registers 1 and 2 are for factory use only. EEPROM Register 3 sets up the EEPROM operating mode. read mode. Setting Bit 1 puts it into programming mode. Setting Bit 2 puts it into erase mode. EEPROM read, program, or erase operation is attempted. cleared by a power−on reset. EEPROM Register 3 Bit 7 is used for clock extend.

  1. The master device asserts a start condition on the
  2. The master sends the 7−bit slave address followed
  3. The addressed slave device asserts an ACK on the
  4. The master sends a command code.
  5. The slave asserts ACK on the SDA.
  6. The master asserts a stop condition on the SDA

address. This is illustrated in Figure 18. Figure 18. Setting a RAM Address for Subsequent Read without asserting an intermediate stop condition.

  1. The master device asserts a start condition on the
  2. The master sends the 7−bit slave address followed
  3. The addressed slave device asserts an ACK on the
  4. The master sends a command code.
  5. The slave asserts an ACK on the SDA.
  6. The master sends a data byte.
  7. The slave asserts an ACK on the SDA.
  8. The master sends a data byte (or may assert stop
  9. The slave asserts an ACK on the SDA.
  10. The master asserts a stop condition on the SDA to

value of the command byte and EEPROM Register 3. The first purpose is to write a single byte of data to RAM.

Figure 19. Single Byte Write to RAM EEPROM address. This is illustrated in Figure 20. Figure 20. Setting an EEPROM Address operation without asserting an intermediate stop condition. In this case, Bit 0 of EEPROM Register 3 should be set. The third use is to erase a page of EEPROM memory. Figure 21. EEPROM Page Erasure responds with No Acknowledge. set. This is illustrated in Figure 22. Figure 22. Single−Byte Write to EEPROM a write byte/word operation to set an EEPROM address.

  1. The master device asserts a start condition on the
  2. The master sends the 7−bit slave address followed
  3. The addressed slave device asserts an ACK on the
  4. The master sends a command code that tells the
  5. The slave asserts an ACK on the SDA.
  6. The master sends a data byte (20h) that tells the

slave device that 32 data bytes are being sent to it.

  1. The slave asserts an ACK on the SDA.
  2. The master sends 32 data bytes.
  3. The slave asserts an ACK on the SDA after each
  4. The master sends a packet error checking (PEC)
  5. The ADM1026 checks the PEC byte and issues an
  6. The master asserts a stop condition on the SDA to

Figure 23. Block Write to EEPROM or RAM

32 PEC

  • There must be at least 32 locations from the start address to the highest EEPROM address (9FF) to avoid writing to invalid addresses.
  • If the addresses cross a page boundary, both pages must be erased before programming.
  1. The master device asserts a start condition on the
  2. The master sends the 7−bit slave address followed
  3. The addressed slave device asserts an ACK on the
  4. The master receives a data byte.
  5. The master asserts a NO ACK on the SDA.
  6. The master asserts a stop condition on the SDA to

Figure 24. Single−Byte Read from EEPROM or RAM

  1. The master device asserts a start condition on the
  2. The master sends the 7−bit slave address followed
  3. The addressed slave device asserts an ACK on the
  4. The master sends a command code that tells the
  5. The slave asserts an ACK on the SDA.
  6. The master asserts a repeat start condition on the
  7. The master sends the 7−bit slave address followed
  8. The slave asserts an ACK on the SDA.
  9. The ADM1026 sends a byte count data byte that

maximum allowed by the SMBus 1.1 specification.

  1. The master asserts an ACK on the SDA.
  2. The master receives 32 data bytes.
  3. The master asserts an ACK on the SDA after each
  4. The ADM1026 issues a PEC byte to the master.

another block read if the PEC byte is incorrect.

  1. A NACK is generated after the PEC byte to signal
  2. The master asserts a stop condition on the SDA to

Figure 25. Block Read from EEPROM or RAM

32 PEC AA BYTE

Consult the SMBus 1.1 Specification for more information. STBY , and the internal chip temperature. a second remote temperature sensor. −12 V, +12 V supplies, and the processor core voltage VCCP.

and output codes of the ADC. analog or local temperature input every 711 /C0109s (typical value). temperature input is 34.13 ms. Table 3. A−toD Output Codes vs. VIN

  1. * V BAT is not accurate for voltages under 1.5 V (see Figure 14).

Table 4. Temperature Data Format Digital boards can be electrically noisy environments.

  • Place the ADM1026 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 to 8 inches.
  • Route the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible.
  • Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended.

Figure 34. Arrangement of Signal Tracks

  • Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D− paths and are at the same temperature.
  • Thermocouple effects should not be a major problem because 1°C corresponds to about 240 /C0109V, a n d thermocouple voltages are about 3 /C0109V/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV .
  • Place a 0.1 /C0109F bypass capacitor close to the ADM1026.
  • If the distance to the remote sensor is more than eight inches, the use of twisted−pair cable is recommended. This works from about 6 to 12 feet.
  • For very long distances (up to 100 feet), use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADM1026. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. A 1/C0032/C0087 series resistance introduces about 0.5°C error. Limit Values Limit values for analog measurements are stored in the appropriate limit registers. In the case of voltage measurements, high and low limits can be stored so that an interrupt request is generated if the measured value goes above or below acceptable values. In the case of temperature, a hot temperature or high limit can be programmed, and a hot temperature hysteresis or low limit can be programmed, which is usually some degrees lower. This can be useful because it allows the system to be shut down when the hot limit is exceeded, and restarted automatically when it has cooled down to a safe temperature. Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the configuration register. INT_Enable (Bit 1) should be set to 1 to enable the INT output. The ADC measures each analog input in turn, starting with Remote Temperature Channel 1 and ending with local temperature. As each measurement is completed, the result is automatically stored in the appropriate value register. This round −robin monitoring cycle continues until it is disabled by writing a 0 to Bit 0 of the configuration register. Because the ADC is typically left to free−run in this way, the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is:
  • Five dedicated supply voltage inputs
  • Ten general−purpose analog inputs
  • 3.3 V MAIN
  • 3.3 V STBY
  • Local temperature

Figure 37. Fan Drive Circuit with Op Amp and Figure 38. Discrete Fan Drive Circuit with P−Channel Figure 39. Discrete Fan Drive Circuit with P−Channel PWM control using an N−channel MOSFET. Figure 40. PWM Fan Drive Circuit Using an

5.0 V OR 12 V

by setting Bit 5 and/or Bit 6 of Configuration Register 1. TMIN can be the same or different for all three channels. 05h) set the minimum values for the DAC and PWM outputs.

Figure 44. Fan with Tach Pullup to Voltage > VCC resistive attenuator may be used, as shown in Figure 47.

2.0 V /C0116VPULLUP /C0032 R2

Figure 45. Fan with Strong Tach Pullup to >VCC or Figure 46. Fan with Strong Tach Pullup to > VCC or period and inversely proportional to the fan speed. Figure 47. Fan Speed Measurement from the second rising tach edge to the fourth rising edge. The measurement then switches to the next fan channel. is repeated for the other six fan channels. ADM1026 could generate false fan failure interrupts. (divisor) of 1, 2, 4, or 8 may be added before the counter.

two tach pulses per revolution. when the measurement exceeds the limit value. 509 is the total number of clock pulses. D is the divisor: 1, 2, 4, or 8. 0.05 ms is the worst−case oscillator period in ms. the worst−case measurement time for each fan. synchronized in any other way. Table 5. Fan Speeds and Divisors in Bit 6 of Status Register 4, and an interrupt is generated. is cleared by writing a 0 to it.

  • A microswitch that opens or closes when the cover is removed.
  • A reed switch operated by magnet fixed to the cover.
  • A hall−effect switch operated by magnet fixed to the cover.
  • A phototransistor that detects light when the cover is removed. The chassis intrusion input can also be used for other types of alarm input. Figure 48 shows a temperature alarm circuit using an AD22105 temperature switch sensor. This produces a low−going output when the preset temperature is exceeded, so the output is inverted by Q1 to make it compatible with the CI input. Q1 can be almost any small−signal NPN transistor, or a TTL or CMOS inverter gate may be used if one is available.

Figure 48. Using the CI Input with a Temperature Sensor

temperature of all three sensors is 5°C below the limit. Figure 52. Interrupt Structure

1 STATUS

2 STATUS

4 STATUS

3 STATUS

Figure 59. NAND Tree Test with One Input Stuck High are low if either is low, but high only if both are high. together, causing a missing pulse in the output pattern. Figure 60. NAND Tree Test with Two Inputs Shorted should be cleared by writing a 0 to it.

  • Writing values to the limit registers.
  • Configuring Pins 3 to 6, and 9 to 12 as fan inputs or GPIO, using Configuration Register 2 (Address 01h).
  • Setting the fan divisors using the fan divisor registers (Addresses 02h and 03h).
  • Configuring the GPIO pins for input/output polarity, using GPIO Configuration Registers 1 to 4 (Addresses 08h to 0Bh) and Bits 6 and 7 of Configuration Register 3.
  • Setting mask bits in Mask Registers 1 to 6 (Addresses 18h to 1Dh) for any inputs that are to be masked out.
  • Setting up Configuration Registers 1 and 3, as described in Table 6 and Table 7.

Table 6. Configuration Register 1 2 Used to clear the INT interrupt output when set high.

3 Configures Pins 27 and 28 as the second external

4 Enables the THERM output when set to 1.

5 Enables automatic fan speed control on the DAC

6 Enables automatic fan speed control on the PWM

7 Performs a soft reset when set to 1. Table 7. Configuration Register 3

0 Configures Pin 42 as GPIO when set to 1 or as

must be written to allow subsequent CI detection. 6, 7 Set up GPIO16 for direction and polarity. independently, and are not synchronized in any way.

http://onsemi.com Reduced Power Mode The ADM1026 can be placed in a low power mode by setting Bit 0 of the configuration register to 0. This disables the internal ADC. Software Reset Function As previously mentioned, the ADM1026 can be reset in software by setting Bit 7 of Configuration Register 1 (Reg. 00h) to 1. Configuration Register 1, 00h, should then be manually cleared. Note that the software reset differs from a power−on reset in that only some of the ADM1026 registers are reinitialized to their power−on default values. The registers that are initialized to their default values by the software reset are

  • Configuration Registers (Registers 01h to 0Bh)
  • Mask Registers 1 to 6, internal temperature offset, and Status Registers 4, 5, and 6 (Registers 18h to 25h)
  • All value registers (Registers 1Fh, 20h to 3Fh)
  • External 1 and External 2 Offset Registers (6Eh, 6Fh) Note that the limit registers (0Dh to 12h, 40h to 6Dh) are not reset by the software reset function. This can be useful if one needs to reset the part but does not want to reprogram all parameters again. Note that a power−on reset initializes all registers on the ADM1026, including the limit registers. Application Schematic Figure 61 shows how the ADM1026 could be used in an application that requires system management of a PC or server. Several GPIOs are used to read the VID codes of the CPU. Up to two CPU temperature measurements can be read back. All power supply voltages are monitored in the system. Up to eight fan speeds can be measured, irrespective of whether they are controlled by the ADM1026 or hardwired to a system supply. The V REF output includes the recommended filtering circuitry.

Figure 61. ADM1026 Schematic

Table 8. Address Pointer Register 7–0 Address Pointer W Address of ADM1026 registers. See the following tables for details. Table 9. List of Registers 00 Configuration 1 00h Configures various operating parameters . 01 Configuration 2 00h Configures Pins 3–6 and 9–12 as fan inputs or GPIO. 02 Fan 0–3 Divisor 55h Sets oscillator frequency for Fan 0–3 speed measurement. 03 Fan 4–7 Divisor 55h Sets oscillator frequency for Fan 4–7 speed measurement.

04 DAC Control FFh Contains value for fan speed DAC (analog fan speed control) or minimum value

for automatic fan speed control.

05 PWM Control FFh Contains value for PWM fan speed control or minimum value for automatic fan

06 EEPROM Register 100h For factory use only. 07 Configuration Register 300h Configuration register for THERM, VREF and GPIO16. 08 GPIO Config 1 00h Configures GPIO0 to GPIO3 as input or output and as active high or active low. 09 GPIO Config 2 00h Configures GPIO4 to GPIO7 as input or output and as active high or active low. 0A GPIO Config 3 00h Configures GPIO8 to GPIO11 as input or output and as active high or active low. 0B GPIO Config 4 00h Configures GPIO12 to GPIO15 as input or output and as active high or active low. 0C EEPROM Register 2 00h For factory use only.

10 Int Temp TMIN 28h (40°C) TMIN value for automatic fan speed control based on internal temperature

11 TDM1 TMIN 40h (64°C) TMIN value for automatic fan speed control based on Remote Channel 1 (D1)

12 TDM2 TMIN 40h (64°C) TMIN value for automatic fan speed control based on Remote Channel 2 (D2)

13 EEPROM Register 3 00h Configures EEPROM for read/write/erase, etc. 14 Test Register 1 00h Manufacturer’s test register. 15 Test Register 2 00h For manufacturer’s use only. 16 Manufacturer’s ID 41h Contains manufacturer’s ID code. 18 Mask Register 1 00h Interrupt mask register for temperature and supply voltage faults. 19 Mask Register 2 00h Interrupt mask register for analog input faults. 1A Mask Register 3 00h Interrupt mask register for fan faults. 1B Mask Register 4 00h Interrupt mask register for local temp, VBAT, AIN8, THERM, AFC, CI and GPIO16. 1C Mask Register 5 00h Interrupt mask register for GPIO0 to GPIO7. 1D Mask Register 6 00h Interrupt mask register for GPIO8 to GPIO15. 1E Int Temp Offset 00h Offset register for internal temperature measurement. 1F Int Temp Value 00h Measured temperature from on–chip sensor. 20 Status Register 1 00h Interrupt status register for external temp and supply voltage faults. 21 Status Register 2 00h Interrupt status register for analog input faults. 22 Status Register 3 00h Interrupt status register for fan faults. 23 Status Register 4 00h Interrupt status register for local temp, VBAT, AIN8, THERM, AFC, CI, and GPIO16.

http://onsemi.com Hex Address DescriptionPower−On ValueName 24 Status Register 5 00h Interrupt status register for GPIO0 to GPIO7. 25 Status Register 6 00h Interrupt status register for GPIO8 to GPIO15. 26 VBAT Value 00h Measured value of VBAT. 27 AIN8 Value 00h Measured value of AIN8. 28 TDM1 Value 00h Measured value of remote temperature channel 1 (D1). 29 TDM2/AIN9 Value 00h Measured value of remote temperature channel 2 (D2) or AIN9. 2A 3.3 V STBY Value 00h Measured value of 3.3 V STBY. 2B 3.3 V MAIN Value 00h Measured value of 3.3 V MAIN. 2C +5.0 V Value 00h Measured value of +5.0 V supply. 2D VCCP Value 00h Measured value of processor core voltage. 2E +12 V Value 00h Measured value of +12 V supply. 2F −12 V Value 00h Measured value of -12 V supply. 30 AIN0 Value 00h Measured value of AIN0.

31 AIN1 Value 00h Measured value of AIN1

32 AIN2 Value 00h Measured value of AIN2. 33 AIN3 Value 00h Measured value of AIN3. 34 AIN4 Value 00h Measured value of AIN4. 35 AIN5 Value 00h Measured value of AIN5. 36 AIN6 Value 00h Measured value of AIN6. 37 AIN7 Value 00h Measured value of AIN7. 38 FAN0 Value 00h Measured speed of Fan 0. 39 FAN1 Value 00h Measured speed of Fan 1. 3A FAN2 Value 00h Measured speed of Fan 2. 3B FAN3 Value 00h Measured speed of Fan 3. 3C FAN4 Value 00h Measured speed of Fan 4. 3D FAN5 Value 00h Measured speed of Fan 5. 3E FAN6 Value 00h Measured speed of Fan 6. 3F FAN7 Value 00h Measured speed of Fan 7. 40 TDM1 High Limit 64h (100°C) High limit for Remote Temperature Channel 1 (D1) measurement. 41 TDM2/AIN9 High Limit 64h (100°C) High limit for Remote Temperature Channel 2 (D2) or AIN9 measurement. 42 3.3 V STBY High Limit FFh High limit for 3.3 V STBY measurement. 43 3.3 V MAIN High Limit FFh High limit for 3.3 V MAIN measurement. 44 +5.0 V High Limit FFh High limit for +5.0 V supply measurement. 45 VCCP High Limit FFh High limit for processor core voltage measurement. 46 +12 V High Limit FFh High limit for +12 V supply measurement. 47 −12 V High Limit FFh High limit for -12 V supply measurement. 48 TDM1 Low Limit 80h Low limit for Remote Temperature Channel 1 (D1) measurement. 49 TDM2/AIN9 Low Limit 80h Low limit for Remote Temperature Channel 2 (D2) or AIN9 measurement. 4A 3.3 V STBY Low Limit 00h Low limit for 3.3 V STBY measurement. 4B 3.3 V MAIN Low Limit 00h Low limit for 3.3 V MAIN measurement. 4C +5.0 V Low Limit 00h Low limit for +5.0 V supply. 4D VCCP Low Limit 00h Low limit for processor core voltage measurement. 4E +12 V Low Limit 00h Low limit for +12 V supply measurement. 4F −12 V Low Limit 00h Low limit for -12 V supply measurement. 50 AIN0 High Limit FFh High limit for AIN0 measurement. 51 AIN1 High Limit FFh High limit for AIN1 measurement. 52 AIN2 High Limit FFh High limit for AIN2 measurement. 53 AIN3 High Limit FFh High limit for AIN3 measurement.

http://onsemi.com Hex Address DescriptionPower−On ValueName 54 AIN4 High Limit FFh High limit for AIN4 measurement. 55 AIN5 High Limit FFh High limit for AIN5 measurement. 56 AIN6 High Limit FFh High limit for AIN6 measurement. 57 AIN7 High Limit FFh High limit for AIN7 measurement. 58 AIN0 Low Limit 00h Low limit for AIN0 measurement. 59 AIN1 Low Limit 00h Low limit for AIN1 measurement. 5A AIN2 Low Limit 00h Low limit for AIN2 measurement. 5B AIN3 Low Limit 00h Low limit for AIN3 measurement. 5C AIN4 Low Limit 00h Low limit for AIN4 measurement. 5D AIN5 Low Limit 00h Low limit for AIN5 measurement. 5E AIN6 Low Limit 00h Low limit for AIN6 measurement. 5F AIN7 Low Limit 00h Low limit for AIN7 measurement. 60 FAN0 High Limit FFh High limit for Fan 0 speed measurement (no low limit). 61 FAN1 High Limit FFh High limit for Fan 1 speed measurement (no low limit). 62 FAN2 High Limit FFh High limit for Fan 2 speed measurement (no low limit). 63 FAN3 High Limit FFh High limit for Fan 3 speed measurement (no low limit). 64 FAN4 High Limit FFh High limit for Fan 4 speed measurement (no low limit). 65 FAN5 High Limit FFh High limit for Fan 5 speed measurement (no low limit). 66 FAN6 High Limit FFh High limit for Fan 6 speed measurement (no low limit). 67 FAN7 High Limit FFh High limit for Fan 7 speed measurement (no low limit). 68 Int. Temp. High Limit 50h (80°C) High limit for local temperature measurement. 69 Int. Temp. Low Limit 80h Low limit for local temperature measurement. 6A VBAT High Limit FFh High limit for VBAT measurement. 6B VBAT Low Limit 00h Low limit for VBAT measurement. 6C AIN8 High Limit FFh High limit for AIN8 measurement. 6D AIN8 Low Limit 00h Low limit for AIN8 measurement. 6E Ext1 Temp Offset 00h Offset register for Remote Temperature Channel 1. 6F Ext2 Temp Offset 00h Offset register for Remote Temperature Channel 2.

Table 10. Register 00h, Configuration Register 1 (Power−On Default 00h)

0 Monitor = 0 R/W When this bit is set the ADM1026 monitors all voltage, temperature and fan

channels in a round robin manner. 1 Int Enable = 0 R/W When this bit is set, the INT output pin is enabled.

2 Int Clear = 0 R/W Setting this bit clears an interrupt from the voltage, temperature or fan speed

again on the next monitoring cycle. is not being used, it is recommended that the bit be set to 1.

4 Enable THERM = 0 R/W When this bit is 1, the THERM pin (Pin 42) is asserted (go low) if any of the

PWM outputs are forced to full scale until THERM is taken high.

5 Enable DAC AFC = 0 R/W When this bit is 1, the DAC output is enabled for automatic fan speed control

in Reg 04h, the DAC Control Register.

6 Enable PWM AFC = 0 R/W When this bit is 1, the PWM output is enabled for automatic fan speed control

in Reg 05h, the PWM Control Register. cleared by writing a 0 to it. For more info, see the Software Reset Function section. Table 11. Register 01h, Configuration Register 2 (Power−On Default 00h)

0 Enable GPIO0/Fan0 = 0 R/W When this bit is 1, Pin 3 is enabled as a general−purpose I/O pin (GPIO0),

otherwise it is a fan tach measurement input (Fan 0).

1 Enable GPIO1/Fan1 = 0 R/W When this bit is 1, Pin 4 is enabled as a general−purpose I/O pin (GPIO1),

otherwise it is a fan tach measurement input (Fan 1).

2 Enable GPIO2/Fan2 = 0 R/W When this bit is 1, Pin 5 is enabled as a general−purpose I/O pin (GPIO2),

otherwise it is a fan tach measurement input (Fan 2).

3 Enable GPIO3/Fan3 = 0 R/W When this bit is 1, Pin 6 is enabled as a general−purpose I/O pin (GPIO3),

otherwise it is a fan tach measurement input (Fan 3).

4 Enable GPIO4/Fan4 = 0 R/W When this bit is 1, Pin 9 is enabled as a general−purpose I/O pin (GPIO4),

otherwise it is a fan tach measurement input (Fan 4).

5 Enable GPIO5/Fan5 = 0 R/W When this bit is 1, Pin 10 is enabled as a general−purpose I/O pin (GPIO5),

otherwise it is a fan tach measurement input (Fan 5).

6 Enable GPIO6/Fan6 = 0 R/W When this bit is 1, Pin 11 is enabled as a general−purpose I/O pin (GPIO6),

otherwise it is a fan tach measurement input (Fan 6).

7 Enable GPIO7/Fan7 = 0 R/W When this bit is 1, Pin 12 is enabled as a general−purpose I/O pin (GPIO7),

otherwise it is a fan tach measurement input (Fan 7).

Table 12. Register 02h, Fans 0 to 3 Fan Divisor Register (Power−On Default 55h) Table 13. Register 03h, Fans 4 to 7 Fan Divisor Register (Power−On Default 55h) Table 14. Register 04h, DAC Configuration Register (Power−On Default FFh) Table 15. Register 05h, PWM Control Register (Power−On Default FFh) Table 16. Register 06h, EEPROM Register 1 (Power−On Default 00h) 7–0 Factory Use R/W For factory use only. Do not write to this register.

Table 17. Register 07h, Configuration Register 3 (Power−On Default 00h)

0 Enable GPIO16/

otherwise it is the THERM output. 1 CI Clear = 0 R/W Writing a 1 to this bit clears the CI latch. This bit is cleared by writing a 0 to it. 2 VREF Select = 0 R/W When this bit is 0, VREF (Pin 24) outputs 1.82 V, otherwise, it outputs 2.5 V. 5–3 Unused R Undefined, reads back 0. 6 GPIO16 Direction R/W When this bit is 0, GPIO16 is configured as an input; otherwise, it is an output. 7 GPIO16 Polarity R/W When this bit is 0, GPIO16 is active low; otherwise, it is active high. Table 18. Register 08h, GPIO Configuration Register 1 (Power−On Default 00h) 0 GPIO0 Direction R/W When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output. 1 GPIO0 Polarity R/W When this bit is 0, GPIO0 is active low; otherwise it is active high. 2 GPIO1 Direction R/W When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output. 3 GPIO1 Polarity R/W When this bit is 0, GPIO1 is active low; otherwise it is active high. 4 GPIO2 Direction R/W When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output. 5 GPIO2 Polarity R/W When this bit is 0, GPIO2 is active low; otherwise, it is active high. 6 GPIO3 Direction R/W When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output. 7 GPIO3 Polarity R/W When this bit is 0, GPIO3 is active low; otherwise, it is active high. Table 19. Register 09h, GPIO Configuration Register 2 (Power−On Default 00h) 0 GPIO4 Direction R/W When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output. 1 GPIO4 Polarity R/W When this bit is 0, GPIO4 is active low; otherwise, it is active high. 2 GPIO5 Direction R/W When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output. 3 GPIO5 Polarity R/W When this bit is 0, GPIO5 is active low; otherwise, it is active high. 4 GPIO6 Direction R/W When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output. 5 GPIO6 Polarity R/W When this bit is 0, GPIO6 is active low; otherwise, it is active high. 6 GPIO7 Direction R/W When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output. 7 GPIO7 Polarity R/W When this bit is 0, GPIO7 is active low; otherwise, it is active high. Table 20. Register 0Ah, GPIO Configuration Register 3 (Power−On Default 00h) 0 GPIO8 Direction R/W When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output. 1 GPIO8 Polarity R/W When this bit is 0, GPIO8 is active low; otherwise, it is active high. 2 GPIO9 Direction R/W When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output. 3 GPIO9 Polarity R/W When this bit is 0, GPIO9 is active low; otherwise, it is active high. 4 GPIO10 Direction R/W When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output. 5 GPIO10 Polarity R/W When this bit is 0, GPIO10 is active low; otherwise, it is active high. 6 GPIO11 Direction R/W When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output. 7 GPIO11 Polarity R/W When this bit is 0, GPIO11 is active low; otherwise, it is active high.

Table 21. Register 0Bh, GPIO Configuration Register 4 (Power−On Default 00h) 0 GPIO12 Direction R/W When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output. 1 GPIO12 Polarity R/W When this bit is 0, GPIO12 is active low; otherwise, it is active high. 2 GPIO13 Direction R/W When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output. 3 GPIO13 Polarity R/W When this bit is 0, GPIO13 is active low; otherwise, it is active high. 4 GPIO14 Direction R/W When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output. 5 GPIO14 Polarity R/W When this bit is 0, GPIO14 is active low; otherwise, it is active high. 6 GPIO15 Direction R/W When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output. 7 GPIO15 Polarity R/W When this bit is 0, GPIO15 is active low; otherwise, it is active high. Table 22. Register 0Ch, EEPROM Configuration Register 2 (Power−On Default 00h) 7–0 Factory Use R For factory use only. Do not write to this register. Table 23. Register 0Dh, Internal Temperature THERM Limit (Power−On Default, 37h 55/C0053C) 7–0 Int Temp THERM Limit R/W This register contains the THERM limit for the internal temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 24. Register 0Eh, TDM1 THERM Limit (Power−On Default, 50h 80/C0053C) 7–0 TDM1 THERM Limit R/W This register contains the THERM limit for the TDM1 temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 25. Register 0Fh, TDM2 THERM Limit (Power−On Default, 50h 80/C0053C) 7–0 TDM2 THERM Limit R/W This register contains the THERM limit for the TDM2 temperature channel. Exceeding this limit causes the THERM output pin to be asserted. Table 26. Register 10h, Internal Temperature TMIN (Power−On Default, 28h 40/C0053C) internal temperature channel. Table 27. Register 11h, TDM1 Temperature TMIN (Power−On Default, 40h 64/C0053C) Table 28. Register 12h, TDM2 Temperature TMIN (Power−On Default, 40h 64/C0053C)

Table 29. Register 13h, EEPROM Register 3 (Power−On Default, 00h) 0 Read R/W Setting this bit puts the EEPROM into read mode. 1 Write R/W Setting this bit puts the EEPROM in write (program) mode. 2 Erase R/W Setting this bit puts the EEPROM into erase mode.

3 Write Protect R/W

can write once and only be cleared by a power−on reset. 5 Test Mode Bit 1 R/W Test mode bits. For factory use only. Table 30. Register 14h, Manufacturer’s Test Register 1 (Power−On Default, 00h) from or written to in normal operation. Table 31. Register 15h, Manufacturer’s Test Register 2 (Power−On Default, 00h) from or written to in normal operation. Table 32. Register 16h, Manufacturer’s ID (Power−On Default, 041h) 7–0 Manufacturer ID Code R/W This register contains the manufacturer’s ID code. Table 33. Register 17h, Revision Register (Power−On Default, 4xh) 3–0 Minor Revision Code R This nibble contains the manufacturer’s code for minor revisions to the device. Table 34. Register 18h, Mask Register 1 (Power−On Default, 00h)

0 Ext1 Temp Mask = 0 R/W When this bit is set, interrupts generated on the Ext1 temperature channel are

1 Ext2 Temp R/W When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out. 5 VCCP Mask = 0 R/W When this bit is set, interrupts generated on the VCCP voltage channel are masked out. 6 +12 V Mask = 0 R/W When this bit is set, interrupts generated on the +12 V voltage channel are masked out. 7 −12 V Mask = 0 R/W When this bit is set, interrupts generated on the −12 V voltage channel are masked out.

Table 35. Register 19h, Mask Register 2 (Power−On Default, 00h) 0 AIN0 Mask = 0 R/W When this bit is set, interrupts generated on the AIN0 voltage channel are masked out. 1 AIN1 Mask = 0 R/W When this bit is set, interrupts generated on the AIN1 voltage channel are masked out. 2 AIN2 Mask = 0 R/W When this bit is set, interrupts generated on the AIN2 voltage channel are masked out. 3 AIN3 Mask = 0 R/W When this bit is set, interrupts generated on the AIN3 voltage channel are masked out. 4 AIN4 Mask = 0 R/W When this bit is set, interrupts generated on the AIN4 voltage channel are masked out. 5 AIN5 Mask = 0 R/W When this bit is set, interrupts generated on the AIN5 voltage channel are masked out. 6 AIN6 Mask = 0 R/W When this bit is set, interrupts generated on the AIN6 voltage channel are masked out. 7 AIN7 Mask = 0 R/W When this bit is set, interrupts generated on the AIN7 voltage channel are masked out. Table 36. Register 1Ah, Mask Register 3 (Power−On Default, 00h) 0 FAN0 Mask = 0 R/W When this bit is set, interrupts generated on the FAN0 tach channel are masked out. 1 FAN1 Mask = 0 R/W When this bit is set, interrupts generated on the FAN1 tach channel are masked out. 2 FAN2 Mask = 0 R/W When this bit is set, interrupts generated on the FAN2 tach channel are masked out. 3 FAN3 Mask = 0 R/W When this bit is set, interrupts generated on the FAN3 tach channel are masked out. 4 FAN4 Mask = 0 R/W When this bit is set, interrupts generated on the FAN4 tach channel are masked out. 5 FAN5 Mask = 0 R/W When this bit is set, interrupts generated on the FAN5 tach channel are masked out. 6 FAN6 Mask = 0 R/W When this bit is set, interrupts generated on the FAN6 tach channel are masked out. 7 FAN7 Mask = 0 R/W When this bit is set, interrupts generated on the FAN7 tach channel are masked out. Table 37. Register 1Bh, Mask Register 4 (Power−On Default, 00h) 1 VBAT Mask = 0 R/W When this bit is set, interrupts generated on the VBAT voltage channel are masked out. 2 AIN8 Mask = 0 R/W When this bit is set, interrupts generated on the AIN8 voltage channel are masked out. 3 THERM Mask = 0 R/W When this bit is set, interrupts generated from THERM events are masked out.

4 AFC Mask = 0 R/W When this bit is set, interrupts generated from automatic fan control events are

5 Unused R/W Unused. Reads back 0. 6 CI Mask = 0 R/W When this bit is set, interrupts generated by the chassis intrusion input are masked out. 7 GPIO16 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO16 channel are masked out. Table 38. Register 1Ch, Mask Register 5 (Power−On Default, 00h) 0 GPIO0 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO0 channel are masked out. 1 GPIO1 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO1 channel are masked out. 2 GPIO2 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO2 channel are masked out. 3 GPIO3 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO3 channel are masked out. 4 GPIO4 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO4 channel are masked out. 5 GPIO5 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO5 channel are masked out. 6 GPIO6 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO6 channel are masked out. 7 GPIO7 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO7 channel are masked out.

Table 39. Register 1Dh, Mask Register 6 (Power−On Default, 00h) 0 GPIO8 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO8 channel are masked out. 1 GPIO9 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO9 channel are masked out. 2 GPIO10 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO10 channel are masked out. 3 GPIO11Mask = 0 R/W When this bit is set, interrupts generated on the GPIO11 channel are masked out. 4 GPIO12 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO12 channel are masked out. 5 GPIO13 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO13 channel are masked out. 6 GPIO14 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO14 channel are masked out. 7 GPIO15 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO15 channel are masked out. Table 40. Register 1Eh, INT Temp Offset (Power−On Default, 00h) the measurement point is moved, if a plug−in card is inserted or removed, and so on. Table 41. Register 1Fh, INT Temp Measured Value (Power−On Default, 00h) 7–0 Int Temp Value R This register contains the measured value of the internal temperature channel. Table 42. Register 20h, Status Register 1 (Power−On Default, 00h) readings going 5°C below Ext1 THERM limit. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise.

5 VCCP Status = 0 R 1, if VCCP value is above the high limit or below the low limit on the previous

conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise.

Table 43. Register 21h, Status Register 2 (Power−On Default, 00h) conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. conversion cycle; 0 otherwise. Table 44. Register 22h, Status Register 3 (Power−On Default, 00h)

Table 45. Register 23h, Status Register 4 (Power−On Default, 00h)

0 INT Temp Status = 0 R 1, if INT value is above the high limit or below the low limit on the previous

engaged as a result of INT temperature readings exceeding the INT THERM limit. temperature readings going 5°C below Int THERM limit.

1 VBAT Status = 0 R 1, if VBAT value is above the high limit or below the low limit on the previous

conversion cycle, 0 otherwise.

2 AIN8 Status = 0 R 1, if AIN8 value is above the high limit or below the low limit on the previous

conversion cycle, 0 otherwise.

3 THERM Status = 0 R This bit is set (once only) if a THERM mode is engaged as a result of temperature

below THERM limits on any channel. also set (once only) if the fan turns off when in automatic fan speed control mode. 5 Unused R Unused. Reads back 0. 6 CI Status = 0 R This bit latches a chassis intrusion event.

7 GPIO16 Status = 0 R

When GPIO16 is configured as an input, this bit is set when GPIO16 is asserted.

Table 46. Register 24h, Status Register 5 (Power−On Default, 00h)

0 GPIO0 Status = 0 R

When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted.

1 GPIO1 Status = 0 R

When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted.

2 GPIO2 Status = 0 R

When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted.

3 GPIO3 Status = 0 R

When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted.

4 GPIO4 Status = 0 R

When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted.

5 GPIO5 Status = 0 R

When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted.

6 GPIO6 Status = 0 R

When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted.

7 GPIO7 Status = 0 R

When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted.

  1. GPIO status bits can be written only when a GPIO pin is configured as output. Read −only otherwise.

Table 47. Register 25h, Status Register 6 (Power−On Default, 00h)

0 GPIO8 Status = 0 R

When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted.

1 GPIO9 Status = 0 R

When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted.

2 GPIO10 Status = 0 R

When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted.

3 GPIO11 Status = 0 R

When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted.

4 GPIO12 Status = 0 R

When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted.

5 GPIO13 Status = 0 R

When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted.

6 GPIO14 Status = 0 R

When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted.

7 GPIO15 Status = 0 R

When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted.

  1. GPIO status bits can be written only when a GPIO pin is configured as output. Read −only otherwise.

Table 48. Register 26h, VBAT Measured Value (Power−On Default, 00h) 7–0 VBAT Value R This register contains the measured value of the VBAT analog input channel. Table 49. Register 27h, AIN8 Measured Value (Power−On Default, 00h) 7–0 AIN8 Value R This register contains the measured value of the AIN8 analog input channel.

Table 50. Register 28h, EXT1 Measured Value (Power−On Default, 00h) 7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel. Table 51. Register 29h, EXT2/AIN9 Measured Value (Power−On Default, 00h) Table 52. Register 2Ah, 3.3 V STBY Measured Value (Power−On Default, 00h) 7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage. Table 53. Register 2Bh, 3.3 V MAIN Measured Value (Power−On Default, 00h) 7–0 3.3 V MAIN Value R This register contains the measured value of the 3.3 V MAIN voltage. Table 54. Register 2Ch, +5.0 V Measured Value (Power−On Default, 00h) 7–0 +5.0 V Value R This register contains the measured value of the +5.0 V analog input channel. Table 55. Register 2Dh, VCCP Measured Value (Power−On Default, 00h) 7–0 VCCP Value R This register contains the measured value of the VCCP analog input channel. Table 56. Register 2Eh, +12 V Measured Value (Power−On Default, 00h) 7–0 +12 V Value R This register contains the measured value of the +12 V analog input channel. Table 57. Register 2Fh, −12 V Measured Value (Power−On Default, 00h) 7–0 –12 V Value R This register contains the measured value of the -12 V analog input channel. Table 58. Register 30h, AIN0 Measured Value (Power−On Default, 00h) 7–0 AIN0 Value R This register contains the measured value of the AIN0 analog input channel. Table 59. Register 31h, AIN1 Measured Value (Power−On Default, 00h) 7–0 AIN1 Value R This register contains the measured value of the AIN1 analog input channel. Table 60. Register 32h, AIN2 Measured Value (Power−On Default, 00h) 7–0 AIN2 Value R This register contains the measured value of the AIN2 analog input channel.

Table 61. Register 33h, AIN3 Measured Value (Power−On Default, 00h) 7–0 AIN3 Value R This register contains the measured value of the AIN3 analog input channel. Table 62. Register 34h, AIN4 Measured Value (Power−On Default, 00h) 7–0 AIN4 Value R This register contains the measured value of the AIN4 analog input channel. Table 63. Register 35h, AIN5 Measured Value (Power−On Default, 00h) 7–0 AIN5 Value R This register contains the measured value of the AIN5 analog input channel. Table 64. Register 36h, AIN6 Measured Value (Power−On Default, 00h) 7–0 AIN6 Value R This register contains the measured value of the AIN6 analog input channel. Table 65. Register 37h, AIN7 Measured Value (Power−On Default, 00h) 7–0 AIN7 Value R This register contains the measured value of the AIN7 analog input channel. Table 66. Register 38h, FAN0 Measured Value (Power−On Default, 00h) 7–0 FAN0 Value R This register contains the measured value of the FAN0 tach input channel. Table 67. Register 39h, FAN1 Measured Value (Power−On Default, 00h) 7–0 FAN1 Value R This register contains the measured value of the FAN1 tach input channel. Table 68. Register 3Ah, FAN2 Measured Value (Power−On Default, 00h) 7–0 FAN2 Value R This register contains the measured value of the FAN2 tach input channel. Table 69. Register 3Bh, FAN3 Measured Value (Power−On Default, 00h) 7–0 FAN3 Value R This register contains the measured value of the FAN3 tach input channel. Table 70. Register 3Ch, FAN4 Measured Value (Power−On Default, 00h) 7–0 FAN4 Value R This register contains the measured value of the FAN4 tach input channel. Table 71. Register 3Dh, FAN5 Measured Value (Power−On Default, 00h) 7–0 FAN5 Value R This register contains the measured value of the FAN5 tach input channel.

Table 72. Register 3Eh, FAN6 Measured Value (Power−On Default, 00h) 7–0 FAN6 Value R This register contains the measured value of the FAN6 tach input channel. Table 73. Register 3Fh, FAN7 Measured Value (Power−On Default, 00h) 7–0 FAN7 Value R This register contains the measured value of the FAN7 tach input channel. Table 74. Register 40h, EXT1 HIgh Limit (Power−On Default 64h/100/C0053C) 7–0 Ext1 High Limit R/W This register contains the high limit of the Ext1 Temp channel. Table 75. Register 41h, EXT2/AIN9 HIgh Limit (Power−On Default 64h/100/C0053C) Table 76. Register 42h, 3.3 V STBY HIgh Limit (Power−On Default FFh) 7–0 3.3 V STBY High Limit R/W This register contains the high limit of the 3.3 V STBY analog input channel. Table 77. Register 43h, 3.3 V MAIN HIgh Limit (Power−On Default FFh) 7–0 3.3 V MAIN High Limit R/W This register contains the high limit of the 3.3 V MAIN analog input channel. Table 78. Register 44h, +5.0 V HIgh Limit (Power−On Default FFh) 7–0 +5.0 V High Limit R/W This register contains the high limit of the +5.0 V analog input channel. Table 79. Register 45h, VCCP HIgh Limit (Power−On Default FFh) 7–0 VCCP High Limit R/W This register contains the high limit of the VCCP analog input channel. Table 80. Register 46h, +12 V HIgh Limit (Power−On Default FFh) 7–0 +12 V High Limit R/W This register contains the high limit of the +12 V analog input channel. Table 81. Register 47h, −12 V HIgh Limit (Power−On Default FFh) 7–0 −12 V High Limit R/W This register contains the high limit of the -12 V analog input channel. Table 82. Register 48h, EXT1 Low Limit (Power−On Default 80h) 7–0 Ext1 Low Limit R/W This register contains the low limit of the Ext1 Temp channel.

Table 83. Register 49h, EXT/AIN9 Low Limit (Power−On Default 80h) Table 84. Register 4Ah, 3.3 V STBY Low Limit (Power−On Default 00h) 7–0 3.3 V STBY Low Limit R/W This register contains the low limit of the 3.3 V STBY analog input channel. Table 85. Register 4Bh, 3.3 V MAIN Low Limit (Power−On Default 00h) 7–0 3.3 V MAIN Low Limit R/W This register contains the low limit of the 3.3 V MAIN analog input channel. Table 86. Register 4Ch, +5.0 V Low Limit (Power−On Default 00h) 7–0 +5.0 V Low Limit R/W This register contains the low limit of the +5.0 V analog input channel. Table 87. Register 4Dh, VCCP Low Limit (Power−On Default 00h) 7–0 VCCP Low Limit R/W This register contains the low limit of the VCCP analog input channel. Table 88. Register 4Eh, +12 V Low Limit (Power−On Default 00h) 7–0 +12 V Low Limit R/W This register contains the low limit of the +12 V analog input channel. Table 89. Register 4Fh, −12 V Low Limit (Power−On Default 00h) 7–0 −12 V Low Limit R/W This register contains the low limit of the -12 V analog input channel. Table 90. Register 50h, AIN0 High Limit (Power−On Default FFh) 7–0 AIN0 High Limit R/W This register contains the high limit of the AIN0 analog input channel. Table 91. Register 51h, AIN1 High Limit (Power−On Default FFh) 7–0 AIN1 High Limit R/W This register contains the high limit of the AIN1 analog input channel. Table 92. Register 52h, AIN2 High Limit (Power−On Default FFh) 7–0 AIN2 High Limit R/W This register contains the high limit of the AIN2 analog input channel. Table 93. Register 53h, AIN3 High Limit (Power−On Default FFh) 7–0 AIN3 High Limit R/W This register contains the high limit of the AIN3 analog input channel.

Table 94. Register 54h, AIN4 High Limit (Power−On Default FFh) 7–0 AIN4 High Limit R/W This register contains the high limit of the AIN4 analog input channel. Table 95. Register 55h, AIN5 High Limit (Power−On Default FFh) 7–0 AIN5 High Limit R/W This register contains the high limit of the AIN5 analog input channel. Table 96. Register 56h, AIN6 High Limit (Power−On Default FFh) 7–0 AIN6 High Limit R/W This register contains the high limit of the AIN6 analog input channel. Table 97. Register 57h, AIN7 High Limit (Power−On Default FFh) 7–0 AIN7 High Limit R/W This register contains the high limit of the AIN7 analog input channel. Table 98. Register 58h, AIN0 Low Limit (Power−On Default 00h) 7–0 AIN0 Low Limit R/W This register contains the low limit of the AIN0 analog input channel. Table 99. Register 59h, AIN1 Low Limit (Power−On Default 00h) 7–0 AIN1 Low Limit R/W This register contains the low limit of the AIN1 analog input channel. Table 100. Register 5Ah, AIN2 Low Limit (Power−On Default 00h) 7–0 AIN2 Low Limit R/W This register contains the low limit of the AIN2 analog input channel. Table 101. Register 5Bh, AIN3 Low Limit (Power−On Default 00h) 7–0 AIN3 Low Limit R/W This register contains the low limit of the AIN3 analog input channel. Table 102. Register 5Ch, AIN4 Low Limit (Power−On Default 00h) 7–0 AIN4 Low Limit R/W This register contains the low limit of the AIN4 analog input channel. Table 103. Register 5Dh, AIN5 Low Limit (Power−On Default 00h) 7–0 AIN5 Low Limit R/W This register contains the low limit of the AIN5 analog input channel. Table 104. Register 5Eh, AIN6 Low Limit (Power−On Default 00h) 7–0 AIN6 Low Limit R/W This register contains the low limit of the AIN6 analog input channel.

Table 105. Register 5Fh, AIN7 Low Limit (Power−On Default 00h) 7–0 AIN7 Low Limit R/W This register contains the low limit of the AIN7 analog input channel. Table 106. Register 60h, FAN0 High Limit (Power−On Default FFh) 7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel. Table 107. Register 61h, FAN1 High Limit (Power−On Default FFh) 7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel. Table 108. Register 62h, FAN2 High Limit (Power−On Default FFh) 7–0 FAN2 High Limit R/W This register contains the high limit of the FAN2 tach channel. Table 109. Register 63h, FAN3 High Limit (Power−On Default FFh) 7–0 FAN3 High Limit R/W This register contains the high limit of the FAN3 tach channel. Table 110. Register 64h, FAN4 High Limit (Power−On Default FFh) 7–0 FAN4 High Limit R/W This register contains the high limit of the FAN4 tach channel. Table 111. Register 65h, FAN5 High Limit (Power−On Default FFh) 7–0 FAN5 High Limit R/W This register contains the high limit of the FAN5 tach channel. Table 112. Register 66h, FAN6 High Limit (Power−On Default FFh) 7–0 FAN6 High Limit R/W This register contains the high limit of the FAN6 tach channel. Table 113. Register 67h, FAN7 High Limit (Power−On Default FFh) 7–0 FAN7 High Limit R/W This register contains the high limit of the FAN7 tach channel. Table 114. Register 68h, Int Temp High Limit (Power−On Default, 50h 80/C0053C) 7–0 Int Temp High Limit R/W This register contains the high limit of the internal temperature channel. Table 115. Register 69h, Int Temp High Limit (Power−On Default 80h) 7–0 Int Temp Low Limit R/W This register contains the low limit of the internal temperature channel.

http://onsemi.com Table 116. Register 6Ah, VBAT High Limit (Power−On Default FFh) 7–0 VBAT High Limit R/W This register contains the high limit of the VBAT analog input channel. Table 117. Register 6Bh, VBAT Low Limit (Power−On Default 00h) 7–0 VBAT Low Limit R/W This register contains the low limit of the VBAT analog input channel. Table 118. Register 6Ch, AIN8 High Limit (Power−On Default FFh) 7–0 AIN8 High Limit R/W This register contains the high limit of the AIN8 analog input channel. Table 119. Register 6Dh, AIN8 Low Limit (Power−On Default 00h) 7–0 AIN8 Low Limit R/W This register contains the low limit of the AIN8 analog input channel. Table 120. Register 6Eh, Ext1 Temp Offset (Power−On Default 00h) measurement point is moved, if a plug−in card is inserted or removed, and so on. Table 121. Register 6Fh, Ext2 Temp Offset (Power−On Default 00h) measurement point is moved, if a plug−in card is inserted or removed, and so on. Device Order Number Temperature Range Package Type Package Option Shipping† ADM1026JST 0°C to +100°C 48−Lead LQFP ST−48 250 Tray ADM1026JST−REEL 0°C to +100°C 48−Lead LQFP ST−48 2000 Tape & Reel ADM1026JST−REEL7 0°C to +100°C 48−Lead LQFP ST−48 500 Tape & Reel ADM1026JSTZ 0°C to +100°C 48−Lead LQFP (Pb−Free) ST−48 250 Tray ADM1026JSTZ−REEL 0°C to +100°C 48−Lead LQFP (Pb−Free) ST−48 2000 Tape & Reel ADM1026JSTZ−REEL7 0°C to +100°C 48−Lead LQFP (Pb−Free) ST−48 500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part.

http://onsemi.com PACKAGE DIMENSIONS 48 LEAD LQFP, 7x7, 0.5P CASE 932AA−01 ISSUE A ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÉÉÉ ÉÉÉ ÉÉÉ Z0.2 Y T-U 13 24 3748 G G T, U, Z DETAIL K DETAIL K BASE METAL c1 c b T-UM0.08 Z Y SECTION G−G 0.08 Y TOP & BOTTOM (S) L (L1) A2A A1 0.250 R DETAIL F NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE Y . 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. T U Z GAUGE PLANE D D/2 PIN 1 E1/2 E E/2 D1/2 H Y e/2 e44 X 48 X b DETAIL F e/2 PLATING NOTE 9 CORNER Z0.2 H T-U DIM MIN MAX MILLIMETERS A 1.4 1.6 A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 9.0 BSC D1 7.0 BSC e 0.5 BSC E 9.0 BSC E1 7.0 BSC L 0.5 0.7 L1 1.0 REF R 0.15 0.25 S 0.2 REF /C01131 5 1 12 REF /C0095/C0095 SEATING PLANE /C0113 /C0113 /C0113 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ADM1026/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative