ADM1026 AD | Alldatasheet

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Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Up to 19 analog measurement channels (including internal measurements) Up to 8 fan speed measurement channels Up to 17 general-purpose logic I/O pins Remote temperature measurement with remote diode (two channels) On-chip temperature sensor Analog and PWM fan speed control outputs 2-wire serial system management bus (SMBus) 8 kB on-chip EEPROM Full SMBus 1.1 support includes packet error checking (PEC) Chassis intrusion detection Interrupt output (SMBAlert) Reset input, reset outputs Thermal interrupt (THERM) output Limit comparison of all monitored values

APPLICATIONS

Network servers and personal computers Telecommunications equipment Test equipment and measuring instruments D2–/AIN9 (0V – +2.5V) D2+/AIN8 (0V – +2.5V) AIN7 (0V – +2.5V) AIN6 (0V – +2.5V) TO GPIO REGISTERS 100kΩ 100kΩ VCC VCC VCC FAN SPEED COUNTER INPUT ATTENUATORS AND ANALOG MULTIPLEXER GPIO REGISTERS SERIAL BUS INTERFACE ADDRESS POINTER REGISTER BAND GAP TEMPERATURE SENSOR AUTOMATIC FAN SPEED CONTROL 8k BYTES EEPROM 8-BIT ADC BAND GAP REFERENCE VBAT +5 VIN –12 VIN +12 VIN +VCCP AIN0 (0V – +3V) AIN1 (0V – +3V) AIN2 (0V – +3V) AIN3 (0V – +3V) AIN4 (0V – +3V) AIN5 (0V – +3V) D1+ D1–/NTESTIN DGND DAC AGND V REF (1.82V OR 2.5V) SCLSDA 3.3V MAIN ADD/ NTESTOUT FAN7/GPIO7 FAN6/GPIO6 FAN5/GPIO5 FAN4/GPIO4 FAN3/GPIO3 FAN2/GPIO2 FAN1/GPIO1 FAN0/GPIO0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 PWM 3.3V STBY GPIO16/THERM CI ADM1026 INT RESET IN VCC VCC 100kΩ RESETMAIN RESETSTBY PWM REGISTER AND CONTROLLER LIMIT COMPARATORS INT MASK REGISTERS INTERRUPT MASKING CONFIGURATION REGISTERS VALUE AND LIMIT REGISTERS 3.3V MAIN RESET GENERATOR 3.3V STBY RESET GENERATOR INTERRUPT STATUS REGISTERS ANALOG OUTPUT REGISTER AND 8-BIT DAC 02657-A-001 Figure 1. Functional Block Diagram

Rev. A | Page 2 of 56 TABLE OF CONTENTS

REVISION HISTORY

3/04—Data Sheet Changed from Rev. 0 to Rev. A 5/02—Revision 0: Initial Version

Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.

5.5 Low level µA

4400 Divisor = 2, fan count = 153 RPM

2200 Divisor = 4, fan count = 153 RPM

1100 Divisor = 8, fan count = 153 RPM

Rev. A | Page 4 of 56 Parameter Min Typ Max Test Conditions/Comments Unit High Level Output Leakage Current, IOH 0.1 1 V OUT = VCC µA Output Low Voltage, VOL 0.4 I OUT = −3.0 mA, VCC = 3.3 V V PWM Output Frequency 75 Hz DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY) Output Low Voltage, VOL 0.4 I OUT = −3.0 mA, VCC = 3.3 V V RESET Pulse Width 140 180 240 ms OPEN DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL 0.4 I OUT = –3.0 mA, VCC = 3.3 V V High Level Output Leakage Current, IOH 0.1 1 V OUT = VCC µA SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.2 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)7, 8 Input High Voltage, VIH 2.4 V CC = 3.3 V V Input Low Voltage, VIL 0.8 V CC = 3.3 V V Hysteresis (Fan 0 to 7) 250 V CC = 3.3 V mV RESETMAIN, RESETSTBY RESETMAIN Threshold 2.89 2.94 2.97 Falling voltage V RESETSBY Threshold 3.01 3.05 3.10 Falling voltage V RESETMAIN Hysteresis 60 mV RESETSTBY Hysteresis 70 mV DIGITAL INPUT CURRENT Input High Current, IIH –1 V IN = VCC µA Input Low Current, IIL 1 V IN = 0 µA Input Capacitance, CIN 20 pF EEPROM RELIABILITY Endurance9 100 700 kcycles Data Retention10 10 Years SERIAL BUS TIMING See Figure 2 for all parameters. Clock Frequency, fSCLK 400 kHz Glitch Immunity, tSW 50 ns Bus Free Time, tBUF 4.7 µs Start Setup Time, tSU; STA 4.7 µs Start Hold Time, tHD; STA 4 µs SCL Low Time, tLOW 4.7 µs SCL High Time, tHIGH 4 µs SCL, SDA Rise Time, tr 1000 ns SCL, SDA Fall Time, tf 300 ns Data Setup Time, tSU; DAT 250 ns Data Hold Time, tHD; DAT 300 ns 1 All voltages are measured with respect to GND, unless otherwise specified. 2 Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. 3 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 4 Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate only for VBAT voltages greater than 1.5 V (see Figure 15). 5 Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and 2 ms × 34.13 ms measurements on external temperature channels. 6 The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the fan speed. See the Fan Speed Measurement section for more details. 7 ADD is a three-state input that may be pulled high, low, or left open-circuit. 8 Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V. 9 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles. 10 Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V derates with junction temperature as shown in Figure 16.

  • 48-Lead LQFP package
  • θJA = 50°C/W , θJC = 10°C/W PS tSU; DAT tHIGH tF tHD; DAT tR tLOW tSU; STO PS SCL SDA tBUF tHD; STA tHD; STA tSU; STA 02657-A-002

Figure 2. Serial Bus Timing Diagram degradation or loss of functionality.

Figure 3. Pin Configuration 1 GPIO9 Digital I/O 1 General-purpose I/O pin that can be conf igured as digital inputs or outputs. 2 GPIO8 Digital I/O 1 General-purpose I/O pin that can be co nfigured as digital inputs or outputs. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. 7 3.3 V MAIN Analog Input Mo nitors the main 3.3 V system supply. Does not power the device. 8 DGND Ground Ground pin for digital circuits. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. reconfigured as a general-purpose, open drain, digital I/O pin. 13 SCL Digital Input Open Drain Serial Bus Clock. Requires a 2.2 kΩ pull-up resistor. 14 SDA Digital I/O Serial Bus Data. Open drain I/O. Requires a 2.2 kΩ pull-up resistor. functions as the output for NAND tree testing. 16 CI Digital Input An active high input that captures a chassis intrusion event in Bit 6 of Status Register 4. even when the ADM1026 is powered off. register is set to 1. The default state is disabled. It has an on-chip 100 kΩ pull-up resistor.

Rev. A | Page 7 of 56 Pin No. Mnemonic Type Description 18 PWM Digital Output Open drain pulse width modulated output for control of the fan speed. This pin defaults to high for the 100% duty cycle for use with NMOS drive circuitry. If a PMOS device is used to drive the fan, the PWM output may be inverted by setting Bit 1 of Test Register 1 = 1. 19 RESETSTBY Digital Output Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETSTBY is asserted whenever 3.3 V STBY is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V STBY rises above the reset threshold. 20 RESETMAIN Digital I/O Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETMAIN is asserted whenever 3.3 V MAIN is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V MAIN rises above the reset threshold. If, however, 3.3 V STBY rises with or before 3.3 V MAIN, then RESETMAIN remains asserted for 180 ms after RESETSTBY is deasserted. Pin 20 also functions as an active low RESET input. 21 AGND Ground Ground pin for analog circuits. 23 DAC Analog Output 0 V to 2.5 V outp ut for analog control of the fan speed. 24 V REF Analog Output Reference Volt age Output. Can be selected as 1.8 V (default) or 2.5 V. 25 D1–/NTESTIN Analog Input Connected to a cathode of the first remote temperature sensing diode. If it is held high at power-on, it activates the NAND tree test mode. 26 D1+ Analog Input Connected to the anode of the first remote temperature sensing diode. 27 D2–/A IN9 Programmable Connected to the cathode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V− 2.5 V analog input. 28 D2+/A IN8 Programmable Connected to the anode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V − 2.5 V analog input. 29 V BAT Analog Input Monitors batte ry voltage, nominally +3 V. 30 +5 V IN Analog Input Monito rs the +5 V supply. 31 −12 VIN Analog Input Monitors the −12 V supply. 32 +12 V IN Analog Input Monito rs the +12 V supply. 33 +V CCP Analog Input Monitors the proces sor core voltage (0 V to 3.0 V). 34 A IN7 Analog Input General-purpos e 0 V to 2.5 V analog inputs. 35 A IN6 Analog Input General-purpos e 0 V to 2.5 V analog inputs. 36 A IN5 Analog Input General-pur pose 0 V to 3 V analog inputs. 37 A IN4 Analog Input General-pur pose 0 V to 3 V analog inputs. 38 A IN3 Analog Input General-pur pose 0 V to 3 V analog inputs. 39 A IN2 Analog Input General-pur pose 0 V to 3 V analog inputs. 40 A IN1 Analog Input General-pur pose 0 V to 3 V analog inputs. 41 A IN0 Analog Input General-pur pose 0 V to 3 V analog inputs. 42 GPIO16/THERM Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. Can also be configured as a bidirectional THERM pin (100 kΩ pull-up). 43 GPIO15 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 44 GPIO14 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 45 GPIO13 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 46 GPIO12 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 47 GPIO11 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 48 GPIO10 Digital I/O 1 General-purpose I/O pin that can be configured as a digital input or output. 1 GPIO pins are open drain and require external pull-up resistors. Fan inputs have integrated 10 kΩ pull-ups, but these pins become open drain when reconfigured as GPIOs.

Rev. A | Page 10 of 56 PRODUCT DESCRIPTION The ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, five of which are dedicated to monitoring +3.3 V , +5 V , and ±12 V power supplies, and the processor core voltage. The ADM1026 can monitor two other power supply voltages by measuring its own V CC and the main system supply. One input (two pins) is dedicated to a remote temperature-sensing diode. Two additional pins can be configured as general-purpose analog inputs to measure 0 V to 2.5 V , or as a second temperature sensing input. The eight remaining inputs are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V . The ADM1026 also has an on-chip temperature sensor. The ADM1026 has eight pins that can be configured for fan speed measurement or as general-purpose logic I/O pins. Another eight pins are dedicated to general-purpose logic I/O. An additional pin can be configured as a general-purpose I/O or as the bidirectional THERM pin. Measured values can be read out via a 2-wire serial system management bus, and values for limit comparisons can be programmed over the same serial bus. The high speed, successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out- of-limit measurement. FUNCTIONAL DESCRIPTION The ADM1026 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial system management bus. The serial bus controller has a hardwired address line for device selection (ADD, Pin 15), a serial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (SCL, Pin 13). All control and programming functions of the ADM1026 are performed over the serial bus. Measurement Inputs Programmability of the analog and digital measurement inputs makes the ADM1026 extremely flexible and versatile. The device has an 8-bit A/D converter, and 17 analog measurement input pins that can be configured in different ways. Pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperature- sensing diode. Pins 27 and 28 may be configured as temperature inputs and connected to a second temperature-sensing diode, or may be reconfigured as analog inputs with a range of 0 V to 2.5 V . Pins 29 to 33 are dedicated analog inputs with on-chip attenuators configured to monitor V and the processor core voltage VCCP, respectively. Pins 34 to 41 are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V . These are mainly intended for monitoring SCSI termination voltages, but may be used for other purposes. The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature. In addition, the ADM1026 monitors the supply from which it is powered, 3.3 V STBY, so there is no need for a separate pin to monitor the power supply voltage. The ADM1026 has eight pins that are general-purpose logic I/O pins (Pins 1, 2, and 43 to 48), a pin that can be configured as GPIO or as a bidirectional thermal interrupt (THERM ) pin (Pin 42), and eight pins that can be configured for fan speed measurement or as general-purpose logic pins (Pins 3 to 6 and Pins 9 to 12). Sequential Measurement When the ADM1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in value registers. These can be read over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the interrupt status registers. An out-of-limit event generates an interrupt on the INT line (Pin 17). Any or all of the interrupt status bits can be masked by appropriate programming of the interrupt mask registers. Chassis Intrusion A chassis intrusion input (Pin 16) is provided to detect unauthorized tampering with the equipment. This event is latched in a battery-backed register bit. Resets The ADM1026 has two power-on reset outputs, RESETMAIN and RESETSTBY, that are asserted when 3.3 V MAIN or 3.3 V STBY fall below the reset threshold. These give a 180 ms reset pulse at power-up. RESETMAIN also functions as an active-low RESET input.

bus as a slave device, under the control of a master device. device is powered on, it does so with a default serial bus address. determined by the logical states of Pin 15 ADD/NTESTOUT. CC, or left open-circuit to give three different addresses. Table 5. Address Pin Truth Table (and the address is locked) have no effect. operations, which are discussed later in this section.

  1. The master initiates data transfer by establishing a start
  2. Data is sent over the serial bus in sequences of nine clock

the address from which data is to be read.

  1. When all data bytes have been read or written, stop

1 If it is required to perform several read or write operations in succession, the

Figure 22. EEPROM Page Erasure Figure 23. Single-Byte Write to EEPROM byte/word operation to set an EEPROM address.

  1. The master device asserts a start condition on the SDA.
  2. The master sends the 7-bit slave address followed by the
  3. The addressed slave device asserts an ACK on the SDA.
  4. The master sends a command code that tells the slave

code for a block write is A0h (10100000).

  1. The slave asserts an ACK on the SDA.
  2. The master sends a data byte (20h) that tells the slave

should always send 32 data bytes to the ADM1026.

  1. The slave asserts an ACK on the SDA.
  2. The master sends 32 data bytes.
  3. The slave asserts an ACK on the SDA after each data byte.
  4. The master sends a packet error checking (PEC ) byte.
  5. The ADM1026 checks the PEC byte and issues an ACK if
  6. The master asserts a stop condition on the SDA to end the

32 PEC

Figure 24. Block Write to EEPROM or RAM

  • There must be at least 32 locations from the start address to the highest EEPROM address (9FFF) to avoid writing to invalid addresses.
  • If the addresses cross a page boundary, both pages must be erased before programming. ADM1026 Read Operations The ADM1026 uses the SMBus read protocols described here. Receive Byte In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on the SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts an ACK on the SDA. 4. The master receives a data byte. 5. The master asserts a NO ACK on the SDA. 6. The master asserts a stop condition on the SDA to end the transaction. In the ADM1026, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation. Figure 25 shows this. When reading from EEPROM, Bit 0 of EEPROM Register 3 must be set. S SLAVE ADDRESS RA DATA A P 12 3 4 5 6 02657-A-025

Figure 25. Single-Byte Read from EEPROM or RAM

  1. The master device asserts a start condition on the SDA.
  2. The master sends the 7-bit slave address followed by the
  3. The addressed slave device asserts an ACK on the SDA.
  4. The master sends a command code that tells the slave

code for a block read is A1h (10100001).

  1. The slave asserts an ACK on the SDA.
  2. The master asserts a repeat start condition on the SDA.
  3. The master sends the 7-bit slave address followed by the
  4. The slave asserts an ACK on the SDA.
  5. The ADM1026 sends a byte count data byte that tells the

by the SMBus 1.1 specification.

  1. The master asserts an ACK on the SDA.
  2. The master receives 32 data bytes.
  3. The master asserts an ACK on the SDA after each data byte.
  4. The ADM1026 issues a PEC byte to the master. The master
  5. A NACK is generated after the PEC byte to signal the end
  6. The master asserts a stop condition on the SDA to end the

32 PEC AA BYTE

Figure 26. Block Read from EEPROM or RAM Consult the SMBus 1.1 Specification for more information. inputs and output codes of the ADC.

Table 6. A-to-D Output Code vs. VIN

3.3 V MAIN

3.3 V STBY VBAT1 V CCP A IN (0–5) A IN (6–9) Decimal Binary

1 VBAT is not accurate for voltages under 1.5 V (see Figure 15).

cooled down to a safe temperature. result is automatically stored in the appropriate value register. measured value of any input can be read out at any time. it can easily be calculated.

  • Ten general-purpose analog inputs
  • 3.3 V MAIN
  • 3.3 V STBY
  • Local temperature
  • Two remote temperature Pins 28 and 27 are measured both as analog inputs AIN8/AIN9 and as remote temperature input D2+/D2−, irrespective of which configuration is selected for these pins. If Pins 28 and 27 are configured as AIN8/AIN9, the measurements for these channels are stored in Registers 27h and 29h, and the invalid temperature measurement is discarded. On the other hand, if Pins 28 and 27 are configured as D2+/D2−, the temper- ature measurement is stored in Register 29h, and there is no valid result in Register 27h. As mentioned previously, the ADC performs a conversion every 711 µs on the analog and local temperature inputs and every 2.13 ms on the remote temperature inputs. Each input is measured 16 times and averaged to reduce noise. The total monitoring cycle time for voltage and temperature inputs is therefore nominally The ADC uses the internal 22.5 kHz clock, which has a toler- ance of ±6%, so the worst-case monitoring cycle time is 290 ms. The fan speed measurement uses a completely separate monitoring loop, as described later. Input Safety Scaling of the analog inputs is performed on-chip, so external attenuators are typically not required. However, because the power supply voltages appear directly at the pins, it is advisable to add small external resistors (that is, 500 Ω) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. Because the resistors form part of the input attenuators, they affect the accuracy of the analog measurement if their value is too high. The worst such accident would be connecting −12 V to +12 V where there is a total of 24 V difference. With the series resistors, this would draw a maximum current of approximately 24 mA. ANALOG OUTPUT The ADM1026 has a single analog output from an unsigned 8-bit DAC that produces 0 V to 2.5 V (independent of the refer- ence voltage setting). The input data for this DAC is contained in the DAC control register (Address 04h). The DAC control register defaults to FFh during a power-on reset, which pro- duces maximum fan speed. The analog output may be amplified and buffered with external circuitry such as an op amp and a transistor to provide fan speed control. During automatic fan speed control, described later, the four MSBs of this register set the minimum fan speed. Suitable fan drive circuits are shown in Figure 36 through

Figure 40. When using any of these circuits, note the following: the gain of these circuits needs to be about 4.8.

  • Take care when choosing the op amp to ensure that its input common-mode range and output voltage swing are suitable. The op amp may be powered from the +12 V rail alone or from ±12 V . If it is powered from +12 V , the input common-mode range should include ground to accom- modate the minimum output voltage of the DAC, and the output voltage should swing below 0.6 V to ensure that the transistor can be turned fully off. If the op amp is powered from −12 V , precautions such as a clamp diode to ground may be needed to prevent the base-emitter junction of the output transistor being reverse-biased in the unlikely event that the output of the op amp should swing negative for any reason.

Bit 6 of Configuration Register 1. TMIN for that channel should be set to 127°C (01111111). PWM control register (Address 05h) has no effect.

2565.2 CodeVoltageOutputDAC ×=

where D is the decimal equivalent of Bits 7 to 4 of the register. code increases linearly up to 240, not its full scale of 255. sensor channel demanding the highest fan speed. Figure 42. Automatic PWM Fan Control Transfer Function Figure 43. Automatic DAC Fan Control Transfer Function inputs are set for fan speed measurement.

spin-up time, all fan tach registers read 0x00. controlled, variable-speed fans, the situation is different. measurement exceeds the limit value. manner time out after 255 clock pulses. 509 is the total number of clock pulses. D is the divisor: 1, 2, 4, or 8. 0.05 ms is the worst-case oscillator period in ms. worst-case measurement time for each fan. Table 8. Fan Speeds and Divisors

generated when the system is powered on.

  • A microswitch that opens or closes when the cover is removed.
  • A reed switch operated by magnet fixed to the cover.
  • A hall-effect switch operated by magnet fixed to the cover.
  • A phototransistor that detects light when the cover is removed. The chassis intrusion input can also be used for other types of alarm input. Figure 49 shows a temperature alarm circuit using an AD22105 temperature switch sensor. This produces a low- going output when the preset temperature is exceeded, so the output is inverted by Q1 to make it compatible with the CI input. Q1 can be almost any small-signal NPN transistor, or a TTL or CMOS inverter gate may be used if one is available. See the AD22105 data sheet on the Analog Devices, Inc. website (www.analog.com) for information on selecting R SET. VCC RSET AD22105 TEMPERATURE SENSOR 6 CI 10kΩ 3 2 02657-A-049

Figure 49. Using the CI Input with a Temperature Sensor function by clearing this bit. registers makes the corresponding GPIO pin an output. Clearing the direction bit to 0 makes it an input. registers makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes it active low. depending on the setting of the polarity bit). bit in one of the GPIO status registers becomes read/write. to monitor a processor’s voltage ID code (VID code).

sources that operate in a different way from the other status bits. not cause INT to be reasserted. Figure 52. Assertion of INT Due to AFC Event other interrupt sources may cause INT to be asserted. sets Bit 6 of Status Register 4. Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is low.

  • Status Register 1 is read. Ideally, if polling the status registers trying to identify interrupt sources, Status Register 1 should be polled last, because a read of Status Register 1 clears all the other interrupt status registers.
  • The ADM1026 receives the alert response address (ARA) (0001 100) over the SMBus. Bit 2 of Configuration Register 1 is set. Bidirectional THERM Pin The ADM1026 has a second interrupt pin (GPIO16/THERM Pin 42) that responds only to critical thermal events. The THERM pin goes low whenever a THERM limit is exceeded. This function is useful for CPU throttling or system shutdown. In addition, whenever THERM is activated, the PWM and DAC outputs go full scale to provide fail-safe system cooling. This output is enabled by setting Bit 4 of Configuration Register 1 (Register 00h). Whenever a THERM limit is exceeded, Bit 3 of Status Register 4 (Reg 23h) is set, even if the THERM function is disabled (Bit 4 of Configuration Register 1 = 0). In this case, the THERM status bit is set, but the PWM and DAC outputs are not forced to full scale. Three thermal limit registers are provided for the three temperature sensors at Addresses 0Dh to 0Fh. These registers are dedicated to the THERM function and none of the other limit registers have any effect on the THERM output. If any of the temperature measurements exceed the correspond- ing limit, THERM is asserted (low) and the DAC and PWM outputs go to maximum to drive any cooling fans to full speed. To avoid cooling fans cycling on and off continually when the temperature is close to the limit, a fixed hysteresis of 5°C is provided. THERM is only deasserted when the measured temperature of all three sensors is 5°C below the limit. Whenever the THERM output changes, INT is asserted, as shown in Figure 54. However, this is edge-triggered, so if INT is subsequently cleared by one of the methods previously described, it is not reasserted, even if THERM remains asserted. THERM causes INT to be reasserted only when it changes state.

1 STATUS

2 STATUS

4 STATUS

3 STATUS

Figure 53. Interrupt Structure

Figure 60. NAND Tree Test with One Input Stuck High is low, but high only if both are high. together, causing a missing pulse in the output pattern. Figure 61. NAND Tree Test with Two Inputs Shorted conflicts with circuits trying to drive these pins. Writing values to the limit registers.

  • Configuring Pins 3 to 6, and 9 to 12 as fan inputs or GPIO, using Configuration Register 2 (Address 01h).
  • Setting the fan divisors using the fan divisor registers (Addresses 02h and 03h).
  • Configuring the GPIO pins for input/output polarity, using GPIO Configuration Registers 1 to 4 (Addresses 08h to 0Bh) and Bits 6 and 7 of Configuration Register 3. Setting mask bits in Mask Registers 1 to 6 (Addresses 18h to 1Dh) for any inputs that are to be masked out. Setting up Configuration Registers 1 and 3, as described in Table 9 and Table 10.

Table 9. Configuration Register 1 0 Controls the monitoring loop of the ADM1026. 2 Used to clear the INT interrupt output when set high.

3 Configures Pins 27 and 28 as the second external

4 Enables the THERM output when set to 1.

5 Enables automatic fan speed control on the DAC

6 Enables automatic fan speed control on the PWM

7 Performs a soft reset when set to 1. Table 10. Configuration Register 3

0 Configures Pin 42 as GPIO when set to 1 or as THERM

be written to allow subsequent CI detection. 6, 7 Set up GPIO16 for direction and polarity.

Rev. A | Page 34 of 56 Starting Conversion The monitoring function (analog inputs, temperature, and fan speeds) in the ADM1026 is started by writing to Configuration Register 1 and setting Start (Bit 0) high. The INT _Enable (Bit 1) should be set to 1, and INT Clear (Bit 2) set to 0 to enable interrupts. The THERM enable bit (Bit 4) should be set to 1 to enable temperature interrupts at the THERM pin. Apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronized in any way. Reduced Power Mode The ADM1026 can be placed in a low power mode by setting Bit 0 of the configuration register to 0. This disables the internal ADC. Software Reset Function As previously mentioned, the ADM1026 can be reset in software by setting Bit 7 of Configuration Register 1 (Reg. 00h) to 1. Configuration Register 1, 00h, should then be manually cleared. Note that the software reset differs from a power-on reset in that only some of the ADM1026 registers are reinitial- ized to their power-on default values. The registers that are initialized to their default values by the software reset are Configuration Registers (Registers 01h to 0Bh)

  • Mask Registers 1 to 6, internal temperature offset, and Status Registers 4, 5, and 6 (Registers 18h to 25h)
  • All value registers (Registers 1Fh, 20h to 3Fh)
  • External 1 and External 2 Offset Registers (6Eh, 6Fh) Note that the limit registers (0Dh to 12h, 40h to 6Dh) are not reset by the software reset function. This can be useful if one needs to reset the part but does not want to reprogram all parameters again. Note that a power-on reset initializes all registers on the ADM1026, including the limit registers. Application Schematic Figure 62 shows how the ADM1026 could be used in an application that requires system management of a PC or server. Several GPIOs are used to read the VID codes of the CPU. Up to two CPU temperature measurements can be read back. All power supply voltages are monitored in the system. Up to eight fan speeds can be measured, irrespective of whether they are controlled by the ADM1026 or hardwired to a system supply. The V REF output includes the recommended filtering circuitry.

Figure 62. ADM1026 Schematic

Table 11. Address Pointer Register 7–0 Address Pointer Write Address of ADM1026 re gisters. See the following tables for details. Table 12. List of Registers

00 Configuration 1 00h Configur es various operating parameters

01 Configuration 2 00h Configures Pins 3–6 and 9–12 as fan inputs or GPIO

02 Fan 0–3 Divisor 55h Sets oscillator frequency for Fan 0–3 speed measurement

03 Fan 4–7 Divisor 55h Sets oscillator frequency for Fan 4–7 speed measurement

04 DAC Control FFh Contains value for fan speed DAC (analog fan speed control) or minimum

05 PWM Control FFh Contains value for PWM fan speed control or minimum value for automatic

06 EEPROM Register 100h For factory use only

07 Configuration Register 300h Configuration register for THERM, VREF and GPIO16

08 GPIO Config 1 00h Configures GPIO0 to GPIO3 as input or output and as active high or active low

09 GPIO Config 2 00h Configures GPIO4 to GPIO7 as input or output and as active high or active low

10 Int Temp T MIN 28h (40°C) TMIN value for automatic fan speed control based on internal temperature

11 TDM1 T MIN 40h (64°C) TMIN value for automatic fan speed control based on Remote Channel 1 (D1)

12 TDM2 T MIN 40h (64°C) TMIN value for automatic fan speed control based on Remote Channel 2 (D2)

13 EEPROM Register 3 00h Configures EEPROM for read/write/erase, etc.

14 Test Register 1 00h Manufacturer’s test register

15 Test Register 2 00h For manufacturer’s use only

16 Manufacturer’s ID 41h Cont ains manufacturer’s ID code

18 Mask Register 1 00h Interrupt mask regi ster for temperature and supply voltage faults

19 Mask Register 2 00h Interrupt ma sk register for analog input faults

20 Status Register 1 00h Interrupt status regi ster for external temp and supply voltage faults

21 Status Register 2 00h Interrupt st atus register for analog input faults

22 Status Register 3 00h Interrupt status register for fan faults

Rev. A | Page 37 of 56 Hex Address Name Power-On Value Description

24 Status Register 5 00h Interrupt status register for GPIO0 to GPIO7

25 Status Register 6 00h Interrupt status register for GPIO8 to GPIO15

26 V BAT Value 00h Measured value of V BAT

27 A IN8 Value 00h Measured value of A IN8

28 TDM1 Value 00h Measured value of remote temperature channel 1 (D1)

29 TDM2/A IN9 Value 00h Measured value of remo te temperature channel 2 (D2) or AIN9

2A 3.3 V STBY Value 00h Measured value of 3.3 V STBY 2B 3.3 V MAIN Value 00h Measured value of 3.3 V MAIN 2C +5 V Value 00h Measured value of +5 V supply 2D V CCP Value 00h Measured value of processor core voltage 2E +12 V Value 00h Measured value of +12 V supply 2F −12 V Value 00h Measured value of −12 V supply

30 A IN0 Value 00h Measured value of A IN0

31 A IN1 Value 00h Measured value of A IN1

32 A IN2 Value 00h Measured value of A IN2

33 A IN3 Value 00h Measured value of A IN3

34 A IN4 Value 00h Measured value of A IN4

35 A IN5 Value 00h Measured value of A IN5

36 A IN6 Value 00h Measured value of A IN6

37 A IN7 Value 00h Measured value of A IN7

38 FAN0 Value 00h Measured speed of Fan 0

39 FAN1 Value 00h Measured speed of Fan 1

3A FAN2 Value 00h Measured speed of Fan 2 3B FAN3 Value 00h Measured speed of Fan 3 3C FAN4 Value 00h Measured speed of Fan 4 3D FAN5 Value 00h Measured speed of Fan 5 3E FAN6 Value 00h Measured speed of Fan 6 3F FAN7 Value 00h Measured speed of Fan 7

40 TDM1 High Limit 64h (100°C) High limit fo r Remote Temperature Channel 1 (D1) measurement

41 TDM2/A IN9 High Limit 64h (100°C) High limit fo r Remote Temperature Channel 2 (D2) or AIN9 measurement 42 3.3 V STBY High Limit FFh High limit for 3.3 V STBY measurement 43 3.3 V MAIN High Limit FFh High limit for 3.3 V MAIN measurement 44 +5 V High Limit FFh High limit for +5 V supply measurement

45 V CCP High Limit FFh High limit for processor core voltage measurement

46 +12 V High Limit FFh High limit for +12 V supply measurement 47 −12 V High Limit FFh High limit for −12 V supply measurement

48 TDM1 Low Limit 80h Low limit for Remo te Temperature Channel 1 (D1) measurement

49 TDM2/A IN9 Low Limit 80h Low limit for Remo te Temperature Channel 2 (D2) or AIN9 measurement

4A 3.3 V STBY Low Limit 00h Lo w limit for 3.3 V STBY measurement 4B 3.3 V MAIN Low Limit 00h Lo w limit for 3.3 V MAIN measurement 4C +5 V Low Limit 00h Low limit for +5 V supply 4D V CCP Low Limit 00h Low limit for pr ocessor core voltage measurement 4E +12 V Low Limit 00h Low limit for +12 V supply measurement 4F −12 V Low Limit 00h Low limit for −12 V supply measurement

50 A IN0 High Limit FFh High limit for A IN0 measurement

51 A IN1 High Limit FFh High limit for A IN1 measurement

52 A IN2 High Limit FFh High limit for A IN2 measurement

53 A IN3 High Limit FFh High limit for A IN3 measurement

54 A IN4 High Limit FFh High limit for A IN4 measurement

55 A IN5 High Limit FFh High limit for A IN5 measurement

56 A IN6 High Limit FFh High limit for A IN6 measurement

57 A IN7 High Limit FFh High limit for A IN7 measurement

58 A IN0 Low Limit 00h Low limit for A IN0 measurement

59 A IN1 Low Limit 00h Low limit for A IN1 measurement

60 FAN0 High Limit FFh High limit fo r Fan 0 speed measurement (no low limit)

61 FAN1 High Limit FFh High limit fo r Fan 1 speed measurement (no low limit)

62 FAN2 High Limit FFh High limit fo r Fan 2 speed measurement (no low limit)

63 FAN3 High Limit FFh High limit fo r Fan 3 speed measurement (no low limit)

64 FAN4 High Limit FFh High limit fo r Fan 4 speed measurement (no low limit)

65 FAN5 High Limit FFh High limit fo r Fan 5 speed measurement (no low limit)

66 FAN6 High Limit FFh High limit fo r Fan 6 speed measurement (no low limit)

67 FAN7 High Limit FFh High limit fo r Fan 7 speed measurement (no low limit)

Table 13. Register 00h, Configuration Register 1 (Power-On Default 00h) 1 Int Enable = 0 R/W When this bit is set, the INT output pin is enabled. may be set again on the next monitoring cycle. 3 Enable Voltage/Ext2 = 0 R/W When this bit is 1, th e ADM1026 monitors voltage (AIN8 and AIN9) on Pins 28 and 27, respectively. 0 to it. For more info, see the Software Reset Function section.

Table 14. Register 01h, Configuration Register 2 (Power-On Default 00h) Table 15. Register 02h, Fans 0 to 3 Fan Divisor Register (Power-On Default 55h) Table 16. Register 03h, Fans 4 to 7 Fan Divisor Register (Power-On Default 55h) Table 17. Register 04h, DAC Control Register (Power-On Default FFh) 4 MSBs contain the minimum fan speed in auto fan speed control mode.

Table 18. Register 05h, PWM Control Register (Power-On Default FFh) mode, or the 4 MSBs contain the minimum fan speed in auto fan speed control mode. Table 19. Register 06h, EEPROM Register 1 (Power-On Default 00h) 7–0 Factory Use R/W For factory use only. Do not write to this register. Table 20. Register 07h, Configuration Register 3 (Power-On Default 00h)

0 Enable GPIO16/ THERM = 0 R/W

1 CI Clear = 0 R/W Writing a 1 to this bit clears the CI latch. This bit is cleared by writing a 0 to it. 2 V REF Select = 0 R/W When this bit is 0, VREF (Pin 24) outputs 1.82 V, otherwise, it outputs 2.5 V. 5–3 Unused R Undefined, reads back 0. 6 GPIO16 Direction R/W When this bit is 0, GPIO16 is configured as an input; otherwise, it is an output. 7 GPIO16 Polarity R/W When this bit is 0, GPIO16 is active low; otherwise, it is active high. Table 21. Register 08h, GPIO Configuration Register 1 (Power-On Default 00h) 0 GPIO0 Direction R/W When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output. 1 GPIO0 Polarity R/W When this bit is 0, GPIO0 is active low; otherwise it is active high. 2 GPIO1 Direction R/W When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output. 3 GPIO1 Polarity R/W When this bit is 0, GPIO1 is active low; otherwise it is active high. 4 GPIO2 Direction R/W When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output. 5 GPIO2 Polarity R/W When this bit is 0, GPIO2 is active low; otherwise, it is active high. 6 GPIO3 Direction R/W When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output. 7 GPIO3 Polarity R/W When this bit is 0, GPIO3 is active low; otherwise, it is active high. Table 22. Register 09h, GPIO Configuration Register 2 (Power-On Default 00h) 0 GPIO4 Direction R/W When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output. 1 GPIO4 Polarity R/W When this bit is 0, GPIO4 is active low; otherwise, it is active high. 2 GPIO5 Direction R/W When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output. 3 GPIO5 Polarity R/W When this bit is 0, GPIO5 is active low; otherwise, it is active high. 4 GPIO6 Direction R/W When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output. 5 GPIO6 Polarity R/W When this bit is 0, GPIO6 is active low; otherwise, it is active high. 6 GPIO7 Direction R/W When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output. 7 GPIO7 Polarity R/W When this bit is 0, GPIO7 is active low; otherwise, it is active high.

Table 23. Register 0Ah, GPIO Configuration Register 3 (Power-On Default 00h) 0 GPIO8 Direction R/W When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output. 1 GPIO8 Polarity R/W When this bit is 0, GPIO8 is active low; otherwise, it is active high. 2 GPIO9 Direction R/W When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output. 3 GPIO9 Polarity R/W When this bit is 0, GPIO9 is active low; otherwise, it is active high. 4 GPIO10 Direction R/W When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output. 5 GPIO10 Polarity R/W When this bit is 0, GPIO10 is active low; otherwise, it is active high. 6 GPIO11 Direction R/W When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output. 7 GPIO11 Polarity R/W When this bit is 0, GPIO11 is active low; otherwise, it is active high. Table 24. Register 0Bh, GPIO Configuration Register 4 (Power-On Default 00h) 0 GPIO12 Direction R/W When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output. 1 GPIO12 Polarity R/W When this bit is 0, GPIO12 is active low; otherwise, it is active high. 2 GPIO13 Direction R/W When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output. 3 GPIO13 Polarity R/W When this bit is 0, GPIO13 is active low; otherwise, it is active high. 4 GPIO14 Direction R/W When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output. 5 GPIO14 Polarity R/W When this bit is 0, GPIO14 is active low; otherwise, it is active high. 6 GPIO15 Direction R/W When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output. 7 GPIO15 Polarity R/W When this bit is 0, GPIO15 is active low; otherwise, it is active high. Table 25. Register 0ch, EEPROM Register 2 (Power-On Default 00h) 7–0 Factory Use R For factory use on ly. Do not write to this register. Table 26. Register 0Dh, Internal Temperature THERM Limit (Power-On Default, 37h 55°C) causes the THERM output pin to be asserted. Table 27. Register 0Eh, TDM1 THERM Limit (Power-On Default 50h, 80°C) causes the THERM output pin to be asserted. Table 28. Register 0Fh, TDM2 THERM Limit (Power-On Default 50h, 80°C) causes the THERM output pin to be asserted. Table 29. Register 10h, Internal Temperature TMIN (Power-On Default 28h, 40°C) Table 30. Register 11h, TDM1 Temperature TMIN (Power-On Default 40h, 64°C)

Table 31. Register 12h, TDM2 Temperature TMIN (Power-On Default 40h, 64°C) Table 32. Register 13h, EEPROM Register 3 (Power-On Default 00h) 0 Read R/W Setting this bit puts the EEPROM into read mode. 1 Write R/W Setting this bit puts the EEPROM in write (program) mode. 2 Erase R/W Setting this bit puts the EEPROM into erase mode.

3 Write Protect

can only be cleared by a power-on reset. 5 Test Mode Bit 1 R/W Test mode bits. For factory use only. pulse during repeated EEPROM write or block write operations. Table 33. Register 14h, Manufacturer’s Test Register 1 (Power-On Default 00h) Table 34. Register 15h, Manufacturer’s Test Register 2 (Power-On Default 00h) Table 35. Register 16h, Manufacturer’s ID (Power-On Default 41h) 7–0 Manufacturer’s ID Code R This register contains the manufacturer’s ID code. Table 36. Register 17h, Revision Register (Power-On Default 4xh) 7–4 Major Revision Code R This nibble denotes the gene ration of the device. For the ADM1026, this nibble reads 4h. Table 37. Register 18h, Mask Register 1 (Power-On Default 00h) 0 Ext1 Temp Mask = 0 R/W When this bit is set, interrupts generated on the Ext1 temperature channel are masked out. 1 Ext2 Temp R/W When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out. 2 3.3 V STBY Mask = 0 R/W When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are masked out. 3 3.3 V MAIN Mask = 0 R/W When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are masked out. 4 +5 V Mask = 0 R/W When this bit is set, interrupts generated on the +5 V voltage channel are masked out. 5 V CCP Mask = 0 R/W When this bit is set, interrupts generated on the VCCP voltage channel are masked out. 6 +12 V Mask = 0 R/W When this bit is set, interrupts generated on the +12 V voltage channel are masked out. 7 −12 V Mask = 0 R/W When this bit is set, interrupts generated on the −12 V voltage channel are masked out.

Table 38. Register 19h, Mask Register 2 (Power-On Default 00h) 0 A IN0 Mask = 0 R/W When this bit is set, interrupts generated on the AIN0 voltage channel are masked out. 1 A IN1 Mask = 0 R/W When this bit is set, interrupts generated on the AIN1 voltage channel are masked out. 2 A IN2 Mask = 0 R/W When this bit is set, interrupts generated on the AIN2 voltage channel are masked out. 3 A IN3 Mask = 0 R/W When this bit is set, interrupts generated on the AIN3 voltage channel are masked out. 4 A IN4 Mask = 0 R/W When this bit is set, interrupts generated on the AIN4 voltage channel are masked out. 5 A IN5 Mask = 0 R/W When this bit is set, interrupts generated on the AIN5 voltage channel are masked out. 6 A IN6 Mask = 0 R/W When this bit is set, interrupts generated on the AIN6 voltage channel are masked out. 7 A IN7 Mask = 0 R/W When this bit is set, interrupts generated on the AIN7 voltage channel are masked out. Table 39. Register 1Ah, Mask Register 3 (Power-On Default 00h) 0 FAN0 Mask = 0 R/W When this bit is set, interrupts generated on the FAN0 tach channel are masked out. 1 FAN1 Mask = 0 R/W When this bit is set, interrupts generated on the FAN1 tach channel are masked out. 2 FAN2 Mask = 0 R/W When this bit is set, interrupts generated on the FAN2 tach channel are masked out. 3 FAN3 Mask = 0 R/W When this bit is set, interrupts generated on the FAN3 tach channel are masked out. 4 FAN4 Mask = 0 R/W When this bit is set, interrupts generated on the FAN4 tach channel are masked out. 5 FAN5 Mask = 0 R/W When this bit is set, interrupts generated on the FAN5 tach channel are masked out. 6 FAN6 Mask = 0 R/W When this bit is set, interrupts generated on the FAN6 tach channel are masked out. 7 FAN7 Mask = 0 R/W When this bit is set, interrupts generated on the FAN7 tach channel are masked out. Table 40. Register 1Bh, Mask Register 4 (Power-On Default 00h) 0 Int Temp Mask = 0 R/W When this bit is set, interrupts generated on the internal temperature channel are masked out. 1 V BAT Mask = 0 R/W When this bit is set, interrupts generated on the VBAT voltage channel are masked out. 2 A IN8 Mask = 0 R/W When this bit is set, interrupts generated on the AIN8 voltage channel are masked out. 3 THERM Mask = 0 R/W When this bit is set, interrupts generated from THERM events are masked out. 4 AFC Mask = 0 R/W When this bit is set, interrupts generated from automatic fan control events are masked out. 5 Unused R/W Unused. Reads back 0. 6 CI Mask = 0 R/W When this bit is set, interrupts generated by the chassis intrusion input are masked out. 7 GPIO16 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO16 channel are masked out. Table 41. Register 1Ch, Mask Register 5 (Power-On Default 00h) 0 GPIO0 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO0 channel are masked out. 1 GPIO1 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO1 channel are masked out. 2 GPIO2 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO2 channel are masked out. 3 GPIO3 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO3 channel are masked out. 4 GPIO4 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO4 channel are masked out. 5 GPIO5 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO5 channel are masked out. 6 GPIO6 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO6 channel are masked out. 7 GPIO7 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO7 channel are masked out.

Table 42. Register 1Dh, Mask Register 6 (Power-On Default 00h) 0 GPIO8 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO8 channel are masked out. 1 GPIO9 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO9 channel are masked out. 2 GPIO10 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO10 channel are masked out. 3 GPIO11Mask = 0 R/W When this bit is set, interrupts generated on the GPIO11 channel are masked out. 4 GPIO12 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO12 channel are masked out. 5 GPIO13 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO13 channel are masked out. 6 GPIO14 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO14 channel are masked out. 7 GPIO15 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO15 channel are masked out. Table 43. Register 1Eh, INT Temp Offset (Power-On Default 00h) Table 44. Register 1Fh, INT Temp Measured Value (Power-On Default 00h) 7–0 Int Temp Value R This register contains the measured value of the internal temperature channel. Table 45. Register 20h, Status Register 1 (Power-On Default 00h) result of Ext1 temperature readings going 5°C below Ext1 THERM limit. THERM mode is engaged as a result of Ext2 temperature readings exceeding the Ext2 THERM limit. going 5°C below Ext2 THERM limit.

Table 46. Register 21h, Status Register 2 (Power-On Default 00h) Table 47. Register 22h, Status Register 3 (Power-On Default 00h) 0 FAN0 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1 FAN1 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 2 FAN2 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 3 FAN3 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 4 FAN4 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 5 FAN5 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 6 FAN6 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 7 FAN7 Status 1 = 0 R 1, if FAN0 to FAN7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. Table 48. Register 23h, Status Register 4 (Power-On Default 00h) as a result of internal temperature readings going 5°C below Int THERM limit. disengaged as a result of temperature readings going 5°C below THERM limits on any channel. fan turns off when in automatic fan speed control mode. 5 Unused R Unused. Reads back 0. 6 CI Status = 0 R This bit latches a chassis intrusion event.

Table 49. Register 24h, Status Register 5 (Power-On Default 00h) 1 GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.

Table 50. Register 25h, Status Register 6 (Power-On Default 00h) 1 GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise. Table 51. Register 26h, VBAT Measured Value (Power-On Default 00h) 7–0 V BAT Value R This register contains the measured value of the V BAT analog input channel. Table 52. Register 27h, AIN8 Measured Value (Power-On Default 00h) 7–0 A IN8 Value R This register contains the measured value of the A IN8 analog input channel. Table 53. Register 28h, EXT1 Measured Value (Power-On Default 00h) 7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel. Table 54. Register 29h, EXT2/AIN9 Measured Value (Power-On Default 00h)

Table 55. Register 2Ah, 3.3 V STBY Measured Value (Power-On Default 00h) 7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage. Table 56. Register 2Bh, 3.3 V MAIN Measured Value (Power-On Default 00h) 7–0 3.3 V MAIN Value R This register contains th e measured value of the 3.3 V MAIN voltage. Table 57. Register 2Ch, +5 V Measured Value (Power-On Default 00h) 7–0 +5 V Value R This register contains the meas ured value of the +5 V analog input channel. Table 58. Register 2Dh, VCCP Measured Value (Power-On Default 00h) 7–0 V CCP Value R This register contains the measured value of the V CCP analog input channel. Table 59. Register 2Eh, +12V Measured Value (Power-On Default 00h) 7–0 +12 V Value R This register contains the meas ured value of the +12 V analog input channel. Table 60. Register 2Fh, –12V Measured Value (Power-On Default 00h) 7–0 –12 V Value R This register contains the measured value of the −12 V analog input channel. Table 61. Register 30h, AIN0 Measured Value (Power-On Default 00h) 7–0 A IN0 Value R This register contains the measured value of the A IN0 analog input channel. Table 62. Register 31h, AIN1 Measured Value (Power-On Default 00h) 7–0 A IN1 Value R This register contains the measured value of the A IN1 analog input channel. Table 63. Register 32h, AIN2 Measured Value (Power-On Default 00h) 7–0 A IN2 Value R This register contains the measured value of the A IN2 analog input channel. Table 64. Register 33h, AIN3 Measured Value (Power-On Default 00h) 7–0 A IN3 Value R This register contains the measured value of the A IN3 analog input channel. Table 65. Register 34h, AIN4 Measured Value (Power-On Default 00h) 7–0 A IN4 Value R This register contains the measured value of the A IN4 analog input channel. Table 66. Register 35h, AIN5 Measured Value (Power-On Default 00h) 7–0 A IN5 Value R This register contains the measured value of the A IN5 analog input channel. Table 67. Register 36h, AIN6 Measured Value (Power-On Default 00h) 7–0 A IN6 Value R This register contains the measured value of the A IN6 analog input channel. Table 68. Register 37h, AIN7 Measured Value (Power-On Default 00h) 7–0 A IN7 Value R This register contains the measured value of the A IN7 analog input channel.

Table 69. Register 38h, FAN0 Measured Value (Power-On Default 00h) 7–0 FAN0 Value R This register contains the meas ured value of the FAN0 tach input channel. Table 70. Register 39h, FAN1 Measured Value (Power-On Default 00h) 7–0 FAN1 Value R This register contains the meas ured value of the FAN1 tach input channel. Table 71. Register 3Ah, FAN2 Measured Value (Power-On Default 00h) 7–0 FAN2 Value R This register contains the meas ured value of the FAN2 tach input channel. Table 72. Register 3Bh, FAN3 Measured Value (Power-On Default 00h) 7–0 FAN3 Value R This register contains the meas ured value of the FAN3 tach input channel. Table 73. Register 3Ch, FAN4 Measured Value (Power-On Default 00h) 7–0 FAN4 Value R This register contains the meas ured value of the FAN4 tach input channel. Table 74. Register 3Dh, FAN5 Measured Value (Power-On Default 00h) 7–0 FAN5 Value R This register contains the meas ured value of the FAN5 tach input channel. Table 75. Register 3Eh, FAN6 Measured Value (Power-On Default 00h) 7–0 FAN6 Value R This register contains the meas ured value of the FAN6 tach input channel. Table 76. Register 3Fh, FAN7 Measured Value (Power-On Default 00h) 7–0 FAN7 Value R This register contains the meas ured value of the FAN7 tach input channel. Table 77. Register 40h, Ext1 High Limit (Power-On Default 64h/100°C) 7–0 Ext1 High Limit R/W This register contains the high limit of the Ext1 Temp channel. Table 78. Register 41h, Ext2/AIN9 High Limit (Power-On Default 64h/100°C) Table 79. Register 42h, 3.3 V STBY High Limit (Power-On Default FFh) 7–0 3.3 V STBY High Limit R/W This register contains the high limit of the 3.3 V STBY analog input channel. Table 80. Register 43h, 3.3 V MAIN High Limit (Power-On Default FFh) 7–0 3.3 V MAIN High Limit R/W This register contains the high limit of the 3.3 V MAIN analog input channel. Table 81. Register 44h, +5 V High Limit (Power-On Default FFh) 7–0 +5 V High Limit R/W This register contains the high limit of the +5 V analog input channel. Table 82. Register 45h, VCCP High Limit (Power-On Default FFh) 7–0 V CCP High Limit R/W This register contains the high limit of the VCCP analog input channel.

Table 83. Register 46h, +12 V High Limit (Power-On Default FFh) 7–0 +12 V High Limit R/W This register contains the high limit of the +12 V analog input channel. Table 84. Register 47h, −12 V High Limit (Power-On Default FFh) 7–0 −12V High Limit R/W This register contains the high limit of the −12 V analog input channel. Table 85. Register 48h, Ext1 Low Limit (Power-On Default 80h) 7–0 Ext1 Low Limit R/W This register contains the low limit of the Ext1 Temp channel. Table 86. Register 49h, Ext2 / AIN9 Low Limit (Power-On-Default 80h) Table 87. Register 4Ah, 3.3 V STBY Low Limit (Power-On Default 00h) 7–0 3.3 V STBY Low Limit R/W This register contains the low limit of the 3.3 V STBY analog input channel. Table 88. Register 4Bh, 3.3 V MAIN Low Limit (Power-On Default 00h) 7–0 3.3 V MAIN Low Limit R/W This register contains the low limit of the 3.3 V MAIN analog input channel. Table 89. Register 4Ch, +5V Low Limit (Power-On Default 00h) 7–0 0+5 V Low Limit R/W This register contains the low limit of the +5 V analog input channel. Table 90. Register 4Dh, VCCP Low Limit (Power-On Default 00h) 7–0 V CCP Low Limit R/W This register contains the low limit of the VCCP analog input channel. Table 91. Register 4Eh, +12V Low Limit (Power-On Default 00h) 7–0 +12 V Low Limit R/W This register contains the low limit of the +12 V analog input channel. Table 92. Register 4Fh, –12V Low Limit (Power-On Default 00h) 7–0 −12 V Low Limit R/W This register contains the low limit of the −12 V analog input channel. Table 93. Register 50h, AIN0 High Limit (Power-On Default FFh) 7–0 A IN0 High Limit R/W This register contains the high limit of the AIN0 analog input channel. Table 94. Register 51h, AIN1 High Limit (Power-On Default FFh) 7–0 A IN1 High Limit R/W This register contains the high limit of the AIN1 analog input channel. Table 95. Register 52h, AIN2 High Limit (Power-On Default FFh) 7–0 A IN2 High Limit R/W This register contains the high limit of the AIN2 analog input channel. Table 96. Register 53h, AIN3 High Limit (Power-On Default FFh) 7–0 A IN3 High Limit R/W This register contains the high limit of the AIN3 analog input channel.

Table 97. Register 54h, AIN4 High Limit (Power-On Default FFh) 7–0 A IN4 High Limit R/W This register contains the high limit of the AIN4 analog input channel. Table 98. Register 55h, AIN5 High Limit (Power-On Default FFh) 7–0 A IN5 High Limit R/W This register co ntains the high limit of the AIN5 analog input channel. Table 99. Register 56h, AIN6 High Limit (Power-On Default FFh) 7–0 A IN6 High Limit R/W This register co ntains the high limit of the AIN6 analog input channel. Table 100. Register 57h, AIN7 High Limit (Power-On Default FFh) 7–0 A IN7 High Limit R/W This register contains the high limit of the AIN7 analog input channel. Table 101. Register 58h, AIN0 Low Limit (Power-On Default 00h) 7–0 A IN0 Low Limit R/W This register contains the low limit of the AIN0 analog input channel. Table 102. Register 59h, AIN1 Low Limit (Power-On Default 00h) 7–0 A IN1 Low Limit R/W This register contains the low limit of the AIN1 analog input channel. Table 103. Register 5Ah, AIN2 Low Limit (Power-On Default 00h) 7–0 A IN2 Low Limit R/W This register contains the low limit of the AIN2 analog input channel. Table 104. Register 5Bh, AIN3 Low Limit (Power-On Default 00h) 7–0 A IN3 Low Limit R/W This register contains the low limit of the AIN3 analog input channel. Table 105. Register 5Ch, AIN4 Low Limit (Power-On Default 00h) 7–0 A IN4 Low Limit R/W This register contains the low limit of the AIN4 analog input channel. Table 106. Register 5Dh, AIN5 Low Limit (Power-On Default 00h) 7–0 A IN5 Low Limit R/W This register contains the low limit of the AIN5 analog input channel. Table 107. Register 5Eh, AIN6 Low Limit (Power-On Default 00h) 7–0 A IN6 Low Limit R/W This register contains the low limit of the AIN6 analog input channel. Table 108. Register 5Fh, AIN7 Low Limit (Power-On Default 00h) 7–0 A IN7 Low Limit R/W This register contains the low limit of the AIN7 analog input channel. Table 109. Register 60h, FAN0 High Limit (Power-On Default FFh) 7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel. Table 110. Register 61h, FAN1 High Limit (Power-On Default FFh) 7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel.

Table 111. Register 62h, FAN2 High Limit (Power-On Default FFh) 7–0 FAN2 High Limit R/W This register contains the high limit of the FAN2 tach channel. Table 112. Register 63h, FAN3 High Limit (Power-On Default FFh) 7–0 FAN3 High Limit R/W This register contains the high limit of the FAN3 tach channel. Table 113. Register 64h, FAN4 High Limit (Power-On Default FFh) 7–0 FAN4 High Limit R/W This register contains the high limit of the FAN4 tach channel. Table 114. Register 65h, FAN5 High Limit (Power-On Default FFh) 7–0 FAN5 High Limit R/W This register contains the high limit of the FAN5 tach channel. Table 115. Register 66h, FAN6 High Limit (Power-On Default FFh) 7–0 FAN6 High Limit R/W This register contains the high limit of the FAN6 tach channel. Table 116. Register 67h, FAN7 High Limit (Power-On Default FFh) 7–0 FAN7 High Limit R/W This register contains the high limit of the FAN7 tach channel. Table 117. Register 68h, Int Temp High Limit (Power-On Default 50h (80°C)) 7–0 Int Temp High Limit R/W This register contains the high limit of the internal temperature channel. Table 118. Register 69h, Int Temp Low Limit (Power-On Default 80h) 7–0 Int Temp Low Limit R/W This register contains the low limit of the internal temperature channel. Table 119. Register 6Ah, VBAT High Limit (Power-On Default FFh) 7–0 V BAT High Limit R/W This register co ntains the high limit of the VBAT analog input channel. Table 120. Register 6Bh, VBAT Low Limit (Power-On Default 00h) 7–0 V BAT Low Limit R/W This register contains the low limit of the VBAT analog input channel. Table 121. Register 6Ch, AIN8 High Limit (Power-On Default FFh) 7–0 A IN8 High Limit R/W This register contains the high limit of the AIN8 analog input channel. Table 122. Register 6Dh, AIN8 Low Limit (Power-On Default 00h) 7–0 A IN8 Low Limit R/W This register contains the low limit of the AIN8 analog input channel.

Table 123. Register 6Eh, Ext1 Temp Offset (Power-On Default 00h) measurement point is moved, if a plug-in card is inserted or removed, and so on. Table 124. Register 6Fh, Ext2 Temp Offset (Power-On Default 00h) measurement point is moved, if a plug-in card is inserted or removed, and so on.

9.00 BSC

0.08 MAX

Figure 63. 48-Lead Thin Plastic Quad Flat Package [LQFP]

Rev. A | Page 55 of 56 ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1026JST 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JST-REEL 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JST-REEL7 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JSTZ-REEL1 0°C to 100°C 48-Lead LQFP ST-48 EVAL-ADM1026EB Evaluation Board 1 Z = Pb-free part.

Rev. A | Page 56 of 56 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the proper ty of their respective owners. C02657-0-3/04(A)