ADM1025 ONSEMI | Alldatasheet
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Preliminary Technical Data ADM1025/ADM1025A ©2008 SCILLC. All rights reserved. Publication Order Number: February 2008 – Rev. P5 ADM1025/D
FEATURES
Up to 8 measurement channels 5 inputs to measure supply voltages V CC monitored internally External temperature measurement with remote diode On-chip temperature sensor 5 digital inputs for VID bits Integrated 100 kΩ pull-ups on VID pins (ADM1025 only) LDCM support I 2C® compatible system management bus (SMBus) Programmable RST output pin Programmable INT output pin Configurable offset for internal/external channel Shutdown mode to minimize power consumption Limit comparison of all monitored values
APPLICATIONS
Network servers and personal computers Microprocessor-based office equipment Test equipment and measuring instruments PRODUCT DESCRIPTION The ADM1025/ADM1025A1 is a complete system hardware monitor for microprocessor-based systems, providing measure- ment and limit comparison of various system parameters. Five voltage measurement inputs are provided for monitoring 2.5 V ,
3.3 V , 5 V , and 12 V power supplies and the processor core
voltage. The ADM1025/ADM1025A can monitor a sixth power supply voltage by measuring its own V CC. One input (two pins) is dedicated to a remote temperature-sensing diode, and an on- chip temperature sensor allows ambient temperature to be monitored. The ADM1025A has open-drain VID inputs while the ADM1025 has on-chip 100 kΩ pull-ups on the VID inputs. Measured values and in/out of limit status can be read out via an I2C compatible serial System Management Bus. The device can be controlled and configured over the same serial bus. The device also has a programmable INT output to indicate undervoltage, overvoltage, and overtemperature conditions. The ADM1025/ADM1025A ’s 3.0 V to 5.5 V supply voltage range, low supply current, and I2C compatible interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics. FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Patent Pending. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
ADM1025/ADM1025A Preliminary Technical Data Rev. P5 | Page 2 of 21| www.onsemi.com TABLE OF CONTENTS
REVISION HISTORY
02/08—Rev P5: Conversion to ON Semiconductor x/07—Rev. C to Rev. D 4/03—Rev. B to Rev. C 10/02—Rev. A to Rev. B 11/99—Revision 0: Initial Version
Preliminary Technical Data ADM1025/ADM1025A Rev. P5 | Page 3 of 21| www.onsemi.com SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, VCC1 3.0 3.30 5.5 V Supply Current, ICC2 1.4 2.5 mA Interface Inactive, ADC Active 32 500 μA Standby Mode TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ±3 °C Resolution 1 °C External Diode Sensor Accuracy ±5 °C ±3 °C 60°C ≤ T A ≤ 100°C; VCC = 3.3 V Resolution 1 °C Remote Sensor Source Current 180 μA High Level 11 μA Low Level ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND AT TENUATORS) Total Unadjusted Error, TUE3 ±2 % Differential Nonlinearity, DNL ±1 LSB Power Supply Sensitivity ±1 %/V Conversion Time (Analog Input or Internal Temperature)4 11.6 ms Conversion Time (External Temperature)4 34.8 ms Input Resistance (2.5 V, 3.3 V, 5 V, 12 V, VCCPIN) 80 140 250 kΩ OPEN-DRAIN DIGITAL OUTPUT ADD/RST/INT/NTO Output Low Voltage, VOL 0.4 V I OUT = −6.0 mA; VCC = 3 V High Level Output Leakage Current, IOH 0.1 1 μA V OUT = VCC; VCC = 3 V RST Pulsewidth 20 45 ms OPEN-DRAIN SERIAL DATABUS OUTPUT (SDA) Output Low Voltage, VOL 0.4 V I OUT = –6.0 mA; VCC = 3 V High Level Output Leakage Current, IOH 0.1 1 μA V OUT = VCC SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.1 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (ADD, VID0–VID4, NTI)5 VID0–VID3 Input Resistance 100 kΩ ADM1025 Only VID4 Input Resistance 300 kΩ ADM1025 Only 100 kΩ ADM1025A Input High Voltage, VIH6 2.1 V Input Low Voltage, VIL6 0.8 V DIGITAL INPUT LEAKAGE CURRENT Input High Current, IIH −1 μA V IN = VCC Input Low Current, IIL +1 μA V IN = 0 Input Capacitance, CIN 5 pF
ADM1025/ADM1025A Preliminary Technical Data Rev. P5 | Page 4 of 21| www.onsemi.com Parameter Min Typ Max Unit Test Conditions/Comments SERIAL BUS TIMING Clock Frequency, fSCLK 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time, tBUF 1.3 μs See Figure 2 Start Setup Time, tSU:STA 600 ns See Figure 2 Start Hold Time, tHD:STA 600 ns See Figure 2 Stop Condition Setup Time, tSU:STO 600 ns See Figure 2 SCL Low Time, tLOW 1.3 μs See Figure 2 SCL High Time, tHIGH 0.6 μs See Figure 2 SCL, SDA Rise Time, tR 300 ns See Figure 2 SCL, SDA Fall Time, tF 300 ns See Figure 2 Data Setup Time, tSU:DAT 100 ns See Figure 2 Data Hold Time, tHD:DAT 300 ns See Figure 2 1 All voltages are measured with respect to GND, unless otherwise specified. 2 Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. 3 TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input protection resistor value between zero and 1 kΩ. 4 Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings. 5 ADD is a three-state input that may be pulled high, low, or left open-circuit. 6 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Figure 2. Diagram for Serial Bus Timing
Table 3. Pin Function Descriptions 1 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 2 SCL Digital Input. Serial bus clock.
3 GND System Ground
serves as the analog input to monitor VCC. Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only). Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only). Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only). Register. It has an on-chip 100 kΩ pull-up resistor (ADM1025 only). initiates NAND tree test mode. 10 D+ Analog Input. Connected to anode of external temperature sensing diode. VIN mode, it has an on-chip voltage attenuator. In VID4 mode, it has an on-chip 300 kΩ pull-up resistor. 12 5V IN Analog Input. Monitors 5 V supply. 13 3.3V IN Analog Input. Monitors 3.3 V supply. 14 2.5V IN Analog Input. Monitors 2.5 V supply. 15 V CCPIN Analog Input. Monitors processor core voltage (0 V to 3.0 V). NAND tree in NAND tree test mode.
Figure 10. Standby Current vs. Temperature
the ADM1025/ADM1025A are performed over the serial bus. monitors the voltage on this pin. sensing transistor may be connected. up default), the VID4 bit in the VID4 register will default to 0. events. These functions are described in more detail later. the function of each register is given in Table 8 to Table 18. Configuration Register: Provides control and configuration. processor can read from these registers. along with their limit values. value written to this register. The ADM1025/ADM1025A has a 7-bit serial bus address. Table 4. Address Selection
If ADD is left open-circuit, the default address will be 0101110. have no effect, unless power is cycled. The serial bus protocol operates as follows. data line SDA while the serial clock line SCL remains high. data will be written to or read from the slave device. master will read from the slave device. one byte and perform the following functions. register selected by the Address Pointer Register. Figure 11. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
- Place the ADM1025/ADM1025A as close as possible to the
CRTs, are avoided, this distance can be four to eight inches. plane under the tracks if possible. Figure 16. Arrangement of Signal Tracks
- Try to minimize the number of copper/solder joints, which
D− path and at the same temperature. voltages are about 3 μV/°C of temperature difference.
- If the distance to the remote sensor is more than eight
will work up to about 6 to 12 feet.
- For really long distances (up to 100 feet) use shielded
twisted pair, such as Belden #8451 microphone cable. introduces about 0.5°C error. result is automatically stored in the appropriate value register. disabled by writing a 0 to Bit 0 of the Configuration Register. can be read out at any time. connect two power supplies together.
standard 510 Ω resistor is suitable. draw a maximum current of approximately 12 mA. located as close as possible to the ADM1025/ADM1025A. limit temperature/voltage events. of the Configuration Register. cleared by issuing an Alert Response Address Call. Table 7. Controlling the Operation of INT 7 of Test Register must be zeros. Pin 16 will be permanently tied low. Figure 17. Using Two ADM1025/ADM1025As on the Same Bus with a
- Master initiates a read operation and sends the Alert
address that must not be used as a specific device address.
- The device whose INT output is low responds to the Alert
Response Address, and the master reads its device address. interrogated in the usual way. with normal SMBus arbitration.
- Once the ADM1025/ADM1025A has responded to the
high, the NAND test mode is invoked. To perform a NAND tree test, all pins are initially driven low. Figure 18. NAND Tree
Preliminary Technical Data ADM1025/ADM1025A Rev. P5 | Page 17 of 21| www.onsemi.com USING THE ADM1025/ADM1025A POWER-ON RESET When power is first applied, the ADM1025/ADM1025A performs a “power- on reset” on several of its registers. Registers whose power-on values are not shown have power-on conditions that are indeterminate. Value and limit registers are reset to 00h on power-up. The ADC is inactive. In most applications, usually the first action after power-on would be to write limits into the Limit Registers. Power-on reset clears or initializes the following registers (the initialized values are shown in Table 9): – Configuration Register – Status Registers #1 and #2 – VID0-3 Register – VID4 Register – Test Register INITIALIZATION Configuration Register Initialization performs a similar, but not identical, function to power-on reset. Configuration Register Initialization is accomplished by setting Bit 7 of the Configuration Register high. This bit automatically clears after being set. USING THE CONFIGURATION REGISTER Control of the ADM1025/ADM1025A is provided through the configuration register. The Configuration Register is used to start and stop the ADM1025/ADM1025A, program the operating modes of Pins 11 and 16, and provide the initialization function described above. Bit 0 of the Configuration Register controls the monitoring loop of the ADM1025/ADM1025A. Setting Bit 0 low stops the monitoring loop and puts the ADM1025/ADM1025A into a low power mode thereby reducing power consumption. Serial bus communication is still possible with any register in the ADM1025/ADM1025A while in low power mode. Setting Bit 0 high starts the monitoring loop. Bit 4 of the Configuration Register causes a low going 20 ms (typ) pulse at the RST pin (Pin 16) when set. This bit is self- clearing. Bit 5 of the Configuration Register selects the operating mode of Pin 11 between the default of 12 V analog input (Bit 5 = 0) and VID4 (Bit 5 = 1). Bit 7 of the Configuration Register is used to start a Configuration Register Initialization when it is set to 1. USING THE OFFSET REGISTER This register contains a twos complement value that is added (or subtracted if the number is negative) to either the internal or external temperature reading. Note that the default value in the offset register is zero, so zero is always added to the temperature reading. The offset register is configured for the external temperature channel by default. It may be switched to the internal channel by setting Bit 0 of the Test Register to 1, setting Bit 6 of the VID Register to 1, and clearing Bit 7 of the VID Register. STARTING CONVERSION The monitoring function of the ADM1025/ADM1025A is started by writing to the Configuration Register and setting Start (Bit 0) high. Limit values should be written into the Limit Registers before starting the ADC to avoid spurious out-of-limit conditions. The time taken to complete the analog measurements depends on how they are configured, as described elsewhere. Once the measurements have been completed, the results can be read from the Value Registers at any time. REDUCED POWER AND SHUTDOWN MODE The ADM1025/ADM1025A can be placed in a low power mode by setting Bit 0 of the Configuration Register to 0. This disables the internal ADC. Full shutdown mode may then be achieved by setting Bit 7 of the VID Register to 1 and Bit 0 of the Test Register to 1. This turns off power to all analog circuits and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. The device will return to its previous state when these bits are reset to zero.
5 V OPERATION
The ADM1025/ADM1025A may be operated with VCC connected to any supply voltage between 3.0 V and 5.5 V , but it should be noted that the device has been optimized for 3.3 V operation. In particular, the internal voltage divider used to measure the supply voltage is optimized for 3.3 V . Powering the device from 5 V will cause the V CC Reading Register (Register 25h) to overrange. In this case, the 5 V measurement should be read from the 5 V Reading Register (Register 23h), instead of the VCC Reading Register. Note also that when the 12 VIN/VID4 pin is programmed to read VID4, due to its internal voltage divider, it will only read V IH = 2.1 V on the 12 VIN/VID4 pin as logic high if the device is being powered from the 3.3 V supply.
Table 8. Address POINTER Register the tables below for detail. Table 9. List of Registers Table 10. Register 40h – Configuration Register
0 START Read/Write Logic 1 enables startup of
1 Reserved Read
2 Reserved Read
3 Reserved Read
4 RESET Read/Write Setting this bit generates a
6 Reserved Read
7 Initialization Read/Write Logic 1 restores power-up
the power-on default is zero.
Table 11. Register 41h – Status Register 1 (Power-On Default
1 V CCP_Error Read-
4 Local Temp
5 Remote
6 Reserved
7 Reserved
Table 12. Register 42h – Status Register 2 (Power-On Default
1 V CC_Error Read-
2 Reserved Read-
3 Reserved Read-
4 Reserved Read-
5 Reserved Read-
6 Remote
remote thermal diode inputs.
7 Reserved Read-
Table 13. Register 47h – VID REGISTER (Power-On Default
6 Offset
7 RST
Table 14. Register 49h – VID4 Register (Power-On Default =
0 VID4 Read VID4 Input (If Selected)
Table 15. Registers 15h–3Dh – Value and Limit Registers Table 16. Register 15h – Manufacturers Test Register
0 Read/Write Used to select RSTor INT
1 Read/Write Used to select RST or INT
to these bits should be zeros. Table 17. Register 3Eh – Company ID device. This register is read-only. Table 18. Register 3Fh – Stepping Table 19. NAND Tree Test Vectors
Figure 19. 16-Lead Shrink Small Outline Package [QSOP] Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.