ADM1024 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
Up to Nine Measurement Channels Inputs Programmable-to-Measure Analog V oltage, Fan Speed or External Temperature External Temperature Measurement with Remote Diode (Two Channels) On-chip Temperature Sensor Five Digital Inputs for VID Bits LDCM Support System Management Bus (SMBus) Chassis Intrusion Detect Interrupt and Overtemperature Outputs Programmable RESET Input Pin Shutdown Mode to Minimize Power Consumption Limit Comparison of All Monitored Values This is a Pb-Free Device*
Applications
Network Servers and Personal Computers Microprocessor-Based Office Equipment Test Equipment and Measuring Instruments *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 29 of this data sheet.
ORDERING INFORMATION
xxx = Specific Device Code # = Pb-Free Package YYWW = Date Code MARKING DIAGRAM TSSOP−24 CASE 948H 1024 ARUZ #YYWW PIN ASSIGNMENT AD1024 (Top View) VID0/IRQ0 VID1/IRQ1 VID2/IRQ2 VID3/IRQ3 VID4/IRQ4 +VCCP1 +2.5VIN/D2+ VCCP2/D2− +5.0VIN +12VIN D1+ D1− NTEST_OUT/ADD THERM SDA SCL FAN1/AIN1 FAN2/AIN2 CI GND VCC INT NTEST_IN/AOUT RESET 241 232 223 214 205 196 187 178 169 1510 1411 1312
Figure 1. Functional Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. Table 2. THERMAL CHARACTERISTICS
Table 3. PIN ASSIGNMENT Address. This pin functions as an output when doing a NAND test. as an interrupt input for fan control. It has an on-chip 100 k/C0087 pullup resistor. 3 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 4 SCL Digital Input. Serial bus clock. Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis Intrusion Latch. 10 /C0109F (electrolytic or tantalum) and 0.1 /C0109F (ceramic) bypass capacitors. 10 INT Digital Output. Interrupt request (open-drain). The output is enabled when Bit 1 of Register 40h is set to 1. The default state is disabled. It has an on-chip 100 k/C0087 pullup resistor. 12 RESET Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulse width. on-chip 100 k/C0087 pullup resistor. 13 D1− Analog Input. Connected to cathode of first external temperature-sensing diode. 14 D1+ Analog Input. Connected to anode of first external temperature-sensing diode. 15 +12 VIN Programmable Analog Input. Monitors 12 V supply. 16 +5.0 VIN Analog Input. Monitors 5.0 V supply. 19 +VCCP1 Analog Input. Monitors first processor core voltage (0 V to 3.6 V). Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k/C0087 pullup resistor. Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k/C0087 pullup resistor. Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k/C0087 pullup resistor. Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k/C0087 pullup resistor. Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k/C0087 pullup resistor.
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1 and 2))
- All voltages are measured with respect to GND, unless otherwise specified.
- Typicals are at T A = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V.
- TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuato rs, including
an external series input protection resistor value between 0 k/C0087 and 1 k/C0087.
- Total monitoring cycle time is nominally m 755 /C0109s + n 33244 /C0109s, where m is the number of channels configured as analog inputs, plus 2
- The total fan count is based on two pulses per revolution of the fan tachometer output.
- Open −drain digital outputs may have an external pullup resistor connected to a voltage lower or higher than VCC (up to 6.5 V absolute maximum).
- All logic inputs except ADD are tolerant of 5.0 V logic levels, even if VCC is less than 5.0 V. ADD is a three-state input that may be connected
to VCC, GND, or left open−circuit.
- Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Figure 2. Serial Bus Timing Diagram
Figure 9. Standby Current vs. Temperature
http://onsemi.com General Description The ADM1024 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial SMBus. The serial bus controller has a hardwired address line for device selection (Pin 1), a serial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (Pin 3), and an input line for the serial clock (Pin 4). All control and programming functions of the ADM1024 are performed over the serial bus. Measurement Inputs Programmability of the measurement inputs makes the ADM1024 extremely flexible and versatile. The device has a 10−bit ADC and nine measurement input pins that can be configured in different ways. Pins 5 and 6 can be programmed as general-purpose analog inputs with a range of 0 V to 2.5 V , or as digital inputs to monitor the speed of fans with digital tachometer outputs. The fan inputs can be programmed to accommodate fans with different speeds and different numbers of pulses per revolution from their tachometer outputs. Pins 13 and 14 are dedicated temperature inputs and may be connected to the cathode and anode of an external temperature sensing diode. Pins 15, 16, and 19 are dedicated analog inputs with on-chip attenuators, configured to monitor 12 V , 5.0 V , and the processor core voltage, respectively. Pins 17 and 18 may be configured as analog inputs with on-chip attenuators to monitor a second processor core voltage and a 2.5 V supply, or they may be configured as a temperature input and connected to a second temperature-sensing diode. The ADC also accepts input from an on-chip band gap temperature sensor that monitors system-ambient temperature. Finally, the ADM1024 monitors the supply from which it is powered, so there is no need for a separate 3.3 V analog input if the chip V CC is 3.3 V . The range of this V CC measurement can be configured for either a 3.3 V or 5.0 V V CC by Bit 3 of the Channel Mode Register. Sequential Measurement When the ADM1024 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in V alue Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out-of-limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT line (Pin 10). Any or all of the Interrupt Status Bits can be masked by appropriate programming of the Interrupt Mask Register. Processor Voltage ID Five digital inputs (VID4 to VID0−Pins 20 to 24) read the processor voltage ID code. These inputs can also be reconfigured as interrupt inputs. The VID pins have internal 100 k/C0087 pullup resistors. Chassis Intrusion A chassis intrusion input (Pin 7) is provided to detect unauthorized tampering with the equipment. RESET A RESET input/output (Pin 12) is provided. Pulling this pin low will reset all ADM1024 internal registers to default values. The ADM1024 can also be programmed to give a low going 45 ms reset pulse at this pin. Analog Output The ADM1024 contains an on-chip, 8-bit DAC with an output range of 0 V to 2.5 V (Pin 11). This is typically used to implement a temperature-controlled fan by controlling the speed of a fan dependent upon the temperature measured by the on-chip temperature sensor. Testing of board level connectivity is simplified by providing a NAND tree test function. The AOUT (Pin 11) also doubles as a NAND test input, while Pin 1 doubles as a NAND tree output. Internal Registers of the ADM1024 A brief description of the ADM1024’s principal internal registers follows. More detailed information on the function of each register is given in Table 10 to Table 23: Configuration Registers: Provide control and configuration. Channel Mode Register: Stores the data for the operating modes of the input channels. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1024, the first byte of data is always a register address, which is written to the Address Pointer Register. Interrupt (INT) Status Registers: Two registers to provide status of each interrupt event. These registers are also mirrored at addresses 4Ch and 4Dh. Interrupt (INT) Mask Registers: Allow masking of individual interrupt sources. Temperature Configuration Register: The configuration of the temperature interrupt is controlled by the lower three bits of this register. VID/Fan Divisor Register: The status of the VID0 to VID4 pins of the processor can be written to and read from these registers. Divisor values for fan speed measurement are also stored in this register.
analog output DAC is stored in this register. Control of the ADM1024 is carried out via the serial bus. under the control of a master device, e.g., ICH.
2 LSBs are determined by the logical states of Pin 1 (NTEST
Table 5. ADD PIN TRUTH TABLE
- ADD is sampled only at powerup, so any changes
made while power is on will have no immediate effect.
- The master initiates data transfer by establishing a
or read from the slave device. master will read from the slave device.
- Data is sent over the serial bus in sequences of
Acknowledge Bit from the slave device. and slave devices can handle.
- When all data bytes have been read or written,
during the low period before the ninth clock pulse. changed without starting a new operation. and perform the following functions. data to be written to the internal data register.
- If the ADM1024’s Address Pointer Register value
to the register. This is shown in Figure 11.
while Pins 15, 16, and 19 are dedicated analog input channels. Their function is unaffected by the Channel Mode Register. programming Bits 0 and 1 of the Channel Mode Register. CC measurement range for either 3.3 V or 5.0 V . of the Channel Mode Register. Table 6. CHANNEL MODE REGISTER (Note 1)
- Power-on Default = 0000 0000
Table 7. A/D OUTPUT CODE VS. VIN
2.5 V , which is the input range of AIN1 and AIN2, but five
inputs and output codes of the ADC. measurement on one of these inputs takes nominally 9.6 ms. Figure 13. Each input circuit consists of an input protection Figure 13. Structure of Analog Inputs
2.5 V Input Precautions
powered off with a 2.5 V input connected. Figure 14. Scaling AIN(1−2) voltage range so it is always positive. Figure 15. Scaling and Offsetting AIN(1−2) a third resistor to set the positive full−scale input voltage. Figure 16. Scaling and Offsetting AIN(1−2)
Table 8. TEMPERATURE DATA FORMAT
- Place the ADM1024 as close as possible to the
distance can be 4 inches to 8 inches.
- Route the D+ and D− tracks close together, in
parallel, with grounded guard tracks on each side.
- Use wide tracks to minimize inductance and
width and spacing is recommended. Figure 18. Arrangement of Signal Tracks
- Try to minimize the number of copper/solder joints,
- Place 0.1/C0032/C0109F bypass and 2200 pF input filter
capacitors close to the ADM1024.
- If the distance to the remote sensor is more than
- For really long distances (up to 100 feet) use
unconnected to avoid ground loops. filter capacitor may be reduced or removed. resistance introduces about 0.5C error. cooled down to a safe temperature. by writing a 0 to Bit 0 of the Configuration Register. value of any input can be read out at any time. internal VCC measurement and internal temperature sensor.
performance but is not mandatory. be located as close as possible to the ADM1024. zeros, which makes Pins 5 and 6 fan inputs. slow rise and fall times typical of fan tachometer outputs. Figure 25. Fan with Tach Pullup to +VCC than 6.5 V , allowing for the voltage tolerance of the Zener. A value of between 3.0 V and 5.0 V is suitable. Figure 26. Fan with Tach. Pullup to Voltage >6.5 V *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 /C0121 VCC. a resistive attenuator may be used, as shown in Figure 28.
2.0 V /C0116VPULLUP /C0032 R2
calculating resistor values. 47 k/C0087. This will give a high input voltage of 3.83 V . Figure 27. Fan with Strong Tach Pullup to >VCC or Figure 28. Fan with Strong Tach Pullup to > VCC or
Figure 29. Fan Speed Measurement fans and the timing relationship of their tachometer pulses. Registers and the most recent value can be read at any time. speed fans, the situation will be different. two tachometer pulses per revolution. of the VID0–3/Fan Divisor Register. Table 9. FAN SPEEDS AND DIVISORS when the measurement exceeds the limit value. synchronized in any other way.
Models—Various sizes available with tachometer output option.
468 Amapola Avenue
generate an interrupt when the system is powered up. 20 ms. This register bit is self-clearing. Figure 30. Chassis Intrusion Detector and Latch Figure 30. Light falling on the photo-transistor when the PC input of N4, resetting the latch. Figure 31. Using the CI Input with a Temperature Sensor Figure 32. As each measurement value is obtained and function of this is described later. Register 1 (INT_Enable) is high, and Bit 3 (INT_Clear) is low. The INT pin has an internal, 100 k/C0087 pullup resistor.
time taken to measure the fan speeds, as described earlier. contents of the Interrupt (INT) Status Registers. is for reading only and has no effect on the interrupt output. Figure 32. Interrupt Register Structure
16 MASK BITS
http://onsemi.com Using the Configuration Registers Control of the ADM1024 is provided through two configuration registers. The ADC is stopped upon powerup, and the INT _Clear signal is asserted, clearing the INT output. The Configuration Registers are used to start and stop the ADM1024; enable or disable interrupt outputs and modes, and provide the initialization function described above. Bit 0 of Configuration Register 1 controls the monitoring loop of the ADM1024. Setting Bit 0 low stops the monitoring loop and puts the ADM1024 into a low power mode thereby reducing power consumption. Serial bus communication is still possible with any register in the ADM1024 while in low power mode. Setting Bit 0 high starts the monitoring loop. Bit 1 of Configuration Register 1 enables or disables the INT Interrupt output. Setting Bit 1 high enables the INT output; setting Bit 1 low disables the output. Bit 2 of Configuration Register 1 enables or disables the THERM output. Setting Bit 1 high enables the INT output; setting Bit 1 low disables the output. Bit 3 of Configuration Register 1 is used to clear the INT interrupt output when set high. The ADM1024 monitoring function will stop until Bit 3 is set low. Interrupt Status register contents will not be affected. Bit 4 of Configuration Register 1 causes a low going 45 ms (typ) pulse at the RESET pin (Pin 12). Bit 6 of Configuration Register 1 is used to clear an interrupt at the THERM output when it is set to 1. Bit 7 of Configuration Register 1 is used to start a Configuration Register Initialization when it is set to 1. Bit 0 of Configuration Register 2 is used to mask temperature interrupts at the INT output when it is set to 1. The THERM output is unaffected by this bit. Bits 1 and 2 of Configuration Register 2 lock the values stored in the Local and Remote Fan Control Registers at addresses 13h and 14h. The values in these registers cannot be changed until a power-on reset is performed. Bit 3 of Configuration Register 2 selects the THERM interrupt mode. The default value of 0 selects one −time mode. Setting this bit to 1 selects ACPI mode. Starting Conversion The monitoring function (analog inputs, temperature, and fan speeds) in the ADM1024 is started by writing to Configuration Register 1 and setting Start (Bit 0) high. The INT _Enable (Bit 1) should be set to 1, and INT Clear (Bit 3) set to 0 to enable interrupts. The THERMenable bit (Bit 2) should be set to 1 and the THERM Clear bit (Bit 6) should be set to 0 to enable temperature interrupts at the THERM pin. Apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronized in any way. The time taken to complete the analog measurements depends on how they are configured, as described elsewhere. The time taken to complete the fan speed measurements depends on the fan speed and the number of tachometer output pulses per revolution. Once the measurements have been completed, the results can be read from the Value Registers at any time. Reduced Power and Shutdown Mode The ADM1024 can be placed in a low power mode by setting Bit 0 of the Configuration Register to 0. This disables the internal ADC. Full shutdown mode may then be achieved by setting Bit 0 of the Test Register to 1. This turns off the analog output and stops the monitoring cycle, if running, but does not affect the condition of any of the registers. The device will return to its previous state when this bit is reset to 0. Application Circuit Figure 37 shows a generic application circuit using the ADM1024. The analog monitoring inputs are connected to the power supplies including two processor core voltage inputs. The VID inputs are connected to the processor voltage ID pins. There are two tachometer inputs from fans, and the analog output is used to control the speed of a third fan. An opto-sensor for chassis intrusion detection is connected to the CI input. Of course, in an actual application, every input and output may not be used, in which case unused analog and digital inputs should be tied to analog or digital ground as appropriate.
Figure 37. Application Circuit
Table 10. ADDRESS POINTER REGISTER 7–0 Address Pointer W Address of ADM1024 registers. See the following tables for details. Table 11. LIST OF REGISTERS fixed trip point in register 16h will be reached first. fixed trip point in register 17h will be reached first. not write to any other bits in this register. VID4 as processor voltage ID or interrupt inputs. = 70C Read Only. Cannot be changed. = 85C Read Only. Cannot be changed.
37h Ext. Temp1 High Limit Indeterminate Stores high limit for a diode sensor connected to Pins 13 and 14. 38h Ext. Temp1 Low Limit Indeterminate Stores low limit for a diode sensor connected to Pins 13 and 14. 39h Internal Temp. High Limit Indeterminate Stores the high limit for the internal temperature reading. 3Ah Internal Temp. Low Limit Indeterminate Stores the low limit for the internal temperature reading. Table 12. REGISTER 16H, CHANNEL MODE REGISTER (POWER-ON DEFAULT, 00H) Pin 5 as AIN1. Power−on default = 0. Pin 6 as AIN2. Power−on default = 0. temperature−sensing diode. Power−on default = 0. to 3.3 V. Setting this bit to 1 sets the internal VCC measurement range to 5.0 V.
4 IRQ0 EN R/W Setting this bit to 1 enables Pin 24 as an active high interrupt input, provided Pins 20
Register. Power−on default = 0.
5 IRQ1 EN R/W Setting this bit to 1 enables Pin 23 as an active high interrupt input, provided Pins 20
Register. Power−on default = 0.
6 IRQ2 EN R/W Setting this bit to 1 enables Pin 22 as an active high interrupt input, provided Pins 20
Register. Power−on default = 0. this bit to 1 configures Pins 20 to 24 as interrupt inputs. Power−on default = 0.
Table 13. REGISTER 40H, CONFIGURATION REGISTER 1 (POWER-ON DEFAULT, 08H) into the ADM1024 prior to turning on this bit (Power−On Default = 0). 1 INT_Enable R/W Logic 1 enables the INT_output. 1 = Enabled 0 = Disabled (Power−On Default = 0).
2 THERM
self−clearing and power−on default is 0.
5 Reserved R/W Default = 0
6 THERM CLR R/W A 1 clears the THERM output without changing the Status Register contents.
7 Initialization R/W Logic 1 restores power−on default values to the Configuration Register, Interrupt
Table 14. REGISTER 41H, INTERRUPT STATUS REGISTER 1 (POWER-ON DEFAULT, 00H) Read only A 1 indicates that a High or Low limit has been exceeded. 1 VCCP1 Error Read only A 1 indicates that a High or Low limit has been exceeded. 2 VCC Error Read only A 1 indicates that a High or Low limit has been exceeded. 3 5.0 V Error Read only A 1 indicates that a High or Low limit has been exceeded. 6 FAN1/AIN1 Error Read only A 1 indicates that a High or Low limit has been exceeded. 7 FAN2/AIN2 Error Read only A 1 indicates that a High or Low limit has been exceeded. Table 15. REGISTER 42H, INTERRUPT STATUS REGISTER 2 (POWER-ON DEFAULT, 00H) (Note 1 and 2) 0 12 V Error Read only A 1 indicates a High or Low limit has been exceeded. 1 VCCP2 Error Read only A 1 indicates a High or Low limit has been exceeded. 2 Reserved Read only Undefined. 3 Reserved Read only Undefined. 4 Chassis Error Read only A 1 indicates Chassis Intrusion has gone high. 5 THERM Interrupt Read only Indicates that THERM pin has been pulled low by an external source. 6 D1 Fault Read only Short or Open−Circuit Sensor Diode D1. 7 D2 Fault Read only Short or Open−Circuit Sensor Diode D2.
- Any time the Status Register is read out, the conditions (i.e., Register) that are read are automatically reset. In the case of the channel priority
- In the Mask Register, the errant voltage interrupt may be disabled until the operator has time to clear the errant condition or set the limit
Table 16. REGISTER 43H, INT INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT, 00H) 0 2.5 V/Ext. Temp2 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 1 VCCP1 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 2 VCC R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 3 5.0 V R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 4 Int. Temp R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 5 Ext. Temp1 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 6 FAN1/AIN1 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 7 FAN2/AIN2 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. Table 17. REGISTER 44H, INT INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT, 00H) 0 12 V R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 1 VCCP2 R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 2 Reserved R/W Powerup Default Set to Low. 3 Reserved R/W Powerup Default Set to Low. 4 CI R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 5 THERM (Input) R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 6 D1 Fault R/W A 1 disables the corresponding interrupt status bit for INT interrupt. 7 D2 Fault R/W A 1 disables the corresponding interrupt status bit for INT interrupt. Table 18. REGISTER 46H, CHASSIS INTRUSION CLEAR (POWER-ON DEFAULT, 00H) 0–6 Reserved Read only Undefined, always reads as 00h. register bit clears itself after the pulse has been output. Table 19. REGISTER 47H, VID0−3/FAN DIVISOR REGISTER (POWER-ON DEFAULT, 0101(VID3−0)) 4–5 FAN1 Divisor R/W Sets counter prescaler for FAN1 speed measurement. 6–7 FAN2 Divisor R/W Sets counter prescaler for FAN2 speed measurement. Table 20. REGISTER 49H, VID4/DEVICE ID REGISTER (POWER-ON DEFAULT, 1000000(VID4))
0 VID4 Read only VID4 Input from Pentium
Table 21. REGISTER 4AH, CONFIGURATION REGISTER 2 (POWER-ON DEFAULT, [7:0] = 0X00H) output will still be generated, regardless of the setting of this bit.
1 Ambient Temp Fan
until a reset is performed (either POR, Hard Reset, or Soft Reset).
2 Remote Temp Fan
is performed (either POR, Hard Reset, or Soft Reset). 3 THERM R/W If this bit is 0, the THERM output operates in default mode. Interrupt Mode If this bit is 1, the THERM output operates in ACPI mode.
6 IRQ3 EN R/W Setting this bit to 1 enables Pin 21 as an active high interrupt input, provided Pins 20
Register. Power−on default = 0.
7 IRQ4 EN R/W Setting this bit to 1 enables Pin 20 as an active high interrupt input, provided Pins 20
Register. Power−on default = 0. Table 22. REGISTER 4CH, INTERRUPT STATUS REGISTER 1 MIRROR (POWER-ON DEFAULT, [7:0] = 00H) 0 2.5 V/Ext. Temp2 Error Read only A 1 indicates that a High or Low limit has been exceeded. 1 VCCP1 Error Read only A 1 indicates that a High or Low limit has been exceeded. 2 VCC Error Read only A 1 indicates that a High or Low limit has been exceeded. 3 5.0 V Error Read only A 1 indicates that a High or Low limit has been exceeded. 6 FAN1/AIN1 Error Read only A 1 indicates that a High or Low limit has been exceeded. 7 FAN2/AIN2 Error Read only A 1 indicates that a High or Low limit has been exceeded. Table 23. REGISTER 4DH, INTERRUPT STATUS REGISTER 2 MIRROR (POWER-ON DEFAULT, [7:0] = 00H) (Note 1) 0 12 V Error Read only A 1 indicates a High or Low limit has been exceeded. 1 VCCP2 Error Read only A 1 indicates a High or Low limit has been exceeded. 2 Reserved Read only Undefined. 3 Reserved Read only Undefined. 4 Chassis Error Read only A 1 indicates Chassis Intrusion has gone high. 5 THERM Interrupt Read only Indicates that THERM pin has been pulled low by an external source. 6 D1 Fault Read only Short or Open−Circuit Sensor Diode D1. 7 D2 Fault Read only Short or Open−Circuit Sensor Diode D2.
- An error that causes continuous interrupts to be generated may be masked in its respective mask register, until the error can be alleviated.
Table 24. ORDERING INFORMATION Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb-Free part.
http://onsemi.com PACKAGE DIMENSIONS
24 LEAD TSSOP
CASE 948H−01 ISSUE A DIM MIN MAX MIN MAX INCHESMILLIMETERS A 7.70 7.90 0.303 0.311 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. /C0095/C0095/C0095/C0095 SU0.15 (0.006) T 2X L/2 SUM0.10 (0.004) V ST L −U− SEATING PLANE 0.10 (0.004) −T− ÇÇÇ ÇÇÇ SECTION N−N DETAIL E J K ÉÉÉ ÉÉÉ DETAIL E F M −W− 0.25 (0.010) 1324 121 PIN 1 IDENT. HG A D C B SU0.15 (0.006) T −V− 24X REFK N N ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 ADM1024/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative