ADM1024

Analog Devices

System Hardware Monitor with Remote Diode Thermal Sensing REV.0

Manufacturer: Analog Devices

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM1024 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 System Hardware Monitor with Remote Diode Thermal Sensing FUNCTIONAL BLOCK DIAGRAM ADDRESS POINTER REGISTER TEMPERATURE CONFIGURATION REGISTER 10-BIT ADC NTEST OUT/ADD SDA SCL 2.5V BANDGAP REFERENCE INPUT ATTENUATORS AND ANALOG MULTIPLEXER BANDGAP TEMPERATURE SENSOR VID0–3 AND FAN DIVISOR REGISTER VID4 AND DEVICE ID REGISTER 100k/H9024 PULLUPS V CC VCC +5VIN D1+ D1– GND ADM1024 FAN SPEED COUNTER +12VIN CONFIGURATION REGISTERS INTERRUPT STATUS REGISTERS VALUE AND LIMIT REGISTERS LIMIT COMPARATORS SERIAL BUS INTERFACE CHANNEL MODE REGISTER CHASSIS INTRUSION CLEAR REGISTER INT MASK REGISTERS INTERRUPT MASKING ANALOG OUTPUT REGISTER AND 8-BIT DAC VCC VCC CI THERM INT NTEST IN/AOUT RESET VID0/IRQ0 VID1/IRQ1 VID2/IRQ2 VID3/IRQ3 VID4/IRQ4 CCP1 +2.5VIN/D2+ FAN1/AIN1 VCCP2/D2– FAN2/AIN2 POWER TO CHIP 100k/H9024 VCC 100k/H9024 100k/H9024

FEATURES

Up to Nine Measurement Channels Inputs Programmable-to-Measure Analog Voltage, Fan Speed or External Temperature External Temperature Measurement with Remote Diode (Two Channels) On-Chip Temperature Sensor Five Digital Inputs for VID Bits LDCM Support System Management Bus (SMBus) Chassis Intrusion Detect Interrupt and Over Temperature Outputs Programmable RESET Input Pin Shutdown Mode to Minimize Power Consumption Limit Comparison of all Monitored Values PRODUCT DESCRIPTION The ADM1 024 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. Eight measurement inputs are provided, of which three are dedicated to monitoring 5 V and 12 V power supplies and the processor core voltage. The ADM1024 can monitor a fourth power-supply voltage by measuring its own V CC. One input (two pins) is dedicated to a remote temperature-sensing diode. Two further pins can be (continued on page 7 )

APPLICATIONS

Network Servers and Personal Computers Microprocessor-Based Ofﬁce Equipment Test Equipment and Measuring Instruments

–2– REV. 0 ADM1024–SPECIFICATIONS1, 2 (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted) Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, VCC 2.8 3.30 5.5 V Supply Current, ICC 1.4 2.6 mA Interface Inactive, ADC Active 1.0 mA ADC Inactive, DAC Active 45 145 µA Shutdown Mode TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ±3 °C0 °C ≤ TA ≤ 100°C ±2 °CT A = 25°C Resolution ±1 °C External Diode Sensor Accuracy ±5 °C0 °C ≤ TA ≤ 100°C ±3 °C2 5 °C Resolution ±1 °C Remote Sensor Source Current 80 110 150 µA High Level 4 6.5 9 µA Low Level ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE (12 V IN) ±4 % (See Note 3) TUE (AIN, VCCP, 2.5 VIN, 5 VIN) ±3% Differential Nonlinearity, DNL ±1 LSB Power Supply Sensitivity ±1 %/V Conversion Time (Analog Input or Int. Temp) 754.8 856.8 µs0 °C ≤ TA ≤ 100°C4 Conversion Time (External Temperature) 9.6 ms (See Note 4) Input Resistance (2.5 V, 5 V, 12 V, V CCP1, VCCP2) 100 140 200 k Ω Input Resistance (AIN1, AIN2) 5 M Ω ANALOG OUTPUT Output Voltage Range 0 2.5 V Total Unadjusted Error, TUE ±3% I L = 2 mA Full-Scale Error ±1 ±5% Zero-Scale Error 2 LSB No Load Differential Nonlinearity, DNL ±1 LSB Monotonic by Design Integral Nonlinearity ±1 LSB Output Source Current 2 mA Output Sink Current 1 mA FAN RPM-TO-DIGITAL CONVERTER Accuracy ±12 % 0 °C ≤ TA ≤ 100°C Full-Scale Count 255 FAN1 and FAN2 Nominal Input RPM 5 8800 rpm Divisor = 1, Fan Count = 153 4400 rpm Divisor = 2, Fan Count = 153 2200 rpm Divisor = 3, Fan Count = 153 1100 rpm Divisor = 4, Fan Count = 153 Internal Clock Frequency 19.8 22.5 25.2 kHz 0 °C ≤ TA ≤ 100°C DIGITAL OUTPUTS NTEST_OUT Output High Voltage, V OH 2.4 V I OUT = +3.0 mA, VCC = 2.85 V – 3.60 V Output Low Voltage, V OL 0.4 V I OUT = –3.0 mA, VCC = 2.85 V – 3.60 V OPEN-DRAIN DIGITAL OUTPUTS (See Note 6) (INT, THERM, RESET) Output Low Voltage, V OL 0.4 V I OUT = –3.0 mA, VCC = 3.60 V High Level Output Current, I OH 0.1 100 µAV OUT = VCC RESET and CI Pulsewidth 20 45 ms OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, V OL 0.4 V I OUT = –3.0 mA, VCC = 2.85 V – 3.60 V High Level Output Current, I OH 0.1 100 µAV OUT = VCC

1All voltages are measured with respect to GND, unless otherwise speciﬁed. 2Typicals are at T A = 25°C and represent most likely parametric norm. Shutdown current typ is measured with V CC = 3.3 V. protection resistor value between zero and 1 k Ω. measurement and internal temperature sensor, and n is the number of channels conﬁgured as external temperature channels (D1 and D2). 5The total fan count is based on two pulses per revolution of the fan tachometer output. 6Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than V CC (up to 6.5 V absolute maximum). 7All logic inputs except ADD are tolerant of 5 V logic levels, even if VCC is less than 5 V. ADD is a three-state input that may connected to VCC, GND, or left open-circuit. 8Timing speciﬁcations are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.2 V for a rising edge. Speciﬁcations subject to change without notice. Figure 1. Diagram for Serial Bus Timing

–4– REV. 0 ABSOLUTE MAXIMUM RATINGS * Voltage on AOUT, N TEST_OUT ADD, 2.5 V IN/D2+ Voltage on Any Other Input or Output Pin . . –0.3 V to +6.5 V Maximum Junction Temperature (T Lead Temperature, Soldering *Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS 24-Lead Small Outline Package: θJA = 50°C/W, θJC = 10°C/W. ORDERING GUIDE Temperature Package Package Model Range Description Option ADM1024ARU 0 °C to 100°C 24-Lead TSSOP RU-24 PIN CONFIGURATION TOP VIEW (Not to Scale) ADM1024 NTEST OUT/ADD VID0/IRQ0 THERM VID1/IRQ1 SDA VID2/IRQ2 SCL VID3/IRQ3 FAN1/AIN1 VID4/IRQ4 FAN2/AIN2 +V CCP1 CI +2.5V IN/D2+ GND V CCP2/D2– VCC +5VIN INT +12VIN NTEST IN/AOUT D1+ RESET D1–

–5–REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 NTEST _OUT/ADD Digital I/O. Dual Function pin. This is a three-state input that controls the 2 LSBs of the Serial Bus Address. This pin functions as an output when doing a NAND test. 2 THERM Digital I/O. Dual Function pin. This pin functions as an interrupt output for temperature interrupts only, or as an interrupt input for fan control. It has an on-chip 100 k Ω pull-up resistor. 3 SDA Digital I/O. Serial Bus bidirectional Data. Open-drain output. 4 SCL Digital Input. Serial Bus Clock. 5 FAN1/AIN1 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V CC) amplitude fan tachometer input. 6 FAN2/AIN2 Pro grammable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V CC) amplitude fan tachometer input. 7 CI Digital I/O. An active high input from an external latch which captures a Chassis Intrusion event. This line can go high without any clamping action, regardless of the powered state of the ADM1024. The ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line, to reset the external Chassis Intrusion Latch. 8 GND System Ground. 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors. 10 INT Digital Output. Interrupt Request (open-drain). The output is enabled when Bit 1 of Register 40h is set to 1. The default state is disabled. It has an on-chip 100 k Ω pull-up resistor. 11 NTEST_IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND Test mode board-level connectivity testing. Refer to section on NAND testing. Also functions as a programmable analog output when NAND Test is not selected. 12 RESET Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulsewidth. Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power-on reset). It has an on-chip 100 kΩ pull-up resistor. 13 D1– Analog Input. Connected to cathode of ﬁrst external temperature sensing diode. 14 D1+ Analog Input. Connected to anode of ﬁrst external temperature sensing diode. 15 +12 V IN Programmable Analog Input. Monitors 12 V supply. 16 +5 V IN Analog Input. Monitors 5 V supply. 17 V CCP2/D2– Programmable Analog Input. Monitors second processor core voltage or cathode of second external temperature sensing diode. 18 +2.5 V IN/D2+ Progr ammable Analog Input. Monitors 2.5 V supply or anode of second external temperature sensing diode. 19 +V CCP1 Analog Input. Monitors 1st processor core voltage (0 V to 3.6 V). 20 VID4/IRQ4 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status Regis- ter. Can also be reconﬁgured as an interrupt input. It has an on-chip 100 k Ω pull-up resistor. 21 VID3/IRQ3 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconﬁgured as an interrupt input. It has an on-chip 100 k Ω pull-up re sistor. 22 VID2/IRQ2 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0-VID3 Status Register. Can also be reconﬁgured as an interrupt input. It has an on-chip 100 k Ω pull-up resistor. 23 VID1/IRQ1 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconﬁgured as an interrupt input. It has an on-chip 100 k Ω pull-up resistor. 24 VID0/IRQ0 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconﬁgured as an interrupt input. It has an on-chip 100 k Ω pull-up resistor.

processor core voltage, or as a second temperature sensing input. analog inputs or as digital fan-speed measuring inputs.

2.5 V supply, or they may be conﬁgured as a temperature input

and connected to a second temperature-sensing diode. ture sensor that monitors system-ambient temperature. interrupt on the INT line (Pin 10). priate programming of the Interrupt Mask Register. The VID pins have internal 100 k /H9024 pull-up resistors. tampering with the equipment. The RESET pin has an internal, 100 k Ω pull-up resistor. measured by the on-chip temperature sensor. a NAND test input, while Pin 1 doubles as a NAND tree output. of each register is given in Tables VI to XIX. Figure 8. Standby Current vs. Temperature

–8– REV. 0 Conﬁguration Registers: Provide control and conﬁguration. Channel Mode Register: Stores the data for the operating modes of the input channels. Address Pointer Register:This register contains the address that selects one of the other internal registers. When writing to the ADM1024, the ﬁrst byte of data is always a register address, which is written to the Address Pointer Register. Interrupt (INT) Status Registers: Two registers to provide status of each Interrupt event. These registers are also mirrored at addresses 4Ch and 4Dh. Interrupt (INT) Mask Registers: Allow masking of individual interrupt sources. Temperature Conﬁguration Register: The conﬁguration of the temperature interrupt is controlled by the lower three bits of this register. VID/Fan Divisor Register: The status of the VID0 to VID4 pins of the processor can be written to and read from these reg- isters. Divisor values for fan-speed measurement are also stored in this register. Value and Limit Registers: The results of analog voltage inputs, temperature and fan speed measurements are stored in these registers, along with their limit values. Analog Output Register: The code controlling the analog output DAC is stored in this register. Chassis Intrusion Clear Register: A signal latched on the chassis intrusion pin can be cleared by writing to this register. SERIAL BUS INTERFACE Control of the ADM1024 is carried out via the serial bus. The ADM1024 is connected to this bus as a slave device, under the control of a master device, e.g., ICH. The ADM1024 has a 7-bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The ﬁve MSBs of the address are set to 01011, the two LSBs are determined by the logical states of Pin 1 (NTESTOUT/ADD). This is a three-state input that can be grounded, connected to V CC or left open-circuit to give three different addresses. Table I. ADD Pin Truth Table ADD Pin A1 A0 GND 1 0 No Connect 0 0 VCC 01 If ADD is left open-circuit the default address will be 0101100. ADD is sampled only at power-up, so any changes made while power is on will have no immediate effect. The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM1024 is used in a system. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, deﬁned as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit ad dress (MSB ﬁrst) plus an R/ W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ m ode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADM1024, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The ﬁrst byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in Figure 9a. The device address is sent over the bus followed by R/W set to 0. This is followed by two data b ytes. The ﬁrst data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. When reading data from a register there are two possibilities: 1. If the ADM1024’s Address Pointer Register value is unknown or not the desired value, it is ﬁrst necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADM1024 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. This is shown in Figure 9b.

–10– REV. 0 Table II. Channel Mode Register Channel Mode Register Bit Controls Pin(s) Function 0 5 0 = FAN1, 1 = AIN1 1 6 0 = FAN2, 1 = AIN2 2 17, 18 0 = 2.5 V, V CCP2, 1 = D2–, D2+ 3 Int. V CC Meas. 0 = 3.3 V, 1 = 5 V 4 24 0 = VID0, 1 = IRQ0 5 23 0 = VID1, 1 = IRQ1 6 22 0 = VID2, 1 = IRQ2 7 20–24 0 = VID0 to VID4, 1 = Interrupt Inputs Power-on Default = 0000 0000 Table III. A/D Output Code vs. V IN Input Voltage A/D Output +12 VIN +5 VIN VCC (3.3 V) V CC (5 V) +2.5 V IN +VCCP1/2 AIN(1/2) Decimal Binary

ment on one of these inputs takes nominally 9.6 ms.

Each input circuit consists of an input protection diode,

ﬁlter which gives the input immunity to high frequency noise. Figure 10. Structure of Analog Inputs

2.5 V INPUT PRECAUTIONS

become forward-biased if Pin 18 is more than 0.3 V above V CC. AIN1 and AIN2 can easily be scaled to voltages other than 2.5 V. that is required is an input attenuator, as shown in Figure 11. Figure 11. Scaling AIN(1–2) Figure 12. Scaling and Offsetting AIN(1–2) for Negative voltage to fall and give a lower output code from the ADC. upper and lower limits will be transposed. positive full-scale input voltage. Figure 13. Scaling and Offsetting AIN(1–2) for Bipolar Inputs when VIN = plus full-scale).

Figure 15. Arrangement of Signal Tracks

Try to minimize the number of copper/solder joints, which

path and at the same temperature. them, thermocouple voltages should be much less than 200 mV.

Place 0.1 µF bypass and 2200 pF input ﬁlter capacitors close
If the distance to the remote sensor is more than 8 inches, the
For really long distances (up to 100 feet) use shielded twisted

tance introduces about 0.5 °C error. esis or Low Limit, which will usually be some degrees lower. cooled down to a safe temperature. a 0 to Bit 0 of the Conﬁguration Register. internal VCC measurement and internal temperature sensor. toring chips that employ slower ADCs. inputs begins at the same time as monitoring of the analog inputs. more details see Fan Speed Measurement section. dard 510 Ω resistor is suitable. a maximum current of approximately 24 mA.

attenuator may be used, as shown in Figure 17d.

2 V < V

will give a high-input voltage of 3.83 V. tach period and inversely proportional to the fan speed. Figure 18. Fan Speed Measurement speed of the fans and the timing relationship of their tach pulses. ments will be updated as long as the monitoring cycle continues. producing two output pulses per revolution. the VID 0–3/Fan Divisor Register.

three tach periods of FAN2 at the lowest normal fan speed. Models—Various sizes available with tach output option.

468 Amapola Avenue

CI input will generate an interrupt when the system is powered up.

Microswitch that opens or closes when the cover is removed.
Reed switch operated by magnet ﬁxed to the cover.
Hall-effect switch operated by magnet ﬁxed to the cover.
Phototransistor that detects light when cover is removed. The chassis intrusion interrupt will remain asserted until the external detection circuit is reset. This can be achieved by setting Bit 7 of the Chassis Intrusion Clear Register to one, which will cause the CI pin to be pulled low for at least 20 ms. This regis- ter bit is self-clearing. The chassis intrusion circuit should be designed so that it can be reset by pulling its output low. A suitable chassis intrusion circuit using a phototransistor is shown in Figure 19. Light falling on the phototransistor when the PC cover is removed will cause it to turn on and pull up the input of N1, thus setting the latch N3/N4. After the cover is replaced, a low reset on the CI output will pull down the input of N4, resetting the latch. 74HC132 100k/H9024 10k/H9024 CI MRD901 470k/H9024 1N914 CMOS BACKUP BATTERY 1N914

Figure 19. Chassis Intrusion Detector and Latch output is inverted by Q1 to make it compatible with the CI input. Figure 20. Using the CI Input with a Temperature Sensor sion latch and reset it when the ADM1024 was powered down. The Interrupt Structure of the ADM1024 is shown in Figure 21. set that bit high or low as appropriate.

16 MASK BITS

Figure 21. Interrupt Register Structure temperature interrupts only, the THERM input/output Pin 2. The function of this is described later. (INT_Enable) is high, and Bit 3 (INT_Clear) is low. The INT pin has an internal, 100 k Ω pull-up resistor. serviced, or the interrupt request will be reasserted. of the Interrupt (INT) Status Registers.

–21–REV. 0 USING THE CONFIGURATION REGISTERS Control of the ADM1024 is provided through two conﬁguration registers. The ADC is stopped upon power-up, and the INT_Clear signal is asserted, clearing the INT output. The Conﬁguration Registers are used to start and stop the ADM1024; enable or dis- able interrupt outputs and modes, and provide the initialization function described above. Bit 0 of Conﬁguration Register 1 controls the monitoring loop of the ADM1024. Setting Bit 0 low stops the monitoring loop and puts the ADM1024 into a low power mode thereby reducing power consumption. Serial bus communication is still possible with any register in the ADM1024 while in low-power mode. Setting Bit 0 high starts the monitoring loop. Bit 1 of Conﬁguration Register 1 enables or disables the INT Interrupt output. Setting Bit 1 high enables the INT output, setting Bit 1 low disables the output. Bit 2 of Conﬁguration Register 1 enables or disables the THERM output. Setting Bit 1 high enables the INT output, setting Bit 1 low disables the output. Bit 3 of Conﬁguration Register 1 is used to clear the INT inter- rupt output when set high. The ADM1024 monitoring function will stop until Bit 3 is set low. Interrupt Status register contents will not be affected. Bit 4 of Conﬁguration Register 1 causes a low-going 45 ms (typ) pulse at the RESET pin (Pin 12). Bit 6 of Conﬁguration Register 1 is used to clear an interrupt at the THERM output when it is set to 1. Bit 7 of Conﬁguration Register 1 is used to start a Conﬁguration Register Initialization when it is set to 1. Bit 0 of Conﬁguration Register 2 is used to mask temperature interrupts at the INT output when it is set to 1. The THERM output is unaffected by this bit. Bits 1 and 2 of Conﬁguration Register 2 lock the values stored in the Local and Remote Fan Control Registers at addresses 13h and 14h. The values in these registers cannot be changed until a power-on reset is performed. Bit 3 of Conﬁguration Register 2 selects the THERM interrupt mode. The default value of 0 selects one-time mode. Setting this bit to 1 selects ACPI mode. STARTING CONVERSION The monitoring function (analog inputs, temperature, and fan speeds) in the ADM1024 is started by writing to Conﬁguration Register 1 and setting Start (Bit 0), high. The INT_Enable (Bit 1) should be set to 1, and INT Clear (Bit 3) set to 0 to enable interrupts. The THERM enable bit (Bit 2) should be set to 1 and the THERM Clear bit (Bit 6) should be set to 0 to enable temperature interrupts at the THERM pin. Apart from initially starting together, the analog measurements and fan speed mea- surements proceed independently, and are not synchronized in any way. The time taken to complete the analog measurements depends on how they are conﬁgured, as described elsewhere. The time taken to complete the fan speed measurements depends on the fan speed and the number of tach output pulses per revolution. Once the measurements have been completed, the results can be read from the Value Registers at any time. REDUCED POWER AND SHUTDOWN MODE The ADM1024 can be placed in a low-power mode by setting Bit 0 of the Conﬁguration Register to 0. This disables the inter- nal ADC. Full shutdown mode may then be achieved by setting Bit 0 of the Test Register to 1. This turns off the analog output and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. The device will return to its previous state when this bit is reset to zero. APPLICATION CIRCUIT Figure 25 shows a generic application circuit using the ADM1024. The analog monitoring inputs are connected to the power supplies including two processor core voltage inputs. The VID inputs are connected to the processor voltage ID pins. There are two tach inputs from fans, and the analog output is used to control the speed of a third fan. An opto-sensor for chassis intrusion detection is connected to the CI input. Of course, in an actual application, every input and output may not be used, in which case unused analog and digital inputs should be tied to analog or digital ground as appropriate.

Figure 25. Application Circuit

–23–REV. 0 ADM REGISTERS Table VI. Address Pointer Register Bit Name R/ W Description 7–0 Address Pointer Write Address of ADM1024 Registers. See the tables below for detail. Table VII. List of Registers Hex Power-On Value Address Description (Binary Bit 7–0) Notes 13h Internal Temperature = 70 °C Can be written only if the write once bit in Conﬁguration Hardware Trip Point Register 2 has not been set. Values higher than 70 °C will have no affect as the ﬁxed trip point in register 16h will be reached ﬁrst. 14h External Temp = 85 °C Can be written only if the write once bit in Conﬁguration Hardware Trip Point Register 2 has not been set. Values higher than 85 °C will have no affect as the ﬁxed trip point in register 17h will be reached ﬁrst. 15h Test Register 0000 00X0 Setting Bit 0 of this register to 1 selects shutdown mode. Caution: Do not write to any other bits in this register. 16h Channel Mode Register 0000 0000 This register conﬁgures the input channels and conﬁgures VID0 to VID as processor voltage ID or interrupt inputs. 17h Internal Temperature = 70 °C Read Only. Cannot be changed. Fixed Hardware Trip Point 18h External Temperature = 85 °C Read Only. Cannot be changed. Fixed Hardware Trip Point 19h Programmed Value of Analog Output 1111 1111 1Ah AIN1 Low Limit Indeterminate 1Bh AIN2 Low Limit Indeterminate 20h 2.5 V Measured Value/EXT Temp2 Indeterminate Read Only. 21h V CCP1 Measured Value Indeterminate Read Only. 22h V CC Measured Value Indeterminate Read Only. 23h 5 V Value Indeterminate Read Only. 24h 12 V Measured Value Indeterminate Read Only. 25h V CCP2 Measured Value Indeterminate Read Only 26h Ext. Temp1 Value Indeterminate Read Only. Stores the measurement from a diode sensor connected to Pins 13 and 14. 27h Internal Temperature Value Indeterminate Read Only. This register is used to store eight bits of the internal temperature reading. 28h FAN1/AIN1 Value Indeterminate Read Only. Stores FAN1 or AIN1 reading depending on the conﬁguration of Pin 5. 29h FAN2/AIN1 Value Indeterminate Read Only. Stores FAN2 or AIN2 reading depending on the conﬁguration of Pin 6. 2Ah Reserved Indeterminate 2Bh 2.5 V/Ext. Temp2 High Limit Indeterminate Stores high limit for 2.5 V input or, in temperature mode, this register stores the high limit for a diode se nsor con- nected to Pins 17 and 18. 2Ch 2.5 V/Ext. Temp2 Low Limit Indeterminate Stores low limit for 2.5 V input or, in temperature mode, this register stores the low limit for a diode sensor con- nected to Pins 17 and 18. 2Dh V CCP1 High Limit Indeterminate 2Eh V CCP1 Low Limit Indeterminate 2Fh V CC High Limit Indeterminate 30h V CC Low Limit Indeterminate 31h 5 V High Limit Indeterminate 32h 5 V Low Limit Indeterminate 33h 12 V High Limit Indeterminate 34h 12 V Low Limit Indeterminate

–24– REV. 0 Table VII (continued) Hex Power-On Value Address Description (Binary Bit 7–0) Notes 35h V CCP2 High Limit Indeterminate 36h V CCP2 Low Limit Indeterminate 37h Ext Temp1. High Limit Indeterminate Stores high limit for a diode sensor connected to Pins 13 and 14. 38h Ext Temp1. Low Limit Indeterminate Stores low limit for a diode sensor connected to Pins 13 and 14. 39h Internal Temp. High Limit Indeterminate Stores the high limit for the internal temperature reading. 3Ah Internal Temp. Low Limit Indeterminate Stores the low limit for the internal temperature reading. 3Bh AIN1/FAN1 High Limit Indeterminate Stores high limit for AIN1 or FAN1, depending on the conﬁguration of Pin 5. 3Ch AIN2/FAN2 High Limit Indeterminate Stores high limit for AIN2 or FAN2, depending on the conﬁguration of Pin 6. 3Dh Reserved Indeterminate 3Eh Company ID Number 0100 0001 This location will contain the company identiﬁcation number (Read Only). 3Fh Revision Number 0001 nnnn Last four bits of this location will contain the revision number of the part. (Read Only) 40h Conﬁguration Register 1 0000 1000 See Table IX. 41h Interrupt INT Status Register 1 0000 0000 See Table X. 42h Interrupt INT Status Register 2 0000 0000 See Table XI. 43h INT Mask Register 1 0000 0000 See Table XII. 44h INT Mask Register 2 0000 0000 See Table XIII. 46h Chassis Intrusion Clear Register 0000 0000 See Table XIV. 47h VID 0–3/Fan Divisor Register 0101 (VID3–VID0) See Table XV. 49h VID4 Register 1000 000 (VID4) See Table XVI. 4Ah Conﬁguration Register 2 0000 0000 See Table XVII. 4Ch Interrupt Status Register 0000 0000 See Table XVIII. Mirror No. 1 4Dh Interrupt Status Register 0000 0000 See Table XIX. Mirror No. 2 Table VIII. Register 16h, Channel Mode Register (Power-On Default = 00h) Bit Name R/ W Description 0 FAN1/AIN1 R/ W Clearing this bit to 0 conﬁgures Pin 5 as FAN1 input. Setting this bit to 1 conﬁgures Pin 5 as AIN1. Power-on default = 0. 1 FAN2/AIN2 R/ W Clearing this bit to 0 conﬁgures Pin 6 as FAN2 input. Setting this bit to 1 conﬁgures Pin 6 as AIN2. Power-on default = 0. 2 2.5 V, V CCP/D2 R/ W Clearing this bit to 0 conﬁgures Pins 17 and 18 to measure 2.5 V and V CCP2. Setting this bit to 1 conﬁgures Pins 18 and 19 as an input for a second remote temperature-sensing diode. Power-on default = 0. 3 Int V CC R/W Clearing this bit to 0 sets the measurement range for the internal V CC measurement to 3.3 V. Setting this bit to 1 sets the internal V CC measurement range to 5 V. Power-on default = 0. 4 IRQ0 EN R/ W Setting this bit to 1 enables Pin 24 as an active high interrupt input, provided Pins 20 to 24 have been conﬁgured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0. 5 IRQ1 EN R/ W Setting this bit to 1 enables Pin 23 as an active high interrupt input, provided have been conﬁgured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0. 6 IRQ2 EN R/ W Setting this bit to 1 enables Pin 22 as an active high interrupt input, provided Pins 20 to 24 have been conﬁgured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0. 7 VID/IRQ R/ W Clearing this bit to 0 conﬁgures Pins 20 to 24 as processor voltage ID inputs. Setting this bit to 1 conﬁgures Pins 20 to 24 as interrupt inputs. Power-on default = 0.

–25–REV. 0 Table IX. Register 40h, Conﬁguration Register 1 (Power-On Default = 08h) Bit Name R/ W Description 0 START R/ W Logic 1 enables start-up of ADM1024, logic 0 places it in standby mode. Caution: The outputs of the interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred (see “INT Clear” bit). At start-up, limit checking functions and scanning begins. Note, all high and low limits should be set into the ADM1024 prior to turning on this bit. (Power-Up Default = 0) 1 INT_Enable R/ W Logic 1 enables the INT_output. 1 = Enabled 0 = Disabled (Power-Up Default = 0). 2 THERM R/W 0 = THERM disabled. Enable 1 = THERM enabled. 3 INT_Clear R/ W During Interrupt Service Routine (ISR) this bit is asserted Logic 1 to clear INT ou tput without affecting the contents of the Interrupt Status Register. The device will stop monitoring. It will resume upon clearing of this bit. (Power-Up Default = 0) 4 RESET R/W Setting this bit generates a low-going 45 ms reset pulse at Pin 12. This bit is self-clearing and power- up default is 0. 5 Reserved R/ W Default = 0. 6 THERM CLR R/ W A one clears the THERM output without changing the Status Register contents. 7 Initialization R/ W Logic 1 restores Power-Up default values to the Conﬁguration register, In terrupt status registers, Interrupt Mask Registers, Fan Divisor Register, and the Temperature Conﬁguration Register. This bit automatically clears itself since the power-on default is zero. Table X. Register 41h, Interrupt Status Register 1 (Power-On Default = 00h) Bit Name R/ W Description 0 2.5 V/External Temp2 Error Read Only A one indicates that a High or Low limit has been exceeded. 1V CCP1 Error Read Only A one indicates that a High or Low limit has been exceeded. 2V CC Error Read Only A one indicates that a High or Low limit has been exceeded. 3 5 V Error Read Only A one indicates that a High or Low limit has been exceeded. 4 Internal Temp Error Read Only A one indicates that a temperature interrupt has been set, or that a High or Low limit has been exceeded. 5 External Temp1 Error Read Only A one indicates that a temperature interrupt has been set, or that a High or Low limit has been exceeded. 6 FAN1/AIN1 Error Read Only A one indicates that a High or Low limit has been exceeded. 7 FAN2/AIN2 Error Read Only A one indicates that a High or Low limit has been exceeded. Table XI. Register 42h, Interrupt Status Register 2 (Power-On Default = 00h) Bit Name R/ W Description 0 12 V Error Read Only A one indicates a High or Low limit has been exceeded. 1V CCP2 Error Read Only A one indicates a High or Low limit has been exceeded. 2 Reserved Read Only Undeﬁned. 3 Reserved Read Only Undeﬁned. 4 Chassis Error Read Only A one indicates Chassis Intrusion has gone high. 5 THERM Interrupt Read Only Indicates that THERM pin has been pulled low by an external source. 6 D1 Fault Read Only Short or open-circuit sensor diode D1. 7 D2 Fault Read Only Short or open-circuit sensor diode D2. NOTES 1. Any time the STATUS Register is read out, the conditions (i.e., Register) that are read are automatically reset. In the case of the channel priority indication, if two or more channels were out of limits, then another indication would automatically be generated if it was not handled during the ISR. 2. In the Mask Register, the errant voltage interrupt may be disabled, until the operator has time to clear the errant condition or set the limit higher/lower.

–26– REV. 0 Table XII. Register 43h, INT Interrupt Mask Register 1 (Power-On Default = 00h) Bit Name R/ W Description 0 2.5 V/Ext. Temp2 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 1V CCP1 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 2V CC Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 3 5 V Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 4 Int. Temp Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 5 Ext. Temp1 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 6 FAN1/AIN1 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 7 FAN2/AIN2 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. Table XIII. Register 44h, INT Mask Register 2 (Power-On Default = 00h) Bit Name R/ W Description 0 12 V Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 1V CCP2 Read/Write A one disables the corresponding interrupt status bit for INT interrupt. 2 Reserved Read/ Write Power-up default set to Low. 3 Reserved Read/ Write Power-up default set to Low. 4 CI Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 5 THERM (Input) Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 6 D1 Fault Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 7 D2 Fault Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. Table XIV. Register 46h, Chassis Intrusion Clear (Power-On Default = 00h) Bit Name R/ W Description 0–6 Reserved Read Only Undeﬁned, always reads as 00h. 7 Chassis Int. Clear Read/ Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The register bit clears itself after the pulse has been output. Table XV. Register 47h, VID0–3/FAN Divisor Register (Power-On Default 0101(VID3–0)) Bit Name R/ W Description 0–3 VID Read The VID[3:0] inputs from processor core power supplies to indicate the operating voltage (e.g., 1.3 V to 3.5 V) 4–5 FAN1 Divisor Read/ Write Sets counter prescaler for FAN1 speed measurement <5:4> = 00 – divide by 1 <5:4> = 01 – divide by 2 <5:4> = 10 – divide by 4 <5:4> = 11 – divide by 8. 6–7 FAN2 Divisor Read/ Write Sets counter prescaler for FAN2 speed measurement <7:6> = 00 – divide by 1 <7:6> = 01 – divide by 2 <7:6> = 10 – divide by 4 <7:6> = 11 – divide by 8. Table XVI. Register 49h, VID4/Device ID Register (Power-On Default 1000000(VID4)) Bit Name R/ W Description 0 VID4 Read Only VID4 Input from Pentium. 1–7 Reserved Read Only Undeﬁned, always reads as 1000 000(VID4).

–27–REV. 0 Table XVII. Register 4AH, Conﬁguration Register 2 (Power-On Default [7:0] = 0x00h) Bit Name R/ W Description 0 Thermal INT Read/Write Setting this bit masks the thermal interrupts for the INT output ONLY. The Mask THERM output will still be generated, regardless of the setting of this bit. 1 Ambient Temp Read/ Write Writing a one to this bit will lock in the values set into the ambient tempera- Fan Control Once ture automatic fan control register 13h. This register will not be able to be Register Write written again until a reset is performed (either POR, Hard or Soft Reset). Once Bit 2 Remote Temp Read/ Write Writing a one to this bit will lock in the values set into the remote tempera- Fan Control Once ture automatic fan control register 14h. This register will not be able to Register Write be written again until a reset is performed (either POR, Hard or Soft Reset). Once Bit 3 THERM Read/Write If this bit is 0 the THERM output operates in default mode. Interrupt Mode If this bit is 1, the THERM output operates in ACPI mode. 4, 5 Reserved Read Only Reserved.

6 IRQ3 EN Read/ Write Setting this bit to 1 enables Pin 21 as an active high interrupt input, provided

Pins 20 to 24 have been conﬁgured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0.

7 IRQ4 EN Read/ Write Setting this bit to 1 enables Pin 20 as an active high interrupt input, provided

Pins 20 to 24 have been conﬁgured as interrupts by setting Bit 7 of the Channel Mode Register. Power-on default = 0. Table XVIII. Register 4Ch, Interrupt Status Register 1 Mirror (Power-On Default <7:0> = 00h) Bit Name R/ W Description 0 2.5 V/Ext. Temp2 Error Read Only A one indicates that a High or Low limit has been exceeded. 1V CCP1 Error Read Only A one indicates that a High or Low limit has been exceeded. 2V CC Error Read Only A one indicates that a High or Low limit has been exceeded. 3 5 V Error Read Only A one indicates that a High or Low limit has been exceeded. 4 Internal Temp Error Read Only A one indicates that a temperature interrupt has been set, or that a High or Low limit has been exceeded. 5 External Temp1 Error Read Only A one indicates that a temperature interrupt has been set, or that a High or Low limit has been exceeded. 6 FAN1/AIN1 Error Read Only A one indicates that a High or Low limit has been exceeded. 7 FAN2/AIN2 Error Read Only A one indicates that a High or Low limit has been exceeded. Table XIX. Register 4DH, Interrupt Status Register 2 Mirror (Power-On Default <7:0> = 00h) Bit Name R/ W Description 0 12 V Error Read Only A one indicates a High or Low limit has been exceeded. 1V CCP2 Error Read Only A one indicates a High or Low limit has been exceeded. 2 Reserved Read Only Undeﬁned. 3 Reserved Read Only Undeﬁned. 4 Chassis Error Read Only A one indicates Chassis Intrusion has gone high. 5 THERM Interrupt Read Only Indicates that THERM pin has been pulled low by an external source. 6 D1 Fault Read Only Short or open-circuit sensor diode D1. 7 D2 Fault Read Only Short or open-circuit sensor diode D2. NOTE An error that causes continuous interrupts to be generated may be masked in its respective mask register, until the error can b e alleviated.

PRINTED IN U.S.A. ADM1024 REV. 0–28– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead TSSOP Package (RU-24) 24 13 121 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.311 (7.90) 0.303 (7.70) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543

Product Information

ADM1024 specifications and overview.

Summary

System Hardware Monitor with Remote Diode Thermal Sensing REV.0

Description

System Hardware Monitor with Remote Diode Thermal Sensing REV.0

Source title ADM1024 Datasheet(PDF) - Analog Devices

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