ADM1021 AD | Alldatasheet
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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM1021 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 Low Cost Microprocessor System Temperature Monitor FUNCTIONAL BLOCK DIAGRAM ON-CHIP TEMP. SENSOR ANALOG MUX 8-BIT A-TO-D CONVERTER LOCAL TEMPERATURE VALUE REGISTER REMOTE TEMPERATURE VALUE REGISTER BUSY RUN/STANDBY LOCAL TEMPERATURE LOW LIMIT COMPARATOR STATUS REGISTER REMOTE TEMPERATURE LOW LIMIT COMPARATOR REMOTE TEMPERATURE HIGH LIMIT COMPARATOR ADDRESS POINTER REGISTER ONE-SHOT REGISTER CONVERSION RATE REGISTER LOCAL TEMPERATURE LOW LIMIT REGISTER LOCAL TEMPERATURE HIGH LIMIT REGISTER REMOTE TEMPERATURE LOW LIMIT REGISTER LOCAL TEMPERATURE HIGH LIMIT COMPARATOR REMOTE TEMPERATURE HIGH LIMIT REGISTER CONFIGURATION REGISTER INTERRUPT MASKING EXTERNAL DIODE OPEN-CIRCUIT SMBUS INTERFACEADM1021 TEST VDD NC GND NC NC TEST ALERT STBY SDATA SCLK ADD0 ADD1GND
FEATURES
Improved Replacement for MAX1617 On-Chip and Remote Temperature Sensing No Calibration Necessary 18C Accuracy for On-Chip Sensor 38C Accuracy for Remote Sensor Programmable Over/Under Temperature Limits Programmable Conversion Rate 2-Wire SMBus Serial Interface Supports System Management Bus (SMBus™) Alert 70 mA Max Operating Current 3 mA Standby Current 3 V to 5.5 V Supply Small 16-Lead QSOP Package
APPLICATIONS
The ADM1021 is a two-channel digital thermometer and under/ over temperature alarm, intended for use in personal computers and other systems requiring thermal monitoring and manage- ment. The device can measure the temperature of a micropro- cessor using a diode-connected PNP transistor, which may be provided on-chip in the case of the Pentium ® II or similar pro- cessors, or can be a low cost discrete NPN/PNP device such as the 2N3904/2N3906. A novel measurement technique cancels out the absolute value of the transistor’s base emitter voltage, so that no calibration is required. The second measurement chan- nel measures the output of an on-chip temperature sensor, to monitor the temperature of the device and its environment. The ADM1021 communicates over a two-wire serial interface compatible with SMBus standards. Under and over temperature limits can be programmed into the devices over the serial bus, and an ALERT output signals when the on-chip or remote temperature is out of range. This output can be used as an inter- rupt, or as an SMBus alert. SMBus is a trademark and Pentium is a registered trademark of Intel Corporation.
–2– REV. 0 ADM1021–SPECIFICATIONS(TA = TMIN to TMAX, VDD = 3.0 V to 3.6 V, unless otherwise noted) Parameter Min Typ Max Units Test Conditions/Comments POWER SUPPLY AND ADC Temperature Resolution 1 °C Guaranteed No Missed Codes Temperature Error, Local Sensor – 1 °C –3 +3 °C Temperature Error, Remote Sensor –3 +3 °CT A = +60°C to +100°C –5 +5 °C Supply Voltage Range 3 3.6 V Note 1 Undervoltage Lockout Threshold 2.5 2.7 2.95 V V DD Input, Disables ADC, Rising Edge Undervoltage Lockout Hysteresis 25 mV Power-On Reset Threshold 0.9 1.7 2.2 V V DD, Falling Edge2 POR Threshold Hysteresis 50 mV Standby Supply Current 3 10 mAV DD = 3.3 V, No SMBus Activity 4 mA SCLK at 10 kHz Average Operating Supply Current 70 90 mA 0.25 Conversions/Sec Rate Auto-Convert Mode, Averaged Over 4 Seconds 160 200 mA 2 Conversions/Sec Rate Conversion Time 65 115 170 ms From Stop Bit to Conversion Complete (Both Channels) Remote Sensor Source Current D+ Forced to D– + 0.65 V 60 90 130 mA High Level 3.5 5.5 8 mA Low Level D-Source Voltage 0.7 V Address Pin Bias Current (ADD0, ADD1) 50 mA Momentary at Power-On Reset SMBUS INTERFACE Logic Input High Voltage, V IH 2.2 V V DD = 3 V to 5.5 V STBY, SCLK, SDATA Logic Input Low Voltage, V IL 0.8 V V DD = 3 V to 5.5 V STBY, SCLK, SDATA SMBus Output Low Sink Current 6 mA SDATA Forced to 0.6 V ALERT Output Low Sink Current 1 mA ALERT Forced to 0.4 V Logic Input Current, I IH, IIL –1 +1 mA SMBus Input Capacitance, SCLK, SDATA 5 pF SMBus Clock Frequency 0 100 kHz SMBus Clock Low Time, t LOW 4.7 mst LOW Between 10% Points SMBus Clock High Time, t HIGH 4 mst HIGH Between 90% Points SMBus Start Condition Setup Time, t SU:STA 4.7 ms SMBus Repeat Start Condition 250 ns Between 90% and 90% Points Setup Time, tSU:STA SMBus Start Condition Hold Time, t HD:STA 4 ms Time from 10% of SDATA to 90% of SCLK SMBus Stop Condition Setup Time, t SU:STO 4 ms Time from 90% of SCLK to 10% of SDATA SMBus Data Valid to SCLK 250 ns Time from 10% or 90% of Rising Edge Time, tSU:DAT SDATA to 10% of SCLK SMBus Data Hold Time, t HD:DAT 0 ms SMBus Bus Free Time, t BUF 4.7 ms Between Start/Stop Condition SCLK Falling Edge to SDATA 1 ms Master Clocking in Data Valid Time, tVD,DAT NOTES 1Operation at V DD = +5 V guaranteed by design, not production tested. 2Guaranteed by design, not production tested. Specifications subject to change without notice.
conditions for extended periods may affect device reliability. 16-Lead QSOP Package: qJA = 150°C/Watt. 2V DD Positive supply, +3 V to +5.5 V.
3 D+ Positive connection to remote tem-
4 D– Negative connection to remote tem-
6 ADD1 Three-state logic input, higher bit of
7, 8 GND Supply 0 V connection.
10 ADD0 Three-state logic input, lower bit of
11 ALERT Open-drain logic output used as
12 SDATA Logic input/output, SMBus serial
14 SCLK Logic input, SMBus serial clock.
15 STBY Logic input selecting normal opera-
tion (high) or standby mode (low). the same potential (i.e., connected together). Figure 1. Diagram for Serial Bus Timing
–7–REV. 0 The power-on default value of the Address Pointer Register is 00h, so if a read operation is performed immediately after power on, without first writing to the Address Pointer, the value of the local temperature will be returned, since its register address is 00h. Value Registers The ADM1021 has two registers to store the results of Local and Remote temperature measurements. These registers are written to by the ADC and can only be read over the SMBus. Status Register Bit 7 of the Status Register indicates that the ADC is busy con- verting when it is high. Bits 5 to 3 are flags that indicate the results of the limit comparisons. If the local and/or remote temperature measurement is above the corresponding high temperature limit or below the corre- sponding low temperature limit, then one or more of these flags will be set. Bit 2 is a flag that is set if the remote temperature sensor is open-circuit. These five flags are NOR’d together, so that if any of them is high, the ALERT interrupt latch will be set and the ALERT output will go low. Reading the Status Register will clear the five flag bits, provided the error conditions that caused the flags to be set have gone away. While a limit com- parator is tripped due to a value register containing an out-of- limit measurement, or the sensor is open-circuit, the corresponding flag bit cannot be reset. A flag bit can only be reset if the corre- sponding value register contains an in-limit measurement, or the sensor is good. The ALERT interrupt latch is not reset by reading the Status Register, but will be reset when the ALERT output has been serviced by the master reading the device address, provided the error condition has gone away and the Status Register flag bits have been reset. Table II. Status Register Bit Assignments Bit Name Function 7 BUSY 1 When ADC Converting. 6 LHIGH* 1 When Local High Temp Limit Tripped. 5 LLOW* 1 When Local Low Temp Limit Tripped. 4 RHIGH* 1 When Remote High Temp Limit Tripped. 3 RLOW* 1 When Remote Low Temp Limit Tripped. 2 OPEN* 1 When Remote Sensor Open-Circuit. 1–0 Reserved. *These flags stay high until the status register is read or they are reset by POR. Configuration Register Two bits of the configuration register are used. If Bit 6 is 0, which is the power-on default, the device is in operating mode with the ADC converting. If Bit 6 is set to 1, the device is in standby mode and the ADC does not convert. Standby mode can also be selected by taking the STBY pin low. Bit 7 of the configuration register is used to mask the ALERT output. If Bit 7 is 0, which is the power-on default, the ALERT output is enabled. If Bit 7 is set to 1, the ALERT output is disabled. Table III. List of ADM1021 Registers READ Address (Hex) WRITE Address (Hex) Name Power-On Default Not Applicable Not Applicable Address Pointer Undefined 00 Not Applicable Local Temp. Value 0000 0000 (00h) 01 Not Applicable Remote Temp. Value 0000 0000 (00h)
02 Not Applicable Status Undefined
03 09 Configuration 0000 0000 (00h) 04 0A Conversion Rate 0000 0010 (02h) 05 0B Local Temp. High Limit 0111 1111 (7Fh) (+127°C) 06 0C Local Temp. Low Limit 1100 1001 (C9h) (–55 °C) 07 0D Remote Temp. High Limit 0111 1111 (7Fh) (+127 °C) 08 0E Remote Temp. Low Limit 1100 1001 (C9h) (–55 °C) Not Applicable 0F
1 One-Shot
10 Not Applicable Reserved Undefined 2
11 13 Reserved Undefined 2 12 14 Reserved Undefined 2 15 16 Reserved 1000 0000 2 17 18 Reserved Undefined 2
19 Not Applicable Reserved 0000 0000 2
FE Not Applicable Manufacturer Device ID 0100 0001 (41h) FF Not Applicable Die Revision Code Undefined NOTES 1Writing to address 0F causes the ADM1021 to perform a single measurement. It is not a data register as such and it does not mat ter what data is written to it. 2These registers are reserved for future versions of the device.
–8– REV. 0 Table IV. Configuration Register Bit Assignments Power-On Bit Name Function Default
7 MASK1 0 = ALERT Enabled 0
1 = ALERT Masked
6 RUN/STOP 0 = Run 0
1 = Standby 5-0 Reserved 0 Conversion Rate Register The lowest three bits of this register are used to program the conversion rate by dividing the ADC clock by 1, 2, 4, 8, 16, 32, 64 or 128, to give conversion times from 125 ms (Code 07h) to 16 seconds (Code 00h). This register can be written to and read back over the SMBus. The higher five bits of this register are unused and must be set to zero. Use of slower conversion times greatly reduces the device power consumption, as shown in Table V. Table V. Conversion Rate Register Codes Average Supply Current Data Conversion/sec mA Typ at VCC = 3.3 V 00h 0.0625 42 01h 0.125 42 02h 0.25 42 03h 0.5 48 04h 1 60 05h 2 82 06h 4 118 07h 8 170 08h to FFh Reserved Limit Registers The ADM1021 has four limit registers to store local and re- mote, high and low temperature limits. These registers can be written to and read back, over the SMBus. The high limit regis- ters perform a > comparison while the low limit registers per- form a < comparison. For example, if the high limit register is programmed as a limit of 80 °C, measuring 81°C will result in an alarm condition. One-Shot Register The one-shot register is used to initiate a single conversion and comparison cycle when the ADM1021 is in standby mode, after which the device returns to standby. This is not a data register as such and it is the write operation that causes the one-shot conversion. The data written to this address is irrelevant and is not stored. SERIAL BUS INTERFACE Control of the ADM1021 is carried out via the serial bus. The ADM1021 is connected to this bus as a slave device, under the control of a master device, e.g., the PIIX4. ADDRESS PINS In general, every SMBus device has a 7-bit device address (except for some devices that have extended, 10-bit addresses). When the master device sends a device address over the bus, the slave device with that address will respond. The ADM1021 has two address pins, ADD0 and ADD1, to allow selection of the device address, so that several ADM1021s can be used on the same bus, and/or to avoid conflict with other devices. Although only two address pins are provided, these are three-state, and can be grounded, left unconnected, or tied to V DD, so that a total of nine different addresses are possible, as shown in Table VI. It should be noted that the state of the address pins is only sampled at power-up, so changing them after power-up will have no effect. Table VI. Device Addresses ADD0 ADD1 Device Address 0 0 0011 000
0 NC 0011 001
1 NC 1001 101
Note: ADD0, ADD1 sampled at power-up only. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDATA, while the serial clock line SCLK remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition and shift in the next eight bits, con- sisting of a 7-bit address (MSB first) plus an R/ W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowl- edge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, then the master will write to the slave device. If the R/ W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop condi- tions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.
- Base-emitter voltage greater than 0.25 V at 6 mA, at the high-
- Base-emitter voltage less than 0.95 V at 100 mA, at the lowest
- Base resistance less than 100 W .
control of Vbe characteristics. package are suitable devices to use. QSOP-16 package is about 10 seconds. due to self-heating will be negligible.
- Place the ADM1021 as close as possible to the remote sens-
this distance can be four to eight inches.
- Route the D+ and D– tracks close together, in parallel, with
under the tracks if possible.
- Use wide tracks to minimize inductance and reduce noise
Figure 17. Arrangement of Signal Tracks
- Try to minimize the number of copper/solder joints, which
path and at the same temperature.
- Place a 0.1 mF bypass capacitor close to the V
- If the distance to the remote sensor is more than eight inches,
- For really long distances (up to 100 feet), use shielded twisted
nected to avoid ground loops. introduces about 0.5°C error.