ADM1014JRU

ADM1014 AD | Alldatasheet

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. /G61 ADM1014 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 REV. PrN 1/02 Preliminary Technical Data Dual PCI Hot-PlugTM Controller FUNCTIONAL BLOCK DIAGRAM TM Hot Plug is a trademark of Core International, Inc. AUXINA VOCSET 100µA OCSET COMMON TO BOTH CHANNELS 3.3VAUX POWER-ON RESET LOW WHEN AUXINA < 2.5V AUXINA 12VGA 12VIN A 5VISENA 5VSA 3VISENA 3VSA 3V5VGA +5V IN +3.3V IN RSENSE3A RSENSE5A +5V OUTA +3.3V OUTA 12VOA -12VGA -12VINA REGULATOR LOW WHEN 12VINA < 10V -12VOA 12VIN A 12V IN POWER-ON RESET GND AUXGA AUXINA AUXOA FLTNA FAUXA PWRONA PAUXONA 12VIN A CIRCUIT OPERATES FROM 3.3VAUX POWER SUPPLY CIRCUIT OPERATES FROM 3.3VAUX AND +12V POWER SUPPLY P-CHANNEL MOSFET D S G FAULT LATCH Q Q RESET SET OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +5V OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3V P-CHANNEL MOSFET D S G OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +12V N-CHANNEL MOSFET D S G OVERCURRENT COMPARATOR FOR -12V FAULT LATCH Q Q RESET SET COMBINING LOGIC COMMON TO BOTH CHANNELS CHANNEL A CHANNEL B ( IDENTICAL TO CHANNEL A ) FLTNB PWRONB PAUXONB 27 12VGB 12VINB 12VOB -12VGB -12VINB 5VISENB 5VSB24 21 3VISENB 3VSB22 -12VOB 3V5VGB AUXGB AUXINB AUXOB EXTERNAL N-CHANNEL POWER MOSFETS EXTERNAL N-CHANNEL POWER MOSFETS 3.3V Cmos Input 3.3V Cmos Output 3030 OVERCURRENT AND UNDERVOLTAGE COMPARATORS FOR +3.3VAUX +5V IN +3.3V IN RSENSE3B RSENSE5B +5V OUTA +3.3V OUTA CHANNEL A +3.3VAux +3.3VAux FAUXB

–2– REV. PrN 1/02 ADM1014–SPECIFICATIONS Parameter Min Typ Max Units Test Conditions/Comments 5V/ 3.3V SUPPLY CONTROL 5V Overcurrent Threshold - 8 - A See Typical Application Diagram 5V Overcurrent Threshold Voltage 33 42 50 mV V OCSET = 0.6V 5V Overcurrent Threshold Voltage 70 80 90 mV V OCSET = 1.2V 5V Undervoltage Trip Threshold 4.42 4.65 4.7 V 5V Undervoltage Fault Response Time - 110 160 ns 5V Turn-On Time - 9.75 - ms C 3V5VG = 0.033µF, C5VOUT = 2000µF, (PWRON High to 5VOUT = 4.75V) R L = 1/H9024 3V Overcurrent Threshold - 10 - A See Typical Application Diagram 3V Overcurrent Threshold Voltage 41 52 62 mV OCSET = 0.6V 3V Overcurrent Threshold Voltage 89 98 108 mV OCSET = 1.2V 3V Undervoltage Trip Threshold 2.74 2.86 2.9 V 3V Undervoltage Fault Response Time - 110 160 ns 3V5VG Undervoltage Enable Threshold - 9.6 - V Voltage 3V Turn-On Time - 9.75 - ms C 3V5VG = 0.033µF, C3VOUT = 2000µF, (PWRON High to 3VOUT = 3.00V) R L = 0.43/H9024 3V5VG Vout High 11.5 11.8 - V PWRON = High, FLTN = High Gate Output Charge Current 19 25.0 29 µA PWRON = High, V 3V5VG = 4V Gate Turn-On Time - 280 - µs C 3V5VG = 0.033µF,3V5VG Rising 10% to 90% (PWRON High to 3V5VG = 11V) Gate Turn-Off Time - 2 - µs C 3V5VG = 0.033µF, 3V5VG Falling 90% to 10% +12V SUPPLY CONTROL On Resistance of Internal PMOS - 0.3 0.35 /H9024PWRON = High, ID = 0.5A, TA= TJ= 25oC On Resistance of Internal PMOS - 0.35 0.5 /H9024PWRON = High, ID = 0.5A, TA= TJ= 70oC Overcurrent Threshold 0.6 0.75 0.9 A V OCSET = 0.6V Overcurrent Threshold 1.25 1.50 1.8 A V OCSET = 1.2V 12V Undervoltage Trip Threshold 10.25 10.6 10.8 V Undervoltage Fault Response Time - 110 - ns (Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, V CC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.)

FEATURES

Controls all Four PCI Supplies, +3.3V, +5V, +12V, -12V, plus 3.3V auxiliary supply Internal MOSFET Switches for +3.3V AUX, +12V and –12V outputs Adjustable Overcurrent Protection for all Outputs Undervoltage Protection on +3.3V, +5V, +12V and +3.3V AUX Supplies Open-Drain Fault Output with Adjustable Delay Logic Control of Outputs Adjustable Soft-start

APPLICATIONS

The ADM1014 is a dual PCI voltage bus controller that allows hot-plugging of adapter cards into and out of an active or pas- sive backplane. The device requires only four external power MOSFETs and a few discrete components for a complete power-control solution for two PCI slots. The ADM1014 operates from a +12V and +3.3V AUX supply and controls five independent supplies (+3.3V, +3.3VAUX, +5V, +12V and –12V) on two separate channels (A and B). The power switches for the +3.3VAUX, +12V and –12V supplies are integrated onto the chip, and internal current limiting is provided. For the +3.3V and +5V supplies, the device drives external, N-channel, power MOSFETs, and provides overcurrent protection by sensing the voltage drop across external current-sense resistors. The current limits for all 10 supplies are set by a single resistor to GND, connected to the OCSET pin. Undervoltage sensing is provided on the +3.3V, +5V, +12V and +3.3VAux supplies. Overcurrent sensing is provided on all supplies. In the event of an overcurrent or undervoltage fault on any of the outputs of either channel, all outputs on that channel will be turned off. Turn-on slew rate may be controlled using eight external capacitors, connected to the gate drives of all of the supplies. Logic control of the four main outputs is provided by the PWRONA and PWRONB pins. When these pins are high, the outputs are turned on, when low, the outputs are turned off. The +3.3VAUX supplies have their own control inputs, PAUXA and PAUXB.

–3–REV. PrN 1/02 ADM1014–SPECIFICATIONS (Continued) (Specifications are for each channel, 3.3VAUX=AUXINA=3.3V, V CC = 12VIN = +12V, -12VIN = -12V, Nominal 3.3V and 5V supplies to external MOSFETs, TA = 0oC to +70oC, unless otherwise noted.) Parameter Min Typ Max Units Test Conditions/Comments Gate Charge Current 19 25.0 29 µA PWRON = High, V 12VG = 10V Turn-On Time - 16 - ms C 12VG = 0.033µF, 12VG Falling 90% - 10% (PWRON High to 12VG = 1V) Turn-Off Time - 4.5 - µs C 12VG = 0.033µF, 12VG Rising 10% - 90% -12V SUPPLY CONTROL On Resistance of Internal NMOS - 0.7 1 /H9024PWRON = High, I D = 0.1A, TA=TJ=25oC On Resistance of Internal NMOS - 1 1.3 /H9024PWRON = High, I D = 0.1A, TA=TJ=70oC Overcurrent Threshold 0.13 0.18 0.25 A V OCSET = 0.6V Overcurrent Threshold 0.23 0.38 0.52 A V OCSET = 1.2V Gate Output Charge Current 19 25 29 µA PWRON = High, V M12VG = -10V Turn-On Time - 16 - ms C M12VG = 0.033µF, CM12VO= 50µF,RL= 120/H9024 (PWRON High to M12VO = -10.8V) Turn-Off Time - 3 - µs C M12VG=0.033µF,M12VG Falling 90% -10% M12VIN Input Bias Current - 2.5 5 mA PWRON = High +3.3VAUX SUPPLY CONTROL On Resistance of Internal PMOS - 0.25 TBD /H9024PAUXON = High, ID = 0.375A, TA=TJ=25oC On Resistance of Internal PMOS - 0.25 TBD /H9024PAUXON = High, ID = 0.375A, TA=TJ=70oC Overcurrent Threshold - 0.5 TBD A V OCSET = 0.6V Overcurrent Threshold - 1.0 TBD A V OCSET = 1.2V 3.3VAUX Undervoltage Trip Threshold - 2.9 TBD V Undervoltage Fault Response Time - 110 - ns Gate Charge Current 19 25.0 29 µA PAUXON = High, V AUXG = 3V Turn-On Time (PAUXON High to AUXG = 1V) - 16 - ms C AUXG = 0.033µF Turn-Off Time - 3 - µs C AUXG = 0.033µF, AUXG Rising 10% - 90% 3.3VAUX Power On Reset Threshold - 2.5 - V AUXIN Voltage Rising CONTROL PINS 12VIN Supply Current - 5.3 8 mA AUXIN Supply Current - 3 TBD mA OCSET Current 93 100 107 µA Overcurrent to Fault Response Time - 500 960 ns PWRONA/B, PAUXA/B Threshold Voltage 1.0 1.6 2.1 V 12V Power On Enable Threshold 9.4 10 10.2 V 12VINA Voltage Rising 12V Power On Reset Threshold 8.9 9.1 9.3 V 12VINA Voltage Falling FAULT O/P PINS /G46/G4C/G54/G41/G2F/G42 Output Low Voltage - 0.5 0.7 V I /G46/G4C/G54 = 2mA /G46/G4C/G54/G41/G2F/G42 Output High Voltage AUXIN-0.5 AUXIN-0.1 - V I /G46/G4C/G54 = 0 /G46/G4C/G54/G41/G2F/G42/G2C/G20Output Latch Threshold TBD 1.6 TBD V I /G46/G4C/G54 High to Low transition /G46/G41/G55/G58/G41/G2F/G42 Output Low Voltage - 0.5 0.7 V I /G46/G41/G55/G58 = 2mA /G46/G41/G55/G58/G41/G2F/G42 Output High Voltage AUXIN-0.5 AUXIN-0.1 - V I /G46/G41/G55/G58 = 0 /G46/G41/G55/G58/G41/G2F/G42 Output Latch Threshold TBD 1.6 TBD V I /G46/G41/G55/G58 High to Low transition NOTES Specifications subject to change without notice.

–4– REV. PrN 1/02 ADM1014–SPECIFICATIONS PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) -12VIN -0.5V to +0.5V Continuous Power Dissipation (T TSSOP (derate 8.3mW/ oC above +70 oC) Operating Temperature Range *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. THERMAL CHARACTERISTICS 38-Pin TSSOP Package: q JA = 100°C/Watt, qJC = 10°C/Watt ORDERING GUIDE Temperature Package Package Model Range Description Option ADM1014JRU 0°C to +70°C 38-Pin TSSOP RU-38 M12VOA M12VGA PWRONA FLTNA FAUXA OCSET AUXGA AUXOA 12VGA 12VOA 12VOB 12VGB AUXOB AUXGB FAUXB FLTNB PWRONB M12VGB M12VOB M12VINA 3VISENA 3VSA 5VISENA 5VSA 3V5VGA GND AUXINA PAUXONA 12VINA 12VINB PAUXONB AUXINB 3V5VGB 5VSB 5VISENB 3VSB 3VISENB M12VINB ADM1014 TOP VIEW (Not to Scale)

–5–REV. PrN 1/02 PIN FUNCTION DESCRIPTION Pin Mnemonic Function 1 M12VOA Switched -12V output for channel A. Rated for 100mA. 2 M12VGA Gate of channel A internal NMOS transistor. A capacitor connected from this pin to -12VOA (pin 1) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. 3 PWRONA Power on control for channel A. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONA high = outputs on, PWRONA low = outputs off. 4 FLTNA Active-low, 5V compatible, Open Drain fault output for channel A. A pull-up resistor connects the pin to 3.3VAux. 4.7k /H9024 is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. 5 FAUXA Active-low, 3.3V compatible, Open Drain fault output for Aux channel A. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. 6 OCSET Overcurrent set for all 10 outputs. A resistor connected from this pin to ground sets the overcurrent trip point of all eight supplies. All eight overcurrent trip-points can be programmed by changing the value of this resistor. The default value of 6.04k /H9024, ±1% is compatible with the maximum currents allowed by the PCI specification. 7 AUXGA Gate of channel A +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOA (pin 8) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25µA current source. 8 AUXOA Switched 3.3V auxiliary output for channel A. Rated for 0.375A. 9 12VGA Gate of channel A internal PMOS transistor. A capacitor connected from this pin to 12VOA (pin 10) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 12VGA rises above 1.2V. If the capacitor on pin 7 (AUXGA) or pin 33 (3V5VGA) is more than 25% larger than the capacitor on pin 9 (12VGA) a false undervoltage condition may be detected during startup. 10 12VOA Switched 12V output for channel A. Rated for 0.5A. 11 12VOB Switched 12V output for channel B. Rated for 0.5A. 12 12VGB Gate of channel B internal PMOS transistor. A capacitor connected from this pin to 12VOB (pin 11) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 12VGB rises above 1.2V. If the capacitor on the pin 25 (3V5VGB) or pin 14 (AUXGB) is more t han 25% larger than the capacitor on pin 12 (12VGB) a false undervoltage condition may be detected during startup. 13 AUXOB Switched 3.3V auxiliary output for channel B. Rated for 0.375A. 14 AUXGB Gate of channel B +3.3VAUX internal PMOS transistor. A capacitor connected from this pin to AUXOB (pin 13) sets the start-up ramp for the +3.3VAUX supply. During turn-on, this capacitor is charged from a 25µA current source. 15 FAUXB Active-low, 3.3V compatible, Open Drain fault output for Aux channel B. The same pull-up resistor as that on FLTNA connects the pin to 3.3VAux. 16 FLTNB Active-low, 5V compatible, Open Drain fault output for channel B. A pull-up resistor connects the pin to 3.3VAux. 4.7k /H9024 is recommended for this function. An optional capacitor may be connected from this pin to GND to provide improved immunity to power supply transients. 17 PWRONB Power on control for channel B. 3.3V CMOS-compatible logic input controls all four main supplies. PWRONB high = outputs on, PWRONB low = outputs off. 18 M12VGB Gate of channel B internal NMOS transistor. A capacitor connected from this pin to -12VOB (pin 19) sets the start-up ramp for the +12V supply. During turn-on, this capacitor is charged from a 25µA current source. 19 M12VOB Switched -12V output for channel B. Rated for 100mA.

–6– REV. PrN 1/02 PIN FUNCTION DESCRIPTION (CONTINUED) Pin Mnemonic Function 20 M12VINB -12V supply input for channel B. Also provides power to the -12V overcurrent circuitry. 21 3VISENB 3.3V current sense for channel B. A current-sensing resistor is connected between this pin and 3VSB (pin 22). Connect to the load side of the current sense resistor. 22 3VSB 3.3V source for channel B. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 21. 23 5VISENB 5V current sense for channel B. A current-sensing resistor is connected between this pin and 5VSB (pin 24). Connect to the load side of the current sense resistor. 24 5VSB 5V source for channel B. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 23. 25 3V5VGB 3.3V and 5V gate output for channel B, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 3V5VGB falls below 12VIN-1.2V. 26 AUXINB +3.3V auxiliary supply input for channel B. 27 PAUXONB Power on control for channel B +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONB high = outputs on, PAUXONB low = outputs off. 28 12VINB Switched +12V supply input for channel B. 29 12VINA Switched +12V supply input for channel A and for OCSET and power-on RESET circuits. 30 PAUXONA Power on control for channel A +3.3V auxiliary output. 3.3V CMOS-compatible logic input. PAUXONA high = outputs on, PAUXONA low = outputs off. 31 AUXINA +3.3V auxiliary supply input for channel A. 32 GND Ground for all chip circuits. Connect to common of power supplies. 33 3V5VGA 3.3V and 5V gate output for channel A, drives the gates of the external 3.3V and 5V MOSFETs. A capacitor connected from this pin to GND sets the start-up ramp for the 3.3V and 5V supplies. During turn-on, this capacitor is charged from a 25µA current source. The undervoltage circuitry is disabled when the voltage on 3V5VGA falls below 12VIN-1.2V. 34 5VSA 5V source for channel A. The source of the 5V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 35. 35 5VISENA 5V current sense for channel A. A current-sensing resistor is connected between this pin and 5VSA (pin 34). Connect to the load side of the current sense resistor. 36 3VSA 3.3V source for channel A. The source of the 3.3V MOSFET is connected to this pin and a current-sensing resistor is connected between this pin and pin 37. 37 3VISENA 3.3V current sense for channel A. A current-sensing resistor is connected between this pin and 3VSA (pin 36). Connect to the load side of the current sense resistor. 38 M12VINA -12V supply input for channel A. Also provides power to the -12V overcurrent circuitry.

Figure 1. Simplified Schematic

–8– REV. PrN 1/02 FUNCTIONAL DESCRIPTION VOLTAGE OUTPUTS The ADM1014 consists of two independent, identical chan- nels, A and B, each of which controls four main power supply voltages and an auxiliary voltage. As the channels are identical, the following description applies to either channel, except where otherwise stated. An on-chip PMOS transistor connected between 12VIN and 12VO switches the +12V supply at currents up to 1.5A, whilst an on-chip NMOS transistor connected between -12VIN and -12VO switches the –12V supply at currents up to 0.38A. The +3.3V and +5V supplies are switched by external, N-channel MOSFETs, whose gate drive is provided by the 3V5VG pins. Using suitable MOSFETs, singly or in parallel, currents of several amps may be switched with very low voltage drops. The four main power supplies may be switched on and off under control of the PWRON pin. The 3.3V auxiliary supply has an on-chip PMOS transistor, which can switch currents at up to 1A. This supply is con- trolled independently of the other four supplies by the PAUXON pin. All five supplies are protected against overcurrent and the four positive supplies are also protected against undervoltage. EXTERNAL CURRENT LIMIT The external power MOSFETs are protected and overcurrent shutdown is provided on the +3.3V and +5V supplies by exter- nal current-sense resistors and on-chip comparators. Current-sensing resistors are connected between the +5V out- put pin and the 5VISEN pin, and between the +3.3V output pin and the 3.3VISEN pin. The sense pins are connected to the inverting inputs of the current-limit comparator directly, while the voltage outputs are connected to the non-inverting inputs via a reference voltage proportional to the voltage on the OCSET pin. This voltage is V OCSET/14.5 in the case of the 5V output and V OCSET/11.5 in the case of the 3.3V output. These values were chosen so that the 3.3V and 5V sense resistors could both be 5m /H9024 in PCI applications. When the voltage drop across the current-sensing resistor ex- ceeds the reference voltage, the output of the comparator will go high, the fault latch will be set and all four main outputs and the auxiliary output on the channel will be turned off. The other main channel and auxiliary channel will remain on. The reference voltages for the current-limit comparators are set by connecting a resistor between the OCSET pin and GND. An on-chip, 100µA current source generates a voltage across this resistor. The current limit may also be adjusted by the choice of current-sensing resistor. I LIMIT(3.3V) = V OCSET/(11.5 /H11003 RSENSE3) = (RSET /H11003 10-4)/(11.5 /H11003 RSENSE3) ILIMIT(5V) = V OCSET/(14.5 /H11003 RSENSE5) = (RSET /H11003 10-4)/(14.5 /H11003 RSENSE5) Where: I LIMIT = current limit in Amps RSET is resistor from OCSET to GND in /H9024 RSENSE is current-sense resistor in /H9024 Note: The OCSET current source obtains its power supply from 12VINA. INTERNAL CURRENT LIMIT The +3.3VAUX, +12V and –12V supplies have the power MOSFET switches on-chip. These devices are protected and overcurrent shutdown is provided by a completely self-contained current sensing system. The output current through the on-chip power MOSFET is tracked at a lower level by a second, smaller MOSFET. The current through this MOSFET is then con- verted to a voltage, which is compared to a reference voltage determined by R SET. In the case of the +12V and -12V outputs, if the current-sense voltage exceeds this reference voltage, the comparator output will go high, the fault latch will be set and all four main outputs and the auxiliary output will be turned off. Similarly in the case of the auxiliary output, if the current- sense voltage exceeds the reference voltage, the comparator output will go high, the fault latch will be set, FAUXN/FLTN will go low, and the auxiliary output and the four main outputs will turn off. The typical internal limiting currents may be calculated as follows: I LIMIT (+3.3VAUX) = V OCSET /1.2 ILIMIT (+12V) = 1.25 /H11003 VOCSET = 1.25 /H11003 10-4 /H11003 RSET ILIMIT (-12V) = V OCSET /3.3 Where: I LIMIT = current limit in Amps RSET is resistor from OCSET to GND in /H9024 Due to tolerances in the current tracking FETs, the variations in the internal current limit are quite wide, typically ±20% of the calculated value for the +12V supply and +35/-20% of the calculated value for the –12V supply. CHOICE OF RSET AND RSENSE Using the above equations, R SET is chosen to set the required current limits for the +3.3VAUX, +12V and -12V supplies. Once R SET has been chosen, R SENSE3 and RSENSE5 can be chosen to set the current limits for the 3.3V and 5V outputs. For PCI applications R SET should be 6.04k /H9024 and the current sense resistors should both be 5m /H9024±1%. This will set the cur- rent limits to the maximum values for the PCI specification. For other applications, the following limits should be noted. 1. The minimum value of R SET is limited by the minimum voltage the current–limit comparators can reliably sense, which is determined by noise, comparator offset voltage and the overdrive required to switch the comparator. The refer- ence voltage set by R SET should not be less than 33mV for the 5V output, which has the smallest reference voltage. The minimum recommended value for R SET is 6k/H9024, which gives a reference voltage of 35mV for the 5V output and 45mV for the 3.3V output. 2. The maximum value of R SET is limited by the junction tem- perature. This is determined by the power dissipated in the on- chip MOSFETs, (which is dependent upon the current passed

oC/W), and the ambient temperature. +3.3VAUX supplies is carried out by four voltage comparators. outputs on the faulting channel will be turned off. FLTN/FAUXN output will return to a high state. halved, as shown in fig. 2 and Table 1. Figure 2. FLTN and 3V5VG Delay TABLE 1. FLT AND 3V5VG DELAY VS. C FLT When PWRON is high, the four main supplies are turned on. Note: the power-on reset circuit monitors 12VINA. +12V and -12V outputs, and from the 3V5VG pin to GND. overcurrent faults at power-on.

Figure 4. Load Board for Typical Application Circuit