ADLD8403 (Rev. D)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 10
Technical content
Ultralow Power, Adaptive Linear Power, Dual-Port ADSL/ADSL2+ Line Driver Data Sheet ADLD8403 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
2 differential DSL channels comprising current feedback, high output current amplifiers with integrated feedback resistors plus biasing network Ideal for use as ADSL/ADSL2+ dual-channel central office (CO) line drivers Low power consumption using Class H technology Single 12.5 V supply operation 20.4 dBm line power, 1:1 transformer Less than 600 mW per channel total power dissipation while driving 20.4 dBm (includes 110 mW line power) Less than 275 mW per channel total power dissipation while driving 14.5 dBm (including line power) High output voltage and current drive
43.4 V differential output voltage swing
−65 dBc typical multitone power ratio (MTPR) at 20.4 dBm, 26 kHz to 2.2 MHz Low cost protection components enable ITU-T-K20 and GR-1089 compliance
APPLICATIONS
ADSL/ADSL2+ CO line drivers INTERNAL SCHEMATIC VEEP VCCPVCC AV = 13V/V VOPA VONA INPA VCOM_A INNA VCC 4kΩ 4kΩ 08848-001 Figure 1. Channel A Internal Schematic The ADLD8403 is available in a 4 mm × 4 mm, 20-lead LFCSP . Figure 2. Outputs and Pumps Time Domain Response, Typical ADSL/ADSL2+
Rev. D | Page 2 of 10 TABLE OF CONTENTS
REVISION HISTORY
3/2017—Rev. C to Rev. D 9/2014—Revision C: Initial Version
Rev. D | Page 3 of 10 SPECIFICATIONS VCC = 12.5 V , RL = 100 Ω, GDIFF = 13 (fixed), PD_A = 0, PD_B = 0, T = 25°C, typical DSL application circuit, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth 8 MHz VOUT = 0.1 V p-p, differential −3 dB Large Signal Bandwidth 8 MHz VOUT = 2 V p-p, differential Differential Gain 12.8 13 13.2 V/V NOISE/DISTORTION PERFORMANCE Multitone Power Ratio (MTPR) −65 dBc 26 kHz to 2.2 MHz, ZLINE = 100 Ω, differential load Differential Output Noise 120 nV/√Hz f = 10 kHz INPUT CHARACTERISTICS Referred to Output (RTO) Offset Voltage <100 mV Single-ended 15 200 mV Differential Input Resistance 8 kΩ Differential Input Capacitance 1 pF Differential OUTPUT CHARACTERISTICS Differential Output Voltage Swing 43.4 V ΔVOUT, RL = 100 Ω POWER SUPPLY Operating Range, Single Supply 11.75 12.5 V Total Quiescent Current Full chip PD_A = 0, PD_B = 0, PD_PMP = 0 35.6 38 mA Pumps are on, both channels active PD_A = 0, PD_B = 0, PD_PMP = 1 22.0 25 mA Pumps are off, both channels active PD_A = 0, PD_B = 1, PD_PMP = 0 21.0 23.5 mA Pumps are on, one channel active PD_A = 0, PD_B = 1, PD_PMP = 1 10.6 13 mA Pumps are off, one channel active PD_A = 1, PD_B = 1 2.5 3.5 mA Pumps are off, both channels inactive Common-Mode Voltage 20 mV With respect to midsupply Threshold PD_A = 0, PD_B = 0 0.8 V PD_A = 1, PD_B = 1 2.4 V Input Current PD_A = 0, PD_B = 0 35 60 µA 0 ≡ 0.8 V PD_A = 1, PD_B = 1 5 10 µA 1 ≡ 2.4 V
15 CAPP
11 CAPN
- CONNECT THE EXPOSED PAD TO THE GND PLANE FOR
Figure 4. Pin Configuration Table 4. Pin Function Descriptions
1 INPA Port A Input P
2 INNA Port A Input N
3 PD_PMP Control for Port A and Port B Pumps
4 INNB Port B Input N
5 INPB Port B Input P
6 VCOM_B Port B VCOM
7 PD_B Port B Shutdown
8 VONB Port B Output N
9 VOPB Port B Output P
10 GND Ground
11 CAPN Pump Capacitor Negative
12 VEEP Dynamic Negative Supply
13 GND Ground
14 VCCP Dynamic Positive Supply
15 CAPP Pump Capacitor Positive
16 VCC Positive Power Supply
17 VOPA Port A Output P
18 VONA Port A Output N
19 PD_A Port A Shutdown
20 VCOM_A Port A VCOM
EPAD Exposed Pad. Connect the exposed pad to the GND plane for the thermal path. No internal electrical connection exists.
supplies to ensure nonsaturation of the output buffer amplifier. architectures using a fixed supply. amplifiers, along with the ALP unit and standard bias block. supplies at the VCCP and VEEP pins. PD pin (PD_A and PD_B), that enables the output buffer. channels require less than 14.5 dBm of line power. Figure 11. Block Diagram
The ADLD8403 is powered from a single 12.5 V power supply. analog and digital circuitry. all differential signal traces as symmetrical as possible. the supply boost necessary to pass the peaks of the xDSL signal. rating of 16 V. Using a dielectric X7R capacitor is recommended. transformer-coupled to the telephone line at the tip and ring. Figure 12. Typical ADSL/ADSL2+ Application Circuit
out-of-band MTPR for the ADLD8403. Figure 13. Out-of-Band MTPR
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
Figure 14. 20-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.