ADL9005

ADL9005 (Rev.A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

Wideband, Low Noise Amplifier, Single Positive Supply, 0.01 GHz to 26.5 GHz Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Single positive supply ►Low noise figure: 2.5 dB typical from 0.01 GHz to 14 GHz ►High gain: 17.5 dB typical from 0.01 GHz to 14 GHz ►OP1dB: 13.5 dBm typical from 0.01 GHz to 20 GHz ►High OIP3: 26 dBm typical from 0.01 GHz to 14 GHz ►RoHS-compliant, 4 mm × 4 mm, LFCSP

APPLICATIONS

►Test instrumentation ►Military ►Communications FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADL9005 is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), wideband, LNA that operates from 0.01 to 26.5 GHz. The ADL9005 provides a typical gain of 17.5 dB from 0.01 GHz to 14 GHz with a positive gain slope from 14 GHz to 20 GHz, a 13.5 dBm typical output power at 1 dB compression (OP1dB) from 0.01 GHz to 20 GHz, a 2.5 dB typical noise figure from 0.01 GHz to 14 GHz, and a typical output third-order intercept (OIP3) of 26 dBm from 0.01 GHz to 14 GHz, requiring only 80 mA from a 5 V supply voltage. The saturated output power (PSAT) of up to 16 dBm enables the LNA to function as a local oscillator (LO) driver for many of Analog Devices, Inc., balanced, inphase/quadrature (I/Q) or image rejection mixers. The ADL9005 also features inputs and outputs (I/Os) that are internally matched to 50 Ω, making it ideal for surface-mounted technology (SMT)-based, high capacity microwave radio applications. The ADL9005 is housed in a RoHS-compliant, 4 mm × 4 mm, LFCSP. Multifunction pin names may be referenced by their relevant func- tion only.

analog.com Rev. A | 2 of 24 Biasing the ADL9005 by Using the LTM8020...21 Providing Drain Bias Through the ACG4/

REVISION HISTORY

9/2022—Rev. 0 to Rev. A 2/2021—Revision 0: Initial Version

analog.com Rev. A | 3 of 24

0.01 GHZ TO 14 GHZ

Drain voltage (VDD) = 5 V, bias voltage (VBIAS) = 5 V, total current (IDQ) = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 0.01 14 GHz GAIN 15.5 17.5 dB Gain Variation Over Temperature 0.0077 dB/°C RETURN LOSS Input 15 dB Output 14 dB OUTPUT OP1dB 11.5 13.5 dBm PSAT 16 dBm OIP3 26 dBm Measurement taken at output power (POUT) per tone = 0 dBm NOISE FIGURE 2.5 dB

14 GHZ TO 20 GHZ

VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 14 20 GHz GAIN 16.5 18.5 dB Gain Variation Over Temperature 0.0127 dB/°C RETURN LOSS Input 15 dB Output 14 dB OUTPUT OP1dB 11 13.5 dBm PSAT 15 dBm OIP3 25 dBm Measurement taken at POUT per tone = 0 dBm NOISE FIGURE 3 dB 20 GHZ TO 26.5 GHZ VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω, and TA = 25°C, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 20 26.5 GHz GAIN 17 19 dB Gain Variation Over Temperature 0.0214 dB/°C RETURN LOSS Input 15 dB Output 14 dB OUTPUT OP1dB 8.5 11.5 dBm PSAT 14 dBm OIP3 22 dBm Measurement taken at POUT per tone = 0 dBm

analog.com Rev. A | 4 of 24 Table 3. Parameter Min Typ Max Unit Test Conditions/Comments NOISE FIGURE 4 dB DC SPECIFICATIONS Table 4. Parameter Min Typ Max Unit VDD 3 5 6 V CURRENT IDQ 80 mA Amplifier (IDQ_AMP) 73.6 mA RBIAS (IDQ_BIAS) 6.4 mA

ing conditions for extended periods may affect product reliability. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 7. ADL9005, 24-Lead LFCSP damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 8. Pin Function Descriptions Table 9. Refer to Figure 74 for the bias resistor connection. See Figure 3 for the interface schematic. 3, 5, 15, 17 GND Ground. The GND pins must be connected to RF and dc ground. See Figure 4 for the interface schematic. 4 RFIN RF Input. The RFIN pin is dc-coupled and matched to 50 Ω. See Figure 5 for the interface schematic. capacitor value. See Figure 5 for the interface schematic. capacitor value. See Figure 5 for the interface schematic. 6 for the interface schematic. capacitor value. See Figure 6 for the interface schematic. 74 for the capacitor value. See Figure 6 for the interface schematic. with RFOUT/VDD. See Figure 6 for the interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.

Figure 19. Output Return Loss vs. Frequency at Various VDD, IDQ = 80mA,

0.01 GHz to 28 GHz

Figure 20. Reverse Isolation (S12) vs. Frequency for Various Temperatures,

10 MHz to 200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω

Figure 21. Reverse Isolation vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 Figure 22. Output Return Loss vs. Frequency for Various Bias Resistor Figure 23. Reverse Isolation vs. Frequency for Various Temperatures, 0.2 Figure 24. Reverse Isolation vs. Frequency for Various Bias Resistor Values

Figure 25. Noise Figure vs. Frequency for Various Temperatures, 10 MHz to

200 MHz, VDD = 5 V, VBIAS = 5 V, IDQ = 80 mA, RBIAS = 300 Ω

Figure 26. Noise Figure vs. Frequency for Various VDD, IDQ = 80 mA, 10 MHz Figure 27. Noise Figure vs. Frequency for Various Bias Resistor Values and Figure 28. Noise Figure vs. Frequency for Various Temperatures, 0.2 GHz to

28 GHz, VDD = 5 V, VBIAS = 5 V IDQ = 80 mA, RBIAS = 300 Ω

Figure 29. Noise Figure vs. Frequency for Various VDD, IDQ = 80 mA, 0.2 GHz Figure 30. Noise Figure vs. Frequency for Various Bias Resistor Values and

Figure 31. OP1dB vs. Frequency for Various Temperatures, 0.01 GHz to 1 Figure 32. OP1dB vs. Frequency for Various Supply Voltages, IDQ = 80 mA,

0.01 GHz to 1 GHz

Figure 33. OP1dB vs. Frequency for Various Bias Resistor Values and IDQ,

0.01 GHz to 1 GHz, VDD = 5 V, VBIAS = 5 V

Figure 34. OP1dB vs. Frequency for Various Temperatures, 1 GHz to 28 GHz, Figure 35. OP1dB vs. Frequency for Various Supply Voltages, IDQ = 80 mA, 1 Figure 36. OP1dB vs. Frequency for Various Bias Resistor Values and IDQ, 1

Figure 43. Power Added Efficiency (PAE) vs. Frequency for Various Figure 44. POUT, PAE, Gain, and Drain Current (IDD) vs. Input Power, Power Figure 45. POUT, PAE, Gain, and IDD vs. Input Power, Power Compression at 8 Figure 46. PAE vs. Frequency for Various Temperatures, 1 GHz to 28 GHz, Figure 47. POUT, PAE, Gain, and IDD vs. Input Power, Power Compression at

10 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω

Figure 48. POUT, PAE, Gain, and IDD vs. Input Power, Power Compression at

14 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω

Figure 49. POUT, PAE, Gain, and IDD vs. Input Power, Power Compression at

20 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω

Figure 50. OIP3 vs. Frequency for Various Temperatures, 0.01 GHz to 1 GHz, Figure 51. OIP3 vs. Frequency for Various VDD, IDQ = 80 mA, 0.01 GHz to 1 Figure 52. POUT, PAE, Gain, and IDD vs. Input Power, Power Compression at

26 GHz, VDD = 5 V, VBIAS = 5 V, RBIAS = 300 Ω

Figure 53. OIP3 vs. Frequency for Various Temperatures, 1 GHz to 28 GHz, Figure 54. OIP3 vs. Frequency for Various VDD, IDQ = 80 mA, 1 GHz to 28 GHz

are dc-coupled and matched to 50 Ω. biased by connecting the ACG4/VDD2 pin to an external supply. Figure 73. Simplified Block Diagram

36 V while maintaining high efficiency and output noise below the

Figure 75. Application Circuit for the ADL9005 Using the LTM8020 Regulator

this case, to set IDQ to 80 mA, use an R1 value of 850 Ω on RBIAS. Figure 78. Providing Resistive Drain Bias Through the ACG4/VDD2 Pin simultaneously with VDD or after VDD is applied.

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP]