ADL8124 AD | Alldatasheet

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Technical content

1GHz to 20GHz, Low Noise Amplifier with Integrated Temperature Sensor and Enable Function Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. All Analog Devices products contained herein are subject to release and availability.

FEATURES

►Single positive supply: 3.3V and IDQ of 55mA ►RBIAS drain current adjustment pin ►Integrated temperature sensor ►Integrated enable and disable function ►Gain: 15dB typical from 10GHz to 17GHz ►OIP3: 29dBm typical from 10GHz to 17 GHz ►Noise figure: 2.1dB typical from 10GHz to 17GHz ►Extended operating temperature range: −55°C to +125°C ►RoHS-compliant, 2mm × 2mm, 8-lead LFCSP

APPLICATIONS

►Telecommunications ►Test instrumentation ►Military GENERAL DESCRIPTION The ADL8124 is a highly integrated, 1GHz to 20GHz, low noise am- plifier (LNA). On-chip features include input and output AC coupling capacitors, an integrated bias inductor, an integrated temperature sensor, and an enable or disable pin (VENBL). The typical gain and noise figure are 15dB and 2.1dB, respectively, from 10GHz to 17GHz. The output power for 1dB compression (OP1dB), output third-order intercept (OIP3), and output second-or- der intercept (OIP2) are 15dBm, 29dBm, and 43dBm, respectively, from 10GHz to 17GHz. The quiescent drain current (IDQ), which can be adjusted, is 55mA operating from a 3.3V supply voltage (VDD). Operation at 5V is also supported. The ADL8124 is fabricated on a gallium arsenide (GaAs), pseudo- morphic high electron mobility transistor (pHEMT) process. This device is housed in an RoHS-compliant, 2mm × 2mm, 8-lead LFCSP package and is specified for operation over an extended temperature range of −55°C to +125°C. FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram

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REVISION HISTORY

9/2025—Revision 0: Initial Version

VDD = 3.3V, IDQ = 55mA, bias resistance (RBIAS) = 1540Ω, VENBL voltage (VENBL) = 3.3V, and TCASE = 25°C, unless otherwise noted. Table 1. 1GHz to 2GHz Frequency Range VDD = 3.3V, IDQ = 55mA, RBIAS = 1540Ω, VENBL = 3.3V, and TCASE = 25°C, unless otherwise noted. Table 2. 2GHz to 10GHz Frequency Range

VDD = 3.3V, IDQ = 55mA, RBIAS = 1540Ω, VENBL = 3.3V, and TCASE = 25°C, unless otherwise noted. Table 3. 10GHz to 17GHz Frequency Range VDD = 3.3V, IDQ = 55mA, RBIAS = 1540Ω, VENBL = 3.3V, and TCASE = 25°C, unless otherwise noted. Table 4. 17GHz to 20GHz Frequency Range

Table 5. DC Specifications Table 6. Logic Control (VENBL) Table 7. Temperature Sensor

Table 8. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. θJC is the channel-to-case thermal resistance. Table 9. Thermal Resistance1 1 Thermal resistance varies with operating conditions. sitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Table 10. ADL8124, 8-Lead LFCSP devices and circuit boards can discharge without detection. taken to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 11. Pin Function Descriptions Table 12 to Table 15 for more details. See Figure 7 for the interface schematic. 2 VTEMP Temperature Sensor Output Voltage. See Figure 5 for the interface schematic. 3, 6 GND Ground. Connect the GND pins to a ground plane that has low electrical and thermal impedance. See Figure 3 for the interface schematic. 4 RFIN RF Input. RFIN is AC-coupled and matched to 50Ω. See Figure 4 for the interface schematic. 5 RFOUT RF Output. The RFOUT pin is AC-coupled and matched to 50Ω. See Figure 6 for the interface schematic. 8 VDD Drain Bias. Connect the VDD pin to the supply voltage. See Figure 6 for the interface schematic. GROUND PADDLEGround Paddle. Connect the ground paddle to a ground plane which has a low electrical and thermal impedance.

Figure 99. Simplified Architecture

to the VDD pin. Alternatively, 5V supply operation is also supported. RBIAS value (see Table 12). Do not leave the RBIAS pin open. internally supplied through the VDD pin. Figure 100. Typical Application Circuit

  1. Apply the RF input signal.

alternate bias resistor options for different VDD and IDQ choices. Table 12. Recommended Bias Resistor Values for VDD = 3.3V Table 13. Recommended Bias Resistor Values for VDD = 5V Table 14. Recommended Bias Resistor Values for Various Supply Voltages, Table 15. Recommended Bias Resistor Values for Various Supply Voltages,

©2025 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. 0 | 29 of 29 Package Drawing Option Package Type Package Description CP-8-30 LFCSP 8-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. ORDERING GUIDE Model1, 2 Temperature Range Package Description Packing Quantity Package Option ADL8124ACPZN −55°C to +125°C 8-Lead LFCSP, 2mm × 2mm × 0.85mm Tape, 1 CP-8-30 ADL8124ACPZN-R7 −55°C to +125°C 8-Lead LFCSP, 2mm × 2mm × 0.85mm Reel, 3000 CP-8-30 1 Z = RoHS Compliant Part. 2 The lead finish of the ADL8124ACPZN and ADL8124ACPZN-R7 is nickel palladium gold.