ADL7003

ADL7003 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 18

Technical content

50 GHz to 95 GHz, GaAs, pHEMT, MMIC,

Wideband Low Noise Amplifier Data Sheet ADL7003 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781 .32 9. 47 00 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Gain: 14 dB typical Noise figure: 5 dB typical Input return loss (S11): 15 dB typical Output return loss (S22): 20 dB typical Output power for 1 dB compression (P1dB): 14 dBm typical Saturated output power (PS AT): 18 dBm typical Output third-order intercept (IP3): 21 dBm typical Supply voltage: 3 V at 120 mA 50 Ω matched input/output Die size: 1.9 mm × 1.9 mm × 0.05 mm

APPLICATIONS

Telecommunications infrastructure FUNCTIONAL BLOCK DIAGRAM 91011121314 765432 VDD2B VDD3B VDD4B VDD1B VGG34B VGG12B RFIN RFOUT ADL7003 VDD4A VDD3A VGG34A VDD2A VDD1A VGG12A 15691-001 Fi gure 1. GENERAL DESCRIPTION The ADL7003 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), balanced low noise amplifier that operates from 50 GHz to 95 GHz. In the lower band of 50 GHz to 70 GHz, the ADL7003 provides 14 dB (typical) of gain, 21 dBm output IP3, and 12 dBm of output power for 1 dB gain compression. In the upper band of 70 GHz to 90 GHz, the ADL7003 provides 15 dB (typical) of gain, 21 dBm output IP3, and 14 dBm of output power for1 dB gain compression. The ADL7003 requires 120 mA from a 3 V supply . The ADL7003 amplifier inputs/outputs are internally matched to 50 Ω, facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via one 0.076 mm (3 mil) ribbon b ond of 0.076 mm (3 mil) minimal length.

Rev. 0 | Page 2 of 18 TABLE OF CONTENTS Mounting and Bonding Techniques for Millimeterwave GaAs

REVISION HISTORY

4/2017 —Revision 0: Initial V ersion

Rev. 0 | Page 3 of 18 SPECIFICATIONS

50 GHz TO 70 GHz FREQUENCY RANGE

TDIE BOTTOM = 25°C; VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3 V; IDQ = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 120 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from −1.5 V to 0 V to achieve the desired IDQ. Typical VGG = −0.5 V for IDQ = 120 mA. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 50 70 GHz GAIN 14 dB Gain Variation over Temperature 0.02 dB/°C NOISE FIGURE 5 dB RETURN LOSS Input S11 15 dB Output S22 20 dB OUTPUT Output Power for 1 dB Compression P1dB 12 dBm Saturated Output Power PS AT 16 dBm Output Third-Order Intercept OIP3 21 dBm Output power (POUT)/tone = 0 dBm with 1 MHz tone spacing INPUT Input Third-Order Intercept IIP3 7 dBm POUT/tone = 0 dBm with 1 MHz tone spacing SUPPLY Current IDQ 120 180 mA Adjust VGG to achieve IDQ = 120 mA typical Voltage VDD 2 3 4 V

70 GHz TO 90 GHz FREQUENCY RANGE

TDIE BOTTOM = 25°C; VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3 V; IDQ = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 120 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from −1.5 V to 0 V to achieve the desired IDQ. Typical VGG = −0.5 V for IDQ = 120 mA. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 70 90 GHz GAIN 13 15 dB Gain Variation over Temperature 0.02 dB/°C NOISE FIGURE 5.5 6.5 dB RETURN LOSS Input S11 15 dB Output S22 15 dB OUTPUT Output Power for 1 dB Compression P1dB 14 dBm Saturated Output Power PS AT 18 dBm Output Third-Order Intercept OIP3 21 dBm POUT/tone = 0 dBm with 1 MHz tone spacing INPUT Input Third -Order Intercept IIP3 6 dBm POUT/tone = 0 dBm with 1 MHz tone spacing SUPPLY Current IDQ 120 180 mA Adjust VGG to achieve IDQ = 120 mA typical Voltage VDD 2 3 4 V

Rev. 0 | Page 4 of 18

90 GHz TO 95 GHz FREQUENCY RANGE

TDIE BOTTOM = 25°C; VDD = VDD1A = VDD2A = VDD3A = VDD4A = 3 V; IDQ = IDQ1A + IDQ2A + IDQ3A + IDQ4A = 120 mA, unless otherwise noted. Adjust VGG = VGG12A = VGG34A from −1.5 V to 0 V to achieve the desired IDQ. Typical VGG = −0.5 V for IDQ = 120 mA. Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments FREQUENCY RANGE 90 95 GHz GAIN 11 dB Gain Variation over Temperature 0.02 dB/°C RETURN LOSS Input S11 15 dB Output S22 15 dB SUPPLY Current IDQ 120 180 mA Adjust VGG to achieve IDQ = 120 mA typical Voltage VDD 2 3 4 V

1 Million Hour MTTF

soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance

Table 6. Pad Function Descriptions 1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2 VGG 12A Gate Control Pad for the First and Second Stage Amplifiers. See Figure 4 for the interface schematic. and 4.7 µF are required. Connect these pads to a 3 V supply. See Figure 5 for the interface schematic. 5 VGG34A Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. and 4.7 µF are required. Connect these pads to a 3 V supply. See Figure 5 for the interface schematic. 8 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic. capacitors of 120 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic. required. See Figure 8 for the interface schematic. capacitors of 120 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic. required. See Figure 8 for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF/dc ground. See Figure 6 for the interface schematic.

Rev. 0 | Page 7 of 18 INTERFACE SCHEMATIC RFIN 15691-003 Fi gure 3. RFIN Interface Schematic VGG12A, VGG34A 15691-004 Fi gure 4. VGG12A, VGG34A Interface Schematic VDD1A TO VDD4A 15691-005 Fi gure 5. VDD 1A to VDD 4A Interface Schematic GND 15691-006 Fi gure 6. GND Interface Schematic VDD1B TO VDD4B 15691-007 Fi gure 7. VDD 1B to VDD 4B Interface Schematic VGG12B, VGG34B 15691-008 Fi gure 8. VGG12B, VGG34B Interface Schematic RFOUT 15691-009 Fi gure 9. RFOUT Interface Schematic

Rev. 0 | Page 8 of 18 TYPICAL PERFORMANCE CHARACTERISTICS –30 40 100 RESPONSE (dB) FREQUENCY (GHz) –25 –20 –15 –10 45 50 55 60 65 70 75 80 85 90 95 S11 S21 S22 15691-010 Fi gure 10. Broadband Gain and Return Loss vs. Frequency 50 95 GAIN (dB) FREQUENCY (GHz) +85°C +25°C –55°C 55 60 65 70 75 80 85 90 15691-013 Fi gure 11. Gain vs. Frequency for Vari ous Temperatures GAIN (dB) 50 95 FREQUENCY (GHz) 55 60 65 70 75 80 85 90 100mA 120mA 140mA 160mA 180mA 15691-020 Fi gure 12. Gain vs. Frequency for Vari ous IDQ Values GAIN (dB) 50 9590 FREQUENCY (GHz) 55 60 65 70 75 80 85 2.0V 2.7V 3.0V 3.3V 4.0V 15691-027 Fi gure 13. Gain vs. Frequency for Vari ous VDD Values –26 50 95 INPUT RETURN LOSS (dB) FREQUENCY (GHz) –24 –22 –20 –18 –16 –14 –12 –10 55 60 65 70 75 80 85 90 +85°C +25°C –55°C 15691-011 Fi gure 14. Input Return Loss vs. Frequency at Various Temperatures –26 INPUT RETURN LOSS (dB) –24 –22 –20 –18 –16 –14 –12 –10 50 95 FREQUENCY (GHz) 55 60 65 70 75 80 85 90 100mA 120mA 140mA 160mA 180mA 15691-018 Fi gure 15. Input Return Loss vs. Frequency for Various IDQ Values

Figure 21. Noi se Fi gure vs. Frequency for Vari ous IDQ Values

Rev. 0 | Page 10 of 18 50 90 FREQUENCY (GHz) NOISE FIGURE (dB) 55 60 65 70 75 80 852.0V 2.7V 3.0V 3.3V 4.0V 15691-029 Fi gure 22. Noi se Fi gure vs. Frequency for Vari ous VDD Values 50 90 OUTPUT P1dB (dB) FREQUENCY (GHz) 55 60 65 70 75 80 85+85°C +25°C –55°C 15691-015 Fi gure 23. Output P1dB vs. Frequency at Various Temperatures P1dB (dBm) 100mA 120mA 140mA 160mA 180mA 50 90 FREQUENCY (GHz) 55 60 65 70 75 80 85 15691-025 Fi gure 24. P1dB vs. Frequency for Vari ous IDQ Values 50 90 FREQUENCY (GHz) P1dB (dBm) 55 60 65 70 75 80 85 2.0V 2.7V 3.0V 3.3V 4.0V 15691-032 Fi gure 25. P1dB vs. Frequency for Vari ous VDD Values PSAT (dBm) +85°C +25°C –55°C 50 90 FREQUENCY (GHz) 55 60 65 70 75 80 85 15691-016 Fi gure 26. PSAT vs. Frequency at Various Temperatures 50 95 PSAT (dBm) FREQUENCY (GHz) 100mA 120mA 140mA 160mA 180mA 55 60 65 70 75 80 85 90 15691-023 Fi gure 27. PSAT vs. Frequency at Various IDQ Values

Figure 33. OIP3 vs. Frequency for Vari ous IDQ Values

Rev. 0 | Page 12 of 18 OUTPUT IP3 (dBm) 50 90 FREQUENCY (GHz) 55 60 65 70 75 80 85 2.0V 2.7V 3.0V 3.3V 4.0V 15691-034 Fi gure 34. OIP3 vs. Frequency for Vari ous VDD Values 0.30 0.25 0.20 0.15 0.10 0.05 –0.10 –0.05 –15 15 GATE SUPPLY CURRENT (mA) RF INPUT POWER (dBm) –12 –9 –6 –3 0 3 6 129 70GHz 75GHz 80GHz 85GHz 15691-035 Fi gure 35. Gate Supply Current (IDD ) vs. RF Input Power 300 100 120 140 160 180 200 220 240 260 280 DRAIN SUPPLY CURRENT (mA) –15 15 RF INPUT POWER (dBm) –12 –9 –6 –3 0 3 6 9 12 70GHz 75GHz 80GHz 85GHz 15691-036 Fi gure 36. Drai n Supply Current (IDD ) vs. RF Input Power 450 400 350 300 250 200 150 100 DRAIN SUPPLY CURRENT (mA) GATE SUPPLY VOLTAGE (V) 2.0V 2.7V 3.0V 3.3V 4.0V 15691-050 Fi gure 37. Drai n Supply Current (IDQ) vs. Gate Supply Voltage (V GG)

Rev. 0 | Page 13 of 18 THEORY OF OPERATION The architecture of the ADL7003 low noise amplifier is shown in Figure 38. The ADL7003 uses two cascaded four-stage amplifiers operating in quadrature between two 90° hybrids. This balanced amplifier approach forms an amplifier with a combined gain of 14 dB and a saturated output power (PSAT) of 18 dBm. The 90° hybrids ensure that the input and output return losses are greater than or equal to 15 dB. See the application circuit shown in Figure 41 for further details on biasing the various blocks. RFIN RFOUT 15691-037 Fi gure 38. ADL7003 Architecture

The ADL7003 is a GaAs, pHEMT, MMIC power amplifier. and VGG34A, and use capacitive bypassin g as shown in Figure 41. the assembly diagram (Figure 42).

1. Set the gate bias voltage to −1.5 V.
2. Set all the drain bias voltages, VDD = 3 V.
3. Increase the gate bias voltag e to achieve a quiescent
4. Decrease the gate bias voltage to −1.5 V to achieve
5. Decrease all of the drain bias voltages to 0 V .
6. Increase the gate bias voltag e to 0 V .

Table 7. Power Selection Table1 1 Data taken at nominal bias conditions; V DD = 3 V, TA = 25°C. Figure 41. Biasing the ADL7003 for higher drain current typically of increased power consumption (see Tab le 7). section, and the Wire Bonding section). board before the ribbon bond.

Rev. 0 | Page 15 of 18 Handling Precautions To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions:

• Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. After the sealed ESD protective bag is opened, store all die in a dry nitrogen environment.
• Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems.
• Follow ESD precautions to protect against ESD strikes.
• While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pickup.
• Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. Mounting Before epoxy die is attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after it is placed into position. Cure the epoxy per the schedule of the manufacturer. Wire Bonding RF bonds made with 0.003 in. × 0.0005 in. gold ribbon are recommended for the RF ports. These bonds must be thermo- sonically bonded with a force of 40 g to 60 g. DC bonds of 0.001 in. (0.025 mm) diameter, thermosonically bonded, are recommended. Create ball bonds with a force of 40 g to 50 g and wedge bonds with a force of 18 g to 22 g. Create all bonds with a nominal stage temperature of 150°C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than 12 mil (0.31 mm). Alternatively, short (≤3 mil) RF bonds made with two 1-mil wires can be used.

The drain and gate voltages can be applied to either the north or the south side of the circuit. Figure 41. Typical Application Circuit

Rev. 0 | Page 17 of 18 ASSEMBLY DIAGRAM 15691-055 Fi gure 42. Assembly Diagram

Rev. 0 | Page 18 of 18 OUTLINE DIMENSIONS 04-26-2017-A 1.90 SQ 0.05 SIDE VIEW 0.207 0.208 0.117 2 3 4 5 6 7 91011121314 0.088 0.088 0.637 0.125 0.125 1.016 0.125 0.125 *AIRBRIDGE AREA *This die utilizes fragile air bridges. Any pickup tools used must not contact this area. 0.076 × 0.076 (Pads 2-7, 9-14) 0.086 × 0.051 (Pads 1 & 8) 0.081 × 0.097 Fi gure 43. 14-Pad Bare Die [CHIP] (C-14-5) Dimensions shown in millimeter ORDERING GUIDE Model Temperature Range Package Description Package Option ADL7003CHIPS −55°C to +85°C 14-Pad Bare Die [CHIP] C-14-5 ADL7003CHIPS-SX −55°C to +85°C 14-Pad Bare Die [CHIP] C-14-5 ©2017 Analog Devices, I nc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D15691-0-4/17(0)