ADL6337_V01 AD | Alldatasheet
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Technical content
35 dB Gain, 500 MHz to 5200 MHz Transmit VGA Rev. E DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Single-channel, high-linearity transmit VGA for RF DACs, trans- ceivers, and SoCs to power amplifier interface ►Single 5 V supply ►Multiple versions covering frequencies of 500 MHz to 5200 MHz ►Power gain: 37.4 dB (ADL6337-A), 35.5 dB (ADL6337-B), 34 dB (ADL6337-C), 35.5 dB (ADL6337-D) ►OIP3: 42.0 dBm (ADL6337-A), 42.5 dBm (ADL6337-B), 38 dBm (ADL6337-C), 40 dBm (ADL6337-D) ►OIP2: 50 dBm (ADL6337-A), 55 dBm (ADL6337-B), 68 dBm (ADL6337-C), 74 dBm (ADL6337-D) ►Noise figure: 3.7 dB (ADL6337-A), 4.5 dB (ADL6337-B), 5.2 dB (ADL6337-C), 4.5 dB (ADL6337-D) ►OP1dB: 26.1 dBm (ADL6337-A), 26.0 dBm (ADL6337-B), 25.5 dBm (ADL6337-C), 23.5 dBm (ADL6337-D) ►RF DSA attenuation range: 31.5 dB with 0.5 dB resolution ►50 Ω/100 Ω differential inputs and 50 Ω single-ended output ►Fully programmable via a 3-/4-wire SPI ►32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
►2G/3G/4G/long-term evolution (LTE) in FDD/TDD broadband ►Communication systems GENERAL DESCRIPTION The ADL6337 belongs to a family of transmit variable gain ampli- fiers (VGAs). It provides an interface from RF digital-to-analog converters (DACs), transceivers, and systems on a chip (SoC) to power amplifiers. It also includes an integrated RF balun and can be configured as a differential input, single-ended output to allow high-performance RF capability in the 500 MHz to 5200 MHz frequency range. To optimize performance vs. power level, the ADL6337 includes high linearity amplifiers and a glitch free digital step attenuator (DSA). All of the ADL6337 components are programmable via a 3- or 4-wire serial port interface (SPI). The ADL6337 is manufactured on an advanced silicon germani- um (SiGe), bipolar complementary metal-oxide semiconductor (BiC- MOS) process. Table 1. ADL6337 Frequency Ranges Figure 1. Functional Block Diagram
analog.com Rev. E | 2 of 53 Linearity and Performance Optimization Configuring Multiple Chips to Share the SPI
REVISION HISTORY
10/2024—Rev. D to Rev. E 11/2023—Rev. C to Rev. D 10/2023—Rev. B to Rev. C
analog.com Rev. E | 3 of 53
dBm per tone for two tones), DSA attenuation = 0 dB, source resistance (RS) = load resistance (RL) = 50 Ω, unless otherwise noted. Table 2. Electrical Characteristics
Table 2. Electrical Characteristics (Continued) Table 3. SPI AC Timing
Table 4. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. must be used in compliance with JESD51-12. Table 5. Thermal Resistance damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 6. Pin Configuration Table 6. Pin Function Descriptions 1 TXENP Input Amplifier Enable. 4 RFIN_P Input Positive RF Input. 5 RFIN_N Input Negative RF Input. 9 ATTSEL1 Input Fast Attenuation Selection. 10 ATTSEL2 Input Fast Attenuation Selection. 11 V50AMP1 Input Amplifier 1 Analog Power Supply (5.0 V). 14 V50AMP2 Input Amplifier 2 Analog Power Supply (5.0 V). 21 RFOUT Output Single-Ended RF Output. floating when 3-wire SPI mode is used. 25 CS Input Serial Port Latch Enable Input. 26 SDIO Input/Output Serial Port Bidirectional Data Input/Output. 27 SCLK Input Serial Port Clock Input. about the connections in a multiple chip operation. Ground these pins if unused. about the connections in a multiple chip operation. Ground these pins if unused. about the connections in a multiple chip operation. Ground these pins if unused.
Figure 11. Gain Settling Time at DSA1 = 0.00 dB (Minimum), DSA2 from 0.00
Figure 99. OP1dB vs. Frequency at Various DSA Values Figure 100. OIP3 vs. Frequency for Various Supplies Figure 101. OIP3 vs. Frequency for Various Temperatures Figure 102. OIP3 vs. Frequency at Various DSA Values Figure 103. OIP3 vs. Output Power Per Tone for Various Temperatures at
4400 MHz and 5000 MHz
Figure 104. OIP2 vs. Frequency for Various Supplies
Figure 105. OIP2 vs. Frequency for Various Temperatures Figure 106. OIP2 vs. Frequency at Various DSA Values Figure 107. OIP2 vs. Output Power per Tone for Various Temperatures at Figure 108. Noise Figure vs. Frequency for Various Supplies Figure 109. Noise Figure vs. Frequency at Various DSA Values Figure 110. Noise Figure vs. Frequency for Various Temperatures
analog.com Rev. E | 31 of 53 A typical RF transmitter transmits RF power at a fixed output level. System gain varies over time, temperature, and process. Therefore, a gain adjustable block is needed to calibrate and compensate this variation. A VGA provides this programmable gain function. The ADL6337 is a highly integrated RF VGA solution for transmit paths. It provides a single-chip solution that contains a balun for differential to single-ended signal conversion, digital attenuation, and gain stages while offering high dynamic range multicarrier transmitter designs. The ADL6337 is a highly integrated 2-stage VGA used to interface an RF DAC to the power amplifier in the transmitter. It offers multiple gain control options with a 31.5 dB attenuation range in 0.5 dB steps integrating a RF Digital Step Attenuator (DSA1), a high linearity amplifier, followed by a second RF Digital Step Attenuator (DSA2), and a second high linearity amplifier. Putting together the ADL6337 building blocks, the signal path through the device starts with converting the differential inputs to single ended by the integrated balun at the output. The integrated building blocks of the ADL6337 are programmable via the SPI. RF INPUT AND OUTPUT The input impedance is 50 Ω differential and the output impedance is 50 Ω single-ended to allow the device to be driven by the DAC . 100 Ω differential inputs can be also achieved with external match- ing networks. See the Input and Output Port Matching section.
subdivided into the major functional blocks, as shown in Table 7. Table 7. Memory Map Functional Groups reduced. Also, use this mode to adjust DSA level in Register 0x103. Its default attenuation level is the maximum (31.5 dB). and 0x116 registers are used for operation. also called Attenuation State 0, 1, 2, and 3 (see Table 10). chronous external control with the ATTSEL1 and ATTSEL2 Pins. 0x102 for Attenuation State 0 to set the DSA attenuation level. be held low during power-up. via the SPI or using the default values provided in Table 10. Table 8. TXENP Mode Selection 1 (High) Normal operation mode0x100 Enable AMP1, AMP2, LDO, etc. Enable bit to adjust DSA1 and DSA2 individually. 0x10A, 0x10B To adjust DSA1 and DSA2 levels individually at DSA_MAN_EN_0 0x100[7] = 1. ATTSEL2 (Pin 10) at DSA_MAN_EN_0 0x100[7] = 0 (default).
Table 8. TXENP Mode Selection (Continued) 0x110 IP3 Linearization Block Enable register. Use default to enable. IP3 linearization trimming values for AMP1 and AMP2 (for example, 0x010). Table 9. Register 0x100: Enable Register for Normal Operation 1: Register 0x10A, 0x10B are used to configure DSA1 and DSA2 individually. Table 10. Four Preconfiguration Settings for DSA
feature to change two types of bias current blocks: IREF and IP3. shows a summary of IREF register address and bit names. however, use the same optimized values for AMP1 and AMP2. and IP3 values to achieve the performance shown in Table 15. Table 11. IREF Register Summary Table 12. IP3 Enable/Disable Register Bits Table 13. 0x105 IP3 Register for AMP1 Table 14. 0x106 IP3 Register for AMP2 Table 15. Optimized IREF and IP3 Values
0x000 (broadcasting reset mode). Table 16. Software Reset Type
3.3 V output levels by setting the SPI_1P8_3P3_CTRL bit (Register
- Set TXENP (Pin 1) to low (GND). The power-down mode is
recommended to configure the ADL6337 via SPI.
- Send the data in Table 17 via SPI.
- Set TXENP (Pin 1) to high (5.0 V) to start the normal operation
Table 17. SPI Sample Script for ADL6337-B
Figure 121. Basic Connections Table 18. Basic Connections RF Input 4, 5 RFIN_P, RFIN_N RF inputs Differential RF input. RF Output 21 RFOUT RFOUT RF output, single-ended. Serial Port 25 CS Active-low chip select 1.8 V to 3.3 V tolerant logic levels. 27 SCLK SPI clock 1.8 V to 3.3 V tolerant logic levels. 24 SDO SPI data input 1.8 V to 3.3 V tolerant logic levels. 26 SDIO SPI data output 1.8 V to 3.3 V tolerant logic levels. no physical connection within the chip. They can be grounded or floated.
Table 19. Register Summary
Table 20. Bit Descriptions for ADI_SPI_CONFIG
7 SOFTRESET_ Soft Reset for the Broadcasting Mode 0x0 R/W
6 LSB_FIRST_ Least Significant Bit (LSB) First 0x0 R/W
5 ENDIAN_ Endian 0x0 R/W
4 SDOACTIVE_ SDO Active 0x0 R/W
3 SDOACTIVE SDO Active 0x0 R/W
1 LSB_FIRST LSB First 0x0 R/W
0 SOFTRESET Soft Reset for the Broadcasting Mode 0x0 R/W
Table 21. Bit Descriptions for REG_0X0001
0 PRIMARY_SUBORDINATE_TRANSFE
Table 22. Bit Descriptions for CHIPTYPE Table 23. Bit Descriptions for PRODUCT_ID_L
Table 24. Bit Descriptions for PRODUCT_ID_H Table 25. Bit Descriptions for SCRATCHPAD Table 26. Bit Descriptions for SPI_REV Table 27. Bit Descriptions for FEOL Table 28. Bit Descriptions for BEOL_SIF Table 29. Bit Descriptions for VARIANT Table 30. Bit Descriptions for SOFTRST_CHIP
0 SOFTRESET_CHIP SoftReset for a Single Chip 0x0 R/W
Table 31. Bit Descriptions for SIG_PATH0_0
7 DSA_MAN_EN_0 DSA Manual Mode Enable When TXENP = 1
0: Enable 4-Predefine mode via ATTSEL pins. 1: Registers 0x10A, 0x10B are used to configure DSA1 and DSA2 individually.
6 AMP2_IP3_OFF_0_0 Turn Off AMP2 IP3 Currents ATTSEL00 When TXENP = 1
Table 31. Bit Descriptions for SIG_PATH0_0 (Continued)
5 AMP1_IP3_OFF_0_0 Turn Off AMP1 IP3 Currents ATTSEL00 When TXENP = 1
2 EN_IBIASGEN_0 Enable Bias Generator When TXENP = 1
1 AMP2_EN_0 Enable Amp 2 When TXENP = 1
0 AMP1_EN_0 Enable Amp 1 When TXENP = 1
Table 32. Bit Descriptions for SIG_PATH2_0
Table 32. Bit Descriptions for SIG_PATH2_0 (Continued) Table 33. Bit Descriptions for SIG_PATH3_0
Table 33. Bit Descriptions for SIG_PATH3_0 (Continued)
Table 34. Bit Descriptions for SIG_PATH4_0 Table 35. Bit Descriptions for SIG_PATH5_0 Table 36. Bit Descriptions for SIG_PATH6_0 Table 37. Bit Descriptions for SIG_PATHA_0
Table 37. Bit Descriptions for SIG_PATHA_0 (Continued) Table 38. Bit Descriptions for SIG_PATHB_0
Table 39. Bit Descriptions for AMPS_IP3_ATTSEL
6 AMP2_IP3_OFF_3 Turn Off AMP2 IP3 Currents ATTSEL11 0x0 R/W
5 AMP2_IP3_OFF_2 Turn Off AMP2 IP3 Currents ATTSEL10 0x0 R/W
4 AMP2_IP3_OFF_1 Turn Off AMP2 IP3 Currents ATTSEL01 0x0 R/W
3 RESERVED Reserved 0x0 R
2 AMP1_IP3_OFF_3 Turn Off AMP1 IP3 Currents ATTSEL11 0x0 R/W
1 AMP1_IP3_OFF_2 Turn Off AMP1 IP3 Currents ATTSEL10 0x0 R/W
0 AMP1_IP3_OFF_1 Turn Off AMP1 IP3 Currents ATTSEL01 0x0 R/W
Table 40. Bit Descriptions for TRM_AMPS_IREF_1 Table 41. Bit Descriptions for TRM_AMPS_IREF_2 Table 42. Bit Descriptions for TRM_AMPS_IREF_3 Table 43. Bit Descriptions for DSA_ATTSEL_1
Table 43. Bit Descriptions for DSA_ATTSEL_1 (Continued)
Table 44. Bit Descriptions for DSA_ATTSEL_2
Table 44. Bit Descriptions for DSA_ATTSEL_2 (Continued) Table 45. Bit Descriptions for DSA_ATTSEL_3
Table 45. Bit Descriptions for DSA_ATTSEL_3 (Continued) Table 46. Bit Descriptions for DIG_CTRL
0 SPI_1P8_3P3_CTRL SPI Supply Control 0x0 R/W
©2023-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. E | 53 of 53 Package Drawing (Option) Package Type Package Description CR-32-2 LFCSP_RT 32-Lead Lead Frame Chip Scale Package, Routable For the latest package outline information and land patterns (footprints), go to Package Index. Updated: November 27, 2023 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option ADL6337ACRZA -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Tray, 490 CR-32-2 ADL6337ACRZA-R7 -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Reel, 1500 CR-32-2 ADL6337ACRZB -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Tray, 490 CR-32-2 ADL6337ACRZB-R7 -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Reel, 1500 CR-32-2 ADL6337ACRZC -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Tray, 490 CR-32-2 ADL6337ACRZC-R7 -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Reel, 1500 CR-32-2 ADL6337ACRZD -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Tray, 490 CR-32-2 ADL6337ACRZD-R7 -40°C to +105°C 32-Lead LFCSP-RT (5 mm × 5 mm × 0.58 mm)Reel, 1500 CR-32-2 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Package Description ADL6337-EVALZA Evaluation Board for Variant A: 500 MHz to 1000 MHz Operation ADL6337-EVALZB Evaluation Board for Variant B: 1350 MHz to 2800 MHz Operation ADL6337-EVALZC Evaluation Board for Variant C: 3100 MHz to 4400 MHz Operation ADL6337-EVALZD Evaluation Board for Variant D: 4400 MHz to 5200 MHz Operation EVAL-SDP-CS1Z SDP-S Controller Board 1 Z = RoHS Compliant Part.