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500 MHz to 1000 MHz Transmit VGA
for Use with RF DACs and Transceivers Data Sheet ADL6316 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Transmit VGA for RF DAC, transceiver, and SoC to power amplifier interface RF output frequency range: 500 MHz to 1000 MHz Internal balun with bias tee to supply RF DAC outputs Integrated VVA attenuation range with on-chip DAC: 20.5 dB 2-stage high linearity amplifiers RF DSA attenuation range: 14 dB with 0.45 dB step resolution 50 Ω differential inputs and 50 Ω single-ended output Fully programmable via a 4-wire SPI Single 5 V supply 38-terminal, 10.5 mm × 5.5 mm LGA
APPLICATIONS
2G/3G/4G/long-term evolution (LT E) in FDD/TDD broadband communication systems GENERAL DESCRIPTION The ADL6316 is a transmit variable gain amplifier (VGA) that provides an interface from radio frequency digital-to-analog converters (RF DACs), transceivers, and systems on a chip (SoC) to power amplifiers. Integrated balun and hybrid couplers allow high performance RF capability in the frequency range of 500 MHz to 1000 MHz. To optimize performance vs. power level, the ADL6316 includes a voltage variable attenuator ( V VA ), high linearity amplifiers, and a digital step attenuator (DSA). All of the devices integrated into the ADL6316 are programmable via a 4-wire serial port interface (SPI). The ADL6316 is manufactured on an advanced silicon germanium (SiGe), bipolar complementary metal-oxide semiconductor (BiCMOS) process. Table 1. Related Devices in Transmit VGA Family
Rev. 0 | Page 2 of 37 TABLE OF CONTENTS Adjacent and Alternate Channel Power Ratios on LTE
REVISION HISTORY
10/2019—Revision 0: Initial Version
Rev. 0 | Page 3 of 37 SPECIFICATIONS V50AMP1 = V50AMP2 = 5 V, TA = 25°C, input power (PIN) = −25 dBm (−25 dBm per tone for two tones), V VA attenuation = 0 dB, DSA attenuation = 0 dB, source resistance (RS) = load resistance (RL) = 50 Ω, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Units FREQUENCY RANGE 500 1000 MHz
620 MHz
Power Gain 29.70 dB Output 1 dB Compression Point (OP1dB) 24.80 dBm Output Second-Order Intercept (OIP2) 46.25 dBm Output Third-Order Intercept (OIP3) 43.40 dBm Second Harmonic (HD2) 51.00 dBc Third Harmonic (HD3) 85.50 dBc Noise Figure (NF) 7.50 dB
869 MHz
Power Gain 31.10 dB OP1dB 25.05 dBm OIP2 48.70 dBm OIP3 41.80 dBm HD2 53.00 dBc HD3 86.00 dBc NF 5.85 dB
960 MHz
Power Gain 30.70 dB OP1dB 24.70 dBm OIP2 48.75 dBm OIP3 41.10 dBm HD2 52.00 dBc HD3 74.5 dBc NF 5.95 dB RF INPUT/OUTPUT CHARACTERISTICS Input Impedance Differential 50 Ω Return Loss Inband, 869 MHz −17.5 dB Output Impedance Single-ended 50 Ω Return Loss Inband, 869 MHz −25.0 dB Gain Flatness Deviation from best linear fit at 620 MHz,
869 MHz, and 960 MHz
Over ±50 MHz bandwidth ±0.1 dB VOLTAGE VARIABLE ATTENUATOR Via 12-bit integrated DAC or external analog voltage on VVA_ANALOG pin Range 20.5 dB Gain Settling Time Minimum attenuation to maximum attenuation by VVA DAC 386.8 ns Maximum attenuation to minimum attenuation by VVA DAC 1.681 µs
Figure 2. Serial Port Interface Register Timing, MSB First
PCB thermal design is required. the case temperature is measured at the bottom of the package. should be used in compliance with JESD51-12. Table 5. Thermal Resistance1, 2
1 For θJC BOTTOM, the case bottom is controlled at 105°C and the case top is
2 Using enhanced heat removal (for example, PCB, heat sink, and airflow)
techniques to improve thermal resistance values.
- NIC = NOT INTERNALLY CONNECTED. THIS PIN HAS NO PHYSICAL
- EXPOSED PAD 1. EPAD1 IS INTERNALLY CONNECTED TO EPAD2.
ELECTRICAL AND THERMAL PURPOSES.
- EXPOSED PAD 2. EPAD2 IS INTERNALLY CONNECTED TO EPAD1.
ELECTRICAL AND THERMAL PURPOSES. Figure 5. Pin Configuration Table 6. Pin Function Descriptions 13 V50AMP1 Amplifier 1 Analog Power Supply (5.0 V). 17 V50AMP2 Amplifier 2 Analog Power Supply (5.0 V). 30 VVA_ANALOG Analog Voltage Control for VVA. 33 SDO Serial Port Data Output. 34 SCLK Serial Port Clock Input. 35 SDI Serial Port Data Input. 36 CS Serial Port Latch Enable Input. 37 TXEN Amplifier Enable, DSA Attenuation, and Trim Value Selection. be connected to ground for electrical and thermal purposes. be connected to ground for electrical and thermal purposes.
0 dB, RS = RL = 50 Ω, unless otherwise noted. Figure 6. Gain vs. Frequency; 0.45 dB DSA Steps Figure 7. Gain vs. Frequency; 100 VVA_ATTEN[11:0] Steps Figure 8. Gain vs. Frequency for Various Supplies Figure 9. Gain vs. Frequency for Various Temperatures Figure 10. Attenuation vs. DSA_ATTEN_x[4:0] at 620 MHz, 869 MHz, and
960 MHz; VVA Attenuation = 0 dB
Figure 11. Attenuation and VVA Voltage vs. VVA_ATTEN[11:0] at 620 MHz,
869 MHz, and 960 MHz; DSA Attenuation = 0 dB
Figure 12. OP1dB vs. Frequency for Various Supplies Figure 13. OP1dB vs. Frequency for Various Temperatures Figure 14. OIP3/OIP2 vs. Frequency at Various VVA Attenuation Values; Figure 15. OIP3/OIP2 vs. Frequency at Various DSA Values, Figure 16. OIP3/OIP2 vs. Frequency for Various Temperatures Figure 17. OIP3 vs. Input Power for Various Temperatures at 620 MHz,
Figure 18. OIP2 vs. Input Power for Various Temperatures at 620 MHz, Figure 19. Noise Figure vs. Frequency for Various Temperatures at Figure 20. Noise Figure vs. Frequency for Various Temperatures at Figure 21. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation; Figure 22. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. DSA Attenuation; Figure 23. Gain, OP1dB, OIP3, OIP2, Noise Figure vs. VVA Attenuation;
Figure 36. Return Loss of Single-Ended RF Output S22 from 0.5 GHz to
1.0 GHz
Figure 37. Amplifier 1 and Amplifier 2 Supply Current vs. Frequency for
interface an RF DAC to the power amplifier in a transmitter. second stage high linearity amplifier. tial signal to a single-ended signal via the integrated balun. included to provide dc bias for the RF DAC. and output reflection coefficient to the RF DAC and PA. Table 7. Register Writes for the Control of VVA
10 VVA_ANALOG (Pin 30) to VVA
0 VVA CONTROL
Figure 38. RF Signal Chain
Figure 39. Basic Connections Table 8. Basic Connections
5 V 13, 17 V50AMP1,
capacitors are located close to the pins. are located close to the pin. transceiver output in differential configuration. VVA 30 VVA_ANALOG External VVA control voltage input Voltage input pin to control VVA attenuation. analyzer, noise figure meter, or spectrum analyzer. Serial Port 33 SDO SPI data output 1.8 V to 3.3 V tolerant logic levels. 34 SCLK SPI clock 1.8 V to 3.3 V tolerant logic levels. 35 SDI SPI data input 1.8 V to 3.3 V tolerant logic levels. 36 CS Chip select active low 1.8 V to 3.3 V tolerant logic levels. Chip Selection 28, 29 CS4, CS5 Chip selection. Connect these pins to ground. 1.8 V to 3.3 V tolerant logic levels. GND Ground Connect these pins to the ground of the PCB.
subdivided into the major functional blocks, as shown in Table 9. Table 9. Memory Map Functional Groups hardware configuration to select the desired mode. Table 10. Mode Selection and Setup Registers
0 TXEN = 0 0x102, 0x107 to 0x10A
1 TXEN = 1 0x112, 0x117 to 0x11A
of the registers (see Table 11). Table 11. Control Registers for the Modes individual blocks that the particular enable bit controls. Figure 40. Signal Path Enable Block Diagram
Figure 41. Auxiliary Mux Block Diagram Table 12. Auxiliary Mux Programming Guide internal control voltage signal to control VVA attenuation. AMUX_2_SEL Register 0x120, Bit 3 ADC input selection. 0 Proportional to absolute temperature (PTAT) to ADC input. AMUX_1_SEL Register 0x120, Bits[2:0] Select mux output.
interface provides users with added flexibility and customization. ID bits, and nine register address bits, followed by eight data bits. first and end with the LSB by default. logic level (see the digital logic parameter in Table 2).
3.3 V output levels by setting SPI_1P8_3P3_CTRL bit
Figure 42. Multiple Chip Configuration to Share SPI Bus
- Set up the SPI interface. See Table 13.
- Set up the common parameters, including auxiliary mux
control. See Table 14 and Table 15.
- Set up the operating mode. See Table 16 to Table 19.
a. Set the attenuation on the DSA. b. Enable or disable the amplifiers. c. Set the amplifier reference currents. d. Set the amplifier for linearity optimization. e. Measure the internal temperature. Table 13. SPI Interface Setup Table 14. Signal Path Trim Table 15. Auxiliary Mux Control Table 16. Power-Down Mode Setup, TXEN = Logic Level 0 Table 17. Normal Operating Mode Setup, TXEN = Logic Level 1 Table 18. Linearity Optimization
Table 19. Internal Temperature Measurement from ADC Conversion
The primary setup used to characterize the ADL6316 is shown in Figure 49. The setup measures gain, HD2, HD3, OIP2, and OIP3. Figure 49. General Characterization Setup
Table 21. Register Summary
Table 22. Bit Descriptions for ADI_SPI_CONFIG
Table 23. Bit Descriptions for REG_0X0001
7 SINGLE_INSTRUCTION Single Instruction 0x0 R/W
6 CSB_STALL CS Stall 0x0 R/W
5 MASTER_SLAVE_RB Master Slave Readback 0x0 R/W
0 MASTER_SLAVE_TRANSFER Master Slave Transfer 0x0 R/W
Table 24. Bit Descriptions for CHIPTYPE Table 25. Bit Descriptions for PRODUCT_ID_L Table 26. Bit Descriptions for PRODUCT_ID_H
Table 27. Bit Descriptions for SCRATCHPAD Table 28. Bit Descriptions for SPI_REV Table 29. Bit Descriptions for VARIANT_FEOL Table 30. Bit Descriptions for BEOL_SIF Table 31. Bit Descriptions for SPARE_0012
Table 32. Bit Descriptions for SPARE_013 Table 33. Bit Descriptions for SIG_PATH0_0 0: Disable auxiliary mux band gap. 1: Enable auxiliary mux band gap.
Table 34. Bit Descriptions for SIG_PATH1_0
1 IP3_OFF Turn off linearization optimization functionality for
0: Turn on linearization optimization functionality. 1: Turn off linearization optimization functionality. Table 35. Bit Descriptions for SIG_PATH2_0
Table 36. Bit Descriptions for SIG_PATH3_0 Table 37. Bit Descriptions for SIG_PATH4_0 Table 38. Bit Descriptions for SIG_PATH5_0 Table 39. Bit Descriptions for SIG_PATH6_0
0 EN_IBIASGEN_RESISTOR Set Bias Generator to Use Resistor Reference 0x0 R/W
Table 40. Bit Descriptions for SIG_PATH7_0
7 BYPASS_TRM_AMP1_IREF_0 Bypass Fused Value of TRM_AMP1_IREF_0 0x0 R/W
4 TRM_AMP1_IREF_SEL_0 Amplifier 1 IREF Trim Select 0 0x0 R/W
Table 41. Bit Descriptions for SIG_PATH8_0
7 BYPASS_TRM_AMP1_EN_0 Bypass Fused Value of AMP1_EN_0 Internal Trim Data 0x0 R/W
0 AMP1_EN_0 Enable Amplifier 1 (TXEN = 0) 0x0 R/W
Table 42. Bit Descriptions for SIG_PATH9_0
7 BYPASS_TRM_AMP2_IREF_0 Bypass Fused Value of TRM_AMP2_IREF_0 0x0 R/W
4 TRM_AMP2_IREF_SEL_0 Amplifier 2 IREF Trim Select 0 0x0 R/W
Table 43. Bit Descriptions for SIG_PATHA_0
7 BYPASS_TRM_AMP2_EN_0 Bypass Fused Value of AMP2_EN_0 Internal Trim Data 0x0 R/W
0 AMP2_EN_0 Enable Amplifier 2 (TXEN = 0) 0x0 R/W
Table 44. Bit Descriptions for SIG_PATHB_0 Table 45. Bit Descriptions for SIG_PATH2_1
Table 46. Bit Descriptions for SIG_PATH7_1
7 BYPASS_TRM_AMP1_IREF_1 Bypass Fused Value of TRM_AMP1_IREF_1 0x0 R/W
4 TRM_AMP1_IREF_SEL_1 Amplifier 1 IREF Trim Select 1 0x0 R/W
Table 47. Bit Descriptions for SIG_PATH8_1
7 BYPASS_TRM_AMP1_EN_1 Bypass Fused Value of AMP1_EN_1 Internal Trim Data 0x0 R/W
0 AMP1_EN_1 Enable Amplifier 1 (TXEN = 1) 0x0 R/W
Table 48. Bit Descriptions for SIG_PATH9_1
7 BYPASS_TRM_AMP2_IREF_1 Bypass Fused Value of TRM_AMP2_IREF_1 0x0 R/W
4 TRM_AMP2_IREF_SEL_1 Amplifier 2 IREF Trim Select 1 0x0 R/W
Table 49. Bit Descriptions for SIG_PATHA_1
7 BYPASS_TRM_AMP2_EN_1 Bypass Fused Value of AMP2_EN_1 Internal Trim Data 0x0 R/W
0 AMP2_EN_1 Enable Amplifier 2 (TXEN = 1) 0x0 R/W
Table 50. Bit Descriptions for SIG_PATHB_1 Table 51. Bit Descriptions for AMUX_SEL Table 52. Bit Descriptions for MULTI_FUNC_CTRL_0111
4 SPI_1P8_3P3_CTRL SPI Supply Control 0x0 R/W
Table 53. Bit Descriptions for ADC_CONTROL 0: Disable ADC clock divider. 1: Enable ADC clock divider. Table 54. Bit Descriptions for ADC_EOC
0 ADC_EOC ADC End of Conversion (EOC) 0x0 R
Table 55. Bit Descriptions for ADC_OUT Table 56. Bit Descriptions for GENERIC_READBACK_2
Table 57. Bit Descriptions for GENERIC_READBACK_3 Table 58. Bit Descriptions for GENERIC_READBACK_4
3.50 REF
8.40 REF
0.530 REF
3.50 BSC
8.50 BSC
4.15 BSC
Figure 50. 38-Terminal Land Grid Array [LGA] 2 Measured at the exposed pad. registered trademarks are the property of their respective owners.