ADL5331 (Rev. A)
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1 MHz to 1.2 GHz VGA with 30 dB Gain Control Range Data Sheet ADL5331 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Voltage-controlled amplifier/attenuator Operating frequency: 1 MHz to 1.2 GHz Optimized for controlling output power High linearity: OIP3 47 dBm @ 100 MHz Output noise floor: −149 dBm/Hz @ maximum gain Input impedance: 50 Ω Output impedance: 20 Ω Wide gain-control range: 30 dB Linear-in-dB gain control function: 40 mV/dB Single-supply voltage: 4.75 V to 5.25 V
APPLICATIONS
Transmit and receive power control at RF and IF CATV distribution FUNCTIONAL BLOCK DIAGRAM INLO VPS1 COM1 INHI COM2 OPLO OPHI IPBS GAIN CONTROL BIAS AND VREF GAIN COM2 RFOUT COM2 VPS2 VPS2 VPS2 COM1 VPS1 VPS2VPS2 COM2COM2OPBSNC ENBL VPS2 RFIN 07593-001 INPUT GM STAGE OUTPUT (TZ) STAGE CONTINUOUSLY VARIABLE ATTENUATOR ADL5331 Figure 1. GENERAL DESCRIPTION The ADL5331 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies up to 1.2 GHz. The balanced structure of the signal path maximizes signal swing, eliminates common-mode noise and minimizes distortion while it also reduces the risk of spu- rious feed-forward at low gains and high frequencies caused by parasitic coupling. The 50 Ω differential input system converts the applied differential voltage at INHI and INLO to a pair of differential currents with high linearity and good common-mode rejection. The signal currents are then applied to a proprietary voltage- controlled attenuator providing precise definition of the overall gain under the control of the linear-in-dB interface. The GAIN pin accepts a voltage from 0 V at a minimum gain to 1.4 V at a full gain with a 40 mV/dB scaling factor over most of the range. The output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. The output stage provides a differential output at OPHI and OPLO, which must be pulled up to the supply with RF chokes or a center-tapped balun. The ADL5331 consumes 240 mA of current including the out- put pins and operates off a single supply ranging from 4.75 V to 5.25 V . A power-down function is provided by applying a logic low input on the ENBL pin. The current consumption in power-down mode is 250 μA. The ADL5331 is fabricated on an Analog Devices, Inc., pro- prietary high performance, complementary bipolar IC process. The ADL5331 is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP package and is specified for operation from ambient temperatures of −40°C to +85°C. An evaluation board is also available.
Rev. A | Page 2 of 15 TABLE OF CONTENTS
REVISION HISTORY
10/2017—Rev. 0 to Rev. A Change to Figure 2 and U 5/2009—Revision 0: Initial Version
Rev. A | Page 3 of 15 SPECIFICATIONS VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match. Table 1. Parameter Conditions Min Typ Max Unit GENERAL Usable Frequency Range 0.001 1.2 GHz Nominal Input Impedance 50 Ω Nominal Output Impedance 20 Ω FREQUENCY INPUT = 100 MHz Gain Control Span ±3 dB gain law conformance 30 dB Minimum Gain VGAIN = 0.1 V −14 dB Maximum Gain VGAIN = 1.4 V 17 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB Gain Control Slope 40 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 700 mV Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 47 dBm Output Noise Floor VGAIN = 1.4 V −149 dBm/Hz Noise Figure VGAIN = 1.4 V 9 dB FREQUENCY INPUT = 400 MHz Gain Control Span ±3 dB gain law conformance 30 dB Minimum Gain VGAIN = 0.1 V −15 dB Maximum Gain VGAIN = 1.4 V 15 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB Gain Control Slope 39.5 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 730 mV Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 39 dBm Output Noise Floor 20 MHz carrier offset, VGAIN = 1.4 V −150 dBm/Hz Noise Figure VGAIN = 1.4 V 9 dB FREQUENCY INPUT = 900 MHz Gain Control Span ±3 dB gain law conformance 35 dB Minimum Gain VGAIN = 0.1 V −18 dB Maximum Gain VGAIN = 1.4 V 15 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB Gain Control Slope 37 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 800 mV Third-Order Harmonic −8 dBm output at 900 MHz fundamental −75 dBc Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 32 dBm Output Noise Floor 20 MHz carrier offset, VGAIN = 1.4 V −150 dBm/Hz Noise Figure VGAIN = 1.4 V 9 dB GAIN CONTROL INPUT Pin GAIN Gain Control Voltage Range1 0.1 1.4 V Incremental Input Resistance Pin GAIN to Pin COM1 1 MΩ Response Time Full scale, to within 1 dB of final gain 380 ns 3 dB gain step, POUT to within 1 dB of final gain 20 ns POWER SUPPLIES Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL Voltage 4.75 5 5.25 V Current, Nominal Active 240 mA ENBL, Logic 1, Device Enabled 2.3 V ENBL, Logic 0, Device Disabled 0.8 V Current, Disabled ENBL = Logic 0 250 µA 1 Minimum gain voltage varies with frequency (see Figure 3, Figure 4, and Figure 5).
Rev. A | Page 4 of 15 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage VPS1 5.5 V Supply Voltage VPS2 5.5 V VPS2 to VPS1 ±200 mV RF Input Power 5 dBm at 50 Ω OPHI, OPLO 5.5 V ENBL VPS1 GAIN VPS1 Internal Power Dissipation 1.2 W θJA (with Pad Soldered to Board) 56.1°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
- EXPOSED PAD. THE EXPOSED PAD MUST BE
BOTH THERMALLY AND ELECTRICALLY. Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1, 6 VPS1 Positive Supply. Nominally equal to 5 V. 2, 5 COM1 Common for the Input Stage. 3, 4 INHI, INLO Differential Inputs, AC-Coupled. 8 IPBS Input Bias. Normally ac-coupled to VPS1. A 10 nF capacitor is recommended. 9 OPBS Output Bias. Internally compensated, do not connect externally. 10 to 12, 14, 17 COM2 Common for the Output Stage. 13, 18 to 22 VPS2 Positive Supply. Nominally equal to 5 V. 15, 16 OPLO, OPHI Differential Outputs. Bias to VPOS with RF chokes. 23 ENBL Device Enable. Apply logic high for normal operation. 24 GAIN Gain Control Voltage Input. Nominal range is 0 V to 1.4 V.
Rev. A | Page 11 of 15 INLO INHI GAIN OPLO OPHI 10dB DIRECTIONAL COUPLER 10dB ATTENUATOR VPOS COMM ADL5331 +5V +5V +5V COMM VOUT VPOS VSET INHI INLOCLPF AD8319 LOG AMP DAC RFIN SIGNAL RFOUT SIGNAL 390Ω 1kΩ SETPOINT VOLTAGE 220pF 1nF 1nF 120nH 120nH 10nF 10nF 07593-021 10nF 10nF F igure 19. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5331 F igure 19 shows the basic connections for operating the AD8319 log detector in an automatic gain control (AGC) loop with the ADL5331. The gain of the ADL5331 is controlled by the output pin of the AD8319. The voltage, VOUT, has a range of 0 V to near VPOS. To avoid overdrive recovery issue s, the AD8319 output voltage can be scaled down using a resistive divider to interface with the 0.1 V to 1.4 V gain control range of the ADL5331. A coupler/attenuation of 21 dB is used to match the desired maximum output power from the VGA to the top end of the linear operating range of the AD8319 (approximately −5 dBm at 900 MHz). Figure 20 shows the transfer function of the output power vs. the VSET voltage over temperature for a 100 MHz sine wave with an input power of −1.5 dBm. Note that the power control of the AD8319 has a negative sense. Dec reasing VSET, which corresponds to demanding a higher signal from the ADL5331, increases gain. T his AGC loop is capable of controlling signals of ~30 dB, which is the gain range limitation on the ADL5331. Across the top 25 dB range of output power, the linear conformance error is within ±0.5 dB over temperature. 3.00 2.25 1.50 –0.75 –1.50 –2.25 –3.00 0.75 –10 –15 –20 VSET (V) OUTPUT POWER (dBm) ERROR FROM STRAIGHT LINE AT 25°C (dB) +85°C +25°C –40°C 07593-022 F igure 20. ADL5331 Output Power vs. AD8319 Setpoint Voltage, PIN = 0 dBm at 100 MHz
Rev. A | Page 13 of 15 INTERFACING TO AN IQ MODULATOR The basic connections for interfacing the ADL5331 with the ADL5385 are shown in Figure 24. The ADL5385 is an RF quadrature modulator with an output frequency range of 50 MHz to 2.2 GHz. It offers excellent phase accuracy and amplitude balance, enabling high performance direct RF modulation for communication systems. The output of the ADL5385 is designed to drive 50 Ω loads and easily interfaces with the ADL5331. The input to the ADL5331 can be driven single-ended, as shown in Figure 17. Similar configurations are possible with the ADL537x family of quadrature modulators. These modulators can provide outputs from 500 MHz to 4 GHz. SOLDERING INFORMATION On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the chip’s ground. Solder the paddle to the low impedance ground plane on the printed circuit board to ensure specified electrical performance and to provide thermal relief. It is also recom- mended that the ground planes on all layers under the paddle be stitched together with vias to reduce thermal impedance. 10nF 10nF INHI INLO RF OUTPUT 10nF 10nF OPHI COMMVPOS OPLO ETC1-1-13 LO IBBP IBBN QBBP QBBN COMMVPOS GAIN CONTROL 100pF 100pF DIFFERENTIAL I/Q BASEBAND INPUTS DAC DAC VOUTADL5385 IQ MOD 68µH 68µH ADL5331 RF VGA 07593-030 Fi gure 24. ADL5385 Quadrature Modulator and ADL5331 Interface
Figure 25. ADL5331 Single-Ended Input/Output Evaluation Board
0.05 MAX
0.02 NOM
0.203 REF
0.20 MIN
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.