ADL5330

ADL5330 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

10 MHz to 3 GHz VGA with

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Suppor t www.analog.com

FEATURES

Voltage controlled amplifier/attenuator Operating frequency 10 MHz to 3 GHz Optimized for controlling output power High linearity: OIP3 31 dBm at 900 MHz Output noise floor: −150 dBm/Hz at 900 MHz 50 Ω input and output impedances Single-ended or differential operation Wide gain control range: −34 dB to +22 dB at 900 MHz Linear in dB gain control function, 20 mV/dB Single-supply 4.75 V to 5.25 V

APPLICATIONS

Transmit and receive power control at RF and IF FUNCTIONAL BLOCK DIAGRAM INLO VPS1 COM1 INHI COM2 OPLO OPHI IPBS GAIN CONTROL BIAS AND VREF GAIN BALUN COM2 RFOUT COM2 VPS2 VPS2 VPS2 COM1 VPS1 VPS2VPS2 COM2COM1OPBSVREF ENBL VPS2 RFIN 05134-001 INPUT GM STAGE O/P (TZ) STAGE CONTINUOUSLY VARIABLE ATTENUATOR Figure 1. GENERAL DESCRIPTION The ADL5330 is a high performance, voltage controlled, variable gain amplifier (VGA)/attenuator for use in applications with frequencies up to 3 GHz. The balanced structure of the signal path minimizes distortion while it also reduces the risk of spurious feedforward at low gains and high frequencies caused by parasitic coupling. While operation between a balanced source and load is recommended, a single sided input is internally converted to differential form. The input impedance is 50 Ω from INHI to INLO. The outputs are usually coupled into a 50 Ω grounded load via a 1:1 balun. A single supply of 4.75 V to 5.25 V is required. The 50 Ω input system converts the applied voltage to a pair of differential currents with high linearity and good common rejection even when driven by a single sided source. The signal currents are then applied to a proprietary voltage controlled attenuator providing precise definition of the overall gain under the control of the linear in dB interface. The GAIN pin accepts a voltage from 0 V at minimum gain to 1.4 V at full gain with a 20 mV/dB scaling factor. The output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. The output stage sets the 50 Ω differential output impedances and drives the OPHI and OPLO pins. The ADL5330 has a power-down function. It can be powered down by a Logic LO input on the ENBL pin. The current consumption in power-down mode is 250 μA. The ADL5330 is fabricated on an Analog Devices, Inc., proprietary high performance, complementary bipolar IC process. The ADL5330 is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP package and is specified for operation from ambient temperatures of −40°C to +85°C. An evaluation board is also available.

Rev. B | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

11/2017—Rev. A to Rev. B 6/2005—Rev. 0 to Rev. A 4/2005—Revision 0: Initial Version

Rev. B | Page 3 of 24 SPECIFICATIONS VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match. Table 1. Parameter Conditions Min Typ Max Unit GENERAL Usable Frequency Range 0.01 3 GHz Nominal Input Impedance Via 1:1 single-sided-to-differential balun 50 Ω Nominal Output Impedance Via 1:1 differential-to-single-sided balun 50 Ω

100 MHz

Gain Control Span ±3 dB gain law conformance 58 dB Maximum Gain VGAIN = 1.4 V 23 dB Minimum Gain VGAIN = 0.1 V −35 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB Gain Control Slope 20.7 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.88 V Input Compression Point VGAIN = 1.2 V 1.8 dBm Input Compression Point VGAIN = 1.4 V −0.3 dBm Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 38 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −140 dBm/Hz Noise Figure VGAIN = 1.4 V 7.8 dB Input Return Loss2 1 V < VGAIN < 1.4 V −12.8 dB Output Return Loss2 −15.5 dB

450 MHz

Gain Control Span ±3 dB gain law conformance 57 dB Maximum Gain VGAIN = 1.4 V 22 dB Minimum Gain VGAIN = 0.1 V −35 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V, (differential output) 0.08 dB Gain Control Slope 20.4 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.89 V Input Compression Point VGAIN = 1.2 V 3.3 dBm Input Compression Point VGAIN = 1.4 V 1.2 dBm Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 36 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −146 dBm/Hz Noise Figure VGAIN = 1.4 V 8.0 dB Input Return Loss2 1 V < VGAIN < 1.4 V −19 dB Output Return Loss2 −13.4 dB

900 MHz

Gain Control Span ±3 dB gain law conformance 53 dB Maximum Gain VGAIN = 1.4 V 21 dB Minimum Gain VGAIN = 0.2 V −32 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.14 dB Gain Control Slope 19.7 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.92 V Input Compression Point VGAIN = 1.2 V 2.7 dBm Input Compression Point VGAIN = 1.4 V 1.3 dBm Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 31.5 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −144 dBm/Hz Noise Figure VGAIN = 1.4 V 9.0 dB

Rev. B | Page 4 of 24 Parameter Conditions Min Typ Max Unit Input Return Loss2 1 V < VGAIN < 1.4 V −18 dB Output Return Loss2 −18 dB

2200 MHz

Gain Control Span ±3 dB gain law conformance 46 dB Maximum Gain VGAIN = 1.4 V 16 dB Minimum Gain VGAIN = 0.6 V −30 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.23 dB Gain Control Slope 16.7 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.06 V Input Compression Point VGAIN = 1.2 V 0.9 dBm Input Compression Point VGAIN = 1.4 V −2.0 dBm Output Third-Order Intercept (OIP3) V GAIN = 1.4 V 21.2 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −147 dBm/Hz Noise Figure VGAIN = 1.4 V 12.5 dB Input Return Loss2 1 V < VGAIN < 1.4 V −11.7 dB Output Return Loss2 −9.5 dB

2700 MHz

Gain Control Span ±3 dB gain law conformance 42 dB Maximum Gain VGAIN = 1.4 V 10 dB Minimum Gain VGAIN = 0.7 V −32 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, V GAIN = 1.0 V (differential output) 0.3 dB Gain Control Slope 16 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.15 V Input Compression Point VGAIN = 1.2 V 1.2 dBm Input Compression Point VGAIN = 1.4 V −0.9 dBm Output Third-Order Intercept (OIP3) V GAIN = 1.4 V 17 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −152 dBm/Hz Noise Figure VGAIN = 1.4 V 14.7 dB Input Return Loss2 1 V < VGAIN < 1.4 V −9.7 dB Output Return Loss2 −5 dB GAIN CONTROL INPUT GAIN pin Gain Control Voltage Range3 0 1.4 V Incremental Input Resistance GAIN pin to COM1 pin 1 MΩ Response Time Full scale: to within 1 dB of final gain 380 ns 3 dB gain step, POUT to within 1 dB of final gain 20 ns POWER SUPPLIES Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL Voltage 4.75 5 5.25 V Current, Nominal Active VGN = 0 V 100 mA V GN = 1.4 V 215 mA Current, Disabled ENBL = LO 250 μA 1 Noise floor varies slightly with output power level. See Figure 9 to Figure 13. 2 See Figure 27 and Figure 29 for differential input and output impedances. 3 Minimum gain voltage varies with frequency. See Figure 3 to Figure 7.

Rev. B | Page 5 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage VPS1, VPS2 5.5 V RF Input Power at Maximum Gain 5 dBm at 50 Ω OPHI, OPLO 5.5 V ENBL VPS1, VPS2 GAIN 2.5 V Internal Power Dissipation 1.1 W θJA (with Pad Soldered to Board) 60°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering 60 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

1. EXPOSED PAD. THE EXPOSED PAD UNDER

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1, 6, 13, 18 to 22 VPS1, VPS2 Positive Supply. Nominally equal to 5 V. 2, 5, 10 COM1 Common for Input Stage. 3, 4 INHI, INLO Differential Inputs, AC-Coupled. 7 VREF Voltage Reference. Output at 1.5 V; normally ac-coupled to ground. 8 IPBS Input Bias. Normally ac-coupled to ground. 9 OPBS Output Bias. AC-Coupled to ground. 11 GNLO Gain Control Common. Connect to ground. 12, 14, 17 COM2 Common for Output Stage. 15 OPLO Low Side of Differential Output. Bias to VP with RF chokes. 16 OPHI High Side of Differential Output. Bias to VP with RF chokes. 23 ENBL Device Enable. Apply logic high for normal operation. 24 GAIN Gain Control Voltage Input. Nominal range 0 V to 1.4 V. impedance path, thermally and electrically.

OP1dB, decrease with decreasing gain. Figure 31. Simplified Schematic inputs to avoid upsetting operation of the device. pin, with maximum gain occurring at the highest voltage. can be taken single-ended from either output. cases, it is necessary to use dc blocking in the output signal path.

1 AVG

2.13996994 GHz

Figure 43. Single-Carrier WCDMA Spectrum at 2140 MHz; at 50 MHz carrier offset, initially falls and then levels off. Figure 44. ACPR and Noise vs. Output Power; Single-Carrier input power is held constant at −19 dBm. Figure 45. Output Power, ACPR, and Noise vs. VGAIN;

Rev. B | Page 19 of 24 CDMA2000 TRANSMIT APPLICATION To test the compliance to the CDMA2000 base station standard, an 880 MHz, three-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A cavity-tuned filter with a 4.6 MHz pass band was used to reduce noise from the signal source being applied to the device. Figure 46 shows the spectrum of the output signal under nominal conditions. Total POUT of the three-carrier signal is equal to 0.46 dBm and VGAIN = 1.4 V . Adjacent and alternate channel power ratio is measured in a 30 kHz bandwidth at 750 kHz and 1.98 MHz carrier offset, respectively. 05134-046 SPAN 15MHzCENTER 880MHz 1.5MHz/ A 1RM EXT –10 –30 –40 –20 –50 –60 –70 –80 –90 –100 –110 1 [T1] –18.55dBm 880MHz CH PWR 0.46dBm ACP Up –65.13dB ACP Low –64.40dB ALT1 Up –89.05dB ALT1 Low –83.68dB ALT2 Up –80.72dB ALT2 Low –81.24dB CU3 CU3CU2 CU2CU1 CU1CL1 CL1CL2 CL2CL3 CL3 C0 C0 0.4 dB OFFSET REF LVL –10dBm MARKER 1 [T1] –18.55dBm 880.00000000MHz RBW 30kHz VBW 300kHz SWT 200ms RF ATT 10dB MIXER –10dBm UNIT dBm F igure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model at −23 dBm Total Input Power, VGAIN = 1.4 V, ACPR Measured at 750 kHz and

1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter

(Pass Band = 4.6 MHz) In testing, by holding the gain control voltage steady at 1.4 V , input power was swept. Figure 47 shows ACPR and noise floor vs. total output power. Noise floor is measured at 1 MHz bandwidth at 4 MHz carrier offset. 05134-047 NOISE – dBm @ 4MHz CARRIER OFFSET (1MHz RBW) –90 –10 –20 –30 –40 –50 –60 –70 –80 TOTAL OUTPUT POWER (dBm) 15–30 –25 –20 –15 –10 –5 0 5 10 ACPR – dBc (30kHz RBW) –30 –50 –40 –60 –70 –80 –90 –100 –110 –120 NOISE 4MHz OFFSET ACPR 750kHz OFFSET ACPR 1.98MHz OFFSET F igure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000 Test Model; VGAIN = 1.4 V (Fixed), ACPR Measured in 30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset The results show that up to a total output power of +8 dBm, ACPR remains in compliance with the standard (<−45 dBc at 750 kHz and <−60 dBc at 1.98 MHz). At low output power levels, ACPR at 1.98 MHz carrier offset degrades as the noise floor of the ADL5330 becomes the dominant contributor to measured ACPR. Measured noise at 4 MHz carrier offset begins to increase sharply above 0 dBm output power. This increase is not due to noise but results from increased carrier-induced distortion. As output power drops below 0 dBm total, the noise floor drops towards −85 dBm. With a fixed input power of −23 dBm, the output power was again swept by exercising the gain control input. V GAIN was swept from 0 V to 1.4 V . The resulting total output power, ACPR, and noise floor are shown in Figure 48. 05134-048 ACPR (dBc) NOISE – 4MHz CARRIER OFFSET – (1MHz RBW)–100 –30 –40 –50 –60 –70 –80 –90 V GAIN (V) TOTAL OUTPUT POWER (dBm) –10 –20 –30 –40 –50 –60 NOISE 4MHz OFFSET ACPR 750kHz OFFSET ACPR 1.98MHz OFFSET OUTPUT POWER F igure 48. Total Output Power and ACPR vs. VGAIN, 880 MHz Three-Carrier CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in 30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset Above VGAIN = 0.4 V , the ACPR is still in compliance with the standard. As the gain control input drops below 1.0 V , the noise floor drops below −90 dBm. SOLDERING INFORMATION On the underside of the chip scale package, there is an exposed compressed paddle. This paddle is internally connected to the chip’s ground. Solder the paddle to the low impedance ground plane on the printed circuit board to ensure specified electrical performance and to provide thermal relief. It is also recommended that the ground planes on all layers under the paddle be stitched together with vias to reduce thermal impedance.

Rev. B | Page 20 of 24 EVALUATION BOARD Figure 49 shows the schematic of the ADL5330 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 50 through Figure 53. The board is powered by a single-supply in the 4.75 V to 5.25 V range. The power supply is decoupled by 100 pF and 0.1 μF capacitors at each power supply pin. Additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. Table 5 details the various configuration options of the evaluation board. The output pins of the ADL5330 require supply biasing with 120 nH RF chokes. Both the input and output pins have 50 Ω differential impedances and must be ac-coupled. These pins are converted to single-ended with a pair of baluns (M/A-COM part number ETC1-1-13). Instead of using balun transformers, lumped-element baluns comprising passive L and C components can be designed. Alternate input and output RF paths with component pads are available on the circuit side of the board. Components M1 through M9 are used for the input interface, and M10 through M18 are used for the output interface. DC blocking capacitors of 100 pF must be installed in C15 and C16 for the input and C17 and C18 for the output. The C5, C6, C11, and C12 capacitors must be removed. An alternate set of SMA connectors, INPUT2 and OUT2, are used for this configuration. The ADL5330 can be driven single-ended; use the RF input path on the circuit side of the board. A set of 100 pF dc blocking capacitors must be installed in C15 and C16. C5 and C6 must be removed. Use the INPUT2 SMA to drive one of the differential input pins. The unused pin should be terminated to ground, as shown in Figure 34. The ADL5330 is enabled by applying a logic high voltage to the ENBL pin by placing a jumper across the SW1 header in the O position. Remove the jumper for disable. This pulls the ENBL pin to ground through the 10 kΩ resistor.

Figure 49. Evaluation Board Schematic

Table 5. Evaluation Board Configuration Options input to the 50 Ω differential input. C5 and C6 are dc blocks. provide dc biases for the output. high or low voltage, use the pin labeled O on the SW1 header. and C18. Use the alternate set of SMA connectors, INPUT2 and OUT2.

0.05 MAX

0.02 NOM

0.203 REF

0.20 MIN

Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.