ADL5320 (Rev. B)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 20
Technical content
400 MHz to 2700 MHz
¼ Watt RF Driver Amplifier Data Sheet ADL5320
FEATURES
Operation: 400 MHz to 2700 MHz Gain of 16.9 dB at 880 MHz OIP3 of 45.0 dBm at 880 MHz P1dB of 25.4 dBm at 880 MHz Noise figure: 4.1 dB at 880 MHz Power supply voltage: 3.3 V to 5 V Power supply current: 44 mA to 104 mA Dynamically adjustable bias No bias resistor required Thermally efficient, MSL-1 rated SOT-89 package Operating temperature range: −40°C to +105°C ESD rating of ±4 kV (Class 3A)
APPLICATIONS
(2) Figure 1. GENERAL DESCRIPTION The ADL5320 incorporates a dynamically adjustable biasing circuit that allows for the customization of OIP3 and P1dB performance from 3.3 V to 5 V without the need for an external bias resistor. This feature gives the designer the ability to tailor driver amplifier performance to the specific needs of the design. This feature also creates the opportunity for dynamic biasing of the driver amplifier, where a variable supply is used to allow for full 5 V biasing under large signal conditions and then can reduce the supply voltage when signal levels are smaller and lower power consumption is desirable. This scalability reduces the need to evaluate and inventory multiple driver amplifiers for different output power requirements from 22 dBm to 26 dBm output power levels. The ADL5320 is also rated to operate across the wide temperature range of −40°C to +105°C for reliable performance in designs that experience higher temperatures, such as power amplifiers. The 1∕4 watt driver amplifier also covers the 400 MHz to 2700 MHz wide frequency range and only requires a few external components to be tuned to a specific band within that wide range. This high performance, broadband RF driver amplifier is well suited for a variety of wired and wireless applications including cellular infrastructure, ISM band power amplifiers, defense equipment, and instrumentation equipment. A fully populated evaluation board is available. The ADL5320 also delivers excellent adjacent channel power ratio (ACPR) vs. output power and bias voltage. The driver can deliver greater than 17 dBm of output power at 2140 MHz while achieving an ACPR of −55 dBc at 5 V . If the bias is reduced to 3.3 V, the −55 dBc ACPR output power reduces to 9 dBm. –90 –80 –70 –60 –50 –40 –30 –20 –20 –15 –10 –5 0 5 10 15 20 ACPR @ 5MHz CARRIER OFFSET (dBc) POUT (dBm) SOURCE VCC = 5V VCC = 3.3V 05840-131 Figure 2. ACPR vs. Output Power, Single Carrier W-CDMA TM1-64 at
2140 MHz
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved.
Soldering Information and Recommended PCB
REVISION HISTORY
10/13—Rev. A to Rev. B Added Optimizing OP1dB Section, Table 10, Table 11, 6/12—Rev. 0 to Rev. A Added Application Section and Figure 2; Renumbered Changes to Operating Temperature Range Parameter, Added Thermal Resistance Section and Table 4; Renumbered Added High Temperature and 3.3 V Operation Section and Changes to Soldering Information and Recommended PCB Changed −82 dBc to −80 dBc in W-CDMA ACPR Performance 2/08—Revision 0: Initial Version Rev. B | Page 2 of 20
TA = 25°C, unless otherwise noted. Table 1.
3.3 V 5 V
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit OVERALL FUNCTION Frequency Range 400 2700 400 2700 MHz FREQUENCY = 880 MHz Gain1 15.6 16.3 16.9 17.5 dB vs. Frequency ±50 MHz ±0.2 ±0.3 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.6 ±0.6 dB Output 1 dB Compression Point 21.5 25.4 dBm Output Third-Order Intercept Δf = 1 MHz, POUT = 10 dBm per tone 34 45 dBm Noise Figure 3.2 4.1 dB FREQUENCY = 2140 MHz Gain1 12.2 12.4 13.2 14.0 dB vs. Frequency ±50 MHz ±0.3 ±0.33 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.7 ±0.8 dB Output 1 dB Compression Point 22.6 25.7 dBm Output Third-Order Intercept Δf = 1 MHz, POUT = 10 dBm per tone 32 42 dBm Noise Figure 3.7 4.4 dB FREQUENCY = 2600 MHz Gain1 10.7 11.5 12.5 13.4 dB vs. Frequency ±100 MHz ±0.2 ±0.6 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.6 ±1.1 dB Output 1 dB Compression Point 25.7 27.4 dBm Output Third-Order Intercept Δf = 1 MHz, POUT = 10 dBm per tone 29 37 dBm Noise Figure 4.1 5.1 dB POWER INTERFACE Pin RFOUT Supply Voltage 3.3 4.5 5 5.5 V Supply Current 44 104 124 mA vs. Temperature −40°C ≤ TA ≤ +85°C ±5.0 ±6.0 mA Power Dissipation VSUP = 3.3 V, VSUP = 5 V 145 520 mW 1 Guaranteed maximum and minimum specified limits on this parameter are based on six sigma calculations. Rev. B | Page 3 of 20
TYPICAL SCATTERING PARAMETERS VSUP = 5 V and TA = 25°C; the effects of the test fixture have been de-embedded up to the pins of the device. Table 2. Freq (MHz) S11 S21 S12 S22 Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Magnitude (dB) Angle (°) Rev. B | Page 4 of 20
junction-to-paddle thermal resistance (θJC) for the ADL5320. Table 4. Thermal Resistance 2 Based on simulation with JEDEC standard JESD51.
- THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND.
SOLDER TO A LOW IMPEDANCE GROUND PLANE. Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 RFIN RF Input. Requires a dc blocking capacitor. 2 GND Ground. Connect to a low impedance ground plane. the external power supply. RF path requires a dc blocking capacitor. Exposed Paddle Expose Paddle. Internally connected to GND. Solder to a low impedance ground plane.
Figure 4. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
800 MHz to 960 MHz
Figure 5. Gain vs. Frequency and Temperature, 800 MHz to 960 MHz Figure 6. Input Return Loss (S11), Output Return Loss (S22), and Reverse Figure 7. OIP3 and P1dB vs. Frequency and Temperature, Figure 8. OIP3 vs. POUT and Frequency, 800 MHz to 960 MHz Figure 9. Noise Figure vs. Frequency and Temperature,
Figure 10. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
2060 MHz to 2200 MHz
Figure 11. Gain vs. Frequency and Temperature, 2060 MHz to 2200 MHz Figure 12. Input Return Loss (S11), Output Return Loss (S22), and Reverse Figure 13. OIP3 and P1dB vs. Frequency and Temperature, Figure 14. OIP3 vs. POUT and Frequency, 2060 MHz to 2200 MHz Figure 15. Noise Figure vs. Frequency and Temperature,
Figure 16. Gain, P1dB, OIP3, and Noise Figure vs. Frequency,
2500 MHz to 2700 MHz
Figure 17. Gain vs. Frequency and Temperature, 2500 MHz to 2700 MHz Figure 18. Input Return Loss (S11), Output Return Loss (S22), and Reverse Figure 19. OIP3 and P1dB vs. Frequency and Temperature, Figure 20. OIP3 vs. POUT and Frequency, 2500 MHz to 2700 MHz Figure 21. Noise Figure vs. Frequency and Temperature,
Figure 28. Gain vs. Frequency and Temperature,
5 V Supply, 2060 MHz to 2200 MHz
Figure 29. OIP3 and P1dB vs. Frequency and Temperature, Figure 30. Noise Figure vs. Frequency and Temperature, 5 V Supply, Figure 31. Gain vs. Frequency and Temperature,
3.3 V Supply, 2060 MHz to 2200 MHz
Figure 32. OIP3 and P1dB vs. Frequency and Temperature, Figure 33. Noise Figure vs. Frequency and Temperature,
component spacing, and Table 12 lists the component values. Table 10. OP1dB, Gain, and IP3 Results with Optimized OP1dB Table 11. Matching Component Spacing for Optimized OP1dB 1SEE TABLE 12 FOR FREQUENCY SPECIFIC COMPONENTS. 2SEE TABLE 11 FOR RECOMMENDED COMPONENT SPACING. Figure 39. Component Values and Spacing for Increased OP1dB incorporates an instrument noise correction function. device particularly suitable for PA driver applications. Figure 40. ACPR vs. POUT, Single Carrier W-CDMA (Test Model 1−64) at
2140 MHz Evaluation Board
Table 12. Matching Component Values for Optimized OP1dB
Figure 41. This evaluation board uses 25 mil wide traces and is options for other frequency bands are also provided in Table 13. voltage of 5 V is recommended. Figure 41. Evaluation Board, 2110 MHz to 2170 MHz Figure 42. Evaluation Board Layout and Default Component Placement for Table 13. Evaluation Board Configuration Options
2110 MHz to
2170 MHz (Default
2300 MHz to
2400 MHz
2500 MHz to
2700 MHz
Table 14. Recommended Component Spacing on Evaluation Board
Figure 43. Evaluation Board Layout and Component Placement
450 MHz to 500 MHz Operation
Figure 44. Evaluation Board Layout and Component Placement
800 MHz to 960 MHz Operation
Figure 45. Evaluation Board Layout and Component Placement
2300 MHz to 2400 MHz Operation
Figure 46. Evaluation Board Layout and Component Placement
2500 MHz to 2700 MHz Operation
1.50 TYP
3.00 TYP
Figure 47. 3−Lead Small Outline Transistor Package [SOT-89]
Rev. B | Page 19 of 20
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05840-0-10/13(B) Rev. B | Page 20 of 20