ADL5315 AD | Alldatasheet
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Precision Wide Range (3 nA to 3 mA) High-Side Current Mirror ADL5315 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Accurately mirrors input current (1:1 ratio) over 6 decades Linearity 1% from 3 nA to 3 mA Stable mirror input voltage Voltage held 1 V below supply using internal reference or can be set externally Adjustable input current limit
2.7 V to 8 V single-supply operation
Miniature 8-lead LFCSP (2 mm × 3 mm)
APPLICATIONS
Optical power monitoring from a single photodiode General voltage biasing with precision current monitoring Voltage-to-current conversion FUNCTIONAL BLOCK DIAGRAM VOLTAGE REFERENCE CURRENT LIMITING COMM VSET NC INPT IPD CURRENT MIRROR 1:1 ADL5315 2 7 SREF VPOS 20kΩ RLIM IOUT IPD 05694-001 Figure 1. GENERAL DESCRIPTION The ADL5315 is a wide input current range, precision high-side current mirror featuring a stable and user-adjustable input voltage. It is optimized for use with PIN photodiodes, but its flexibility and wide operating range make it suitable for a broad array of additional applications. Over the 3 nA to 3 mA range, the current sourced from the INPT pin is accurately mirrored with a 1:1 ratio and sourced from the IOUT output pin. In a typical photodiode application, the output drives a current- input logarithmic amplifier to produce a linear-in-dB output representing the optical power incident upon the photodiode. For linear voltage output, a single resistor to ground is all that is required. The photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. The voltage at the INPT pin is temperature stable with respect to the voltage at the VSET input pin, which it tracks. A temperature stable reference voltage is provided at the SREF pin, which, when tied to VSET, fixes the voltage at INPT 1.0 V below VPOS. VSET can also be driven from an external source. The VSET input has very low input current and can be driven as low as the bottom rail, facilitating nonloading voltage-to- current conversion as well as minimizing dark current in photodiode applications. The ADL5315 also features adjustable input current limiting using an external resistor from RLIM to VPOS. The maximum current sourced by INPT (and IOUT) can be set between 1 mA and 16 mA, beyond which the voltage at INPT falls rapidly from its setpoint. Connecting RLIM directly to VPOS provides basic input short-circuit protection with the default current limit of 16 mA typical. The ADL5315 is available in a 2 mm × 3 mm, 8-lead LFCSP and is specified for operation from −40°C to +85°C.
Rev. 0 | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 3 of 20 SPECIFICATIONS VPOS = 5 V , VSET = 4 V , IINPT = 3 μA, TA = 25°C, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit CURRENT MIRROR OUTPUT IOUT (Pin 8) Current Gain from INPT to IOUT 0.99 1.00 1.01 Current Gain from INPT to IOUT −40°C < TA < +85°C 0.97 1.00 1.03 A/A Nonlinearity 3 nA < IPD < 3 mA 0.25 1.00 % Small Signal Bandwidth IINPT = 3 nA 1 kHz I INPT = 3 μA 1 MHz Wideband Noise at IPDM IINPT = 3 μA, CSET = 2.2 nF 20 nA rms Specified Output Voltage Range 0 VPOS − 1 V IOUT × ROUT Product IINPT = 3 μA 900 V MIRROR INPUT, VOLTAGE CONTROL INPT (Pin 1), VSET (Pin 2), SREF (Pin 3) Specified Input Current Range, IINPT Flows from INPT pin 3n 3m A Specified VSET Voltage Range 2.7 V < VPOS < 6.5 V 0 VPOS − 1 V 6.5 V < VPOS < 8 V VPOS − 6.5 VPOS − 1 V Incremental Gain from VSET to INPT 0.2 V < VSET < 7.0 V 0.98 1 1.02 V/V Incremental Input Resistance at VSET VSET = 4.0 V >100 GΩ Input Bias Current at VSET VSET = 4.0 V <30 pA SREF Voltage, Relative to VPOS 2.7 V < VPOS < 8 V −1.04 −1.0 −0.97 V OVERCURRENT PROTECTION INPT Current Limit VINPT drops to 0 V, RLIM = 0 Ω 16 mA V INPT drops to 0 V, RLIM = 3 kΩ 6.4 8 9.6 mA POWER SUPPLY VPOS (Pin 6) Supply Voltage Range 2.7 8 V Quiescent Current IINPT = 3 μA 1.8 2.2 mA IINPT = 3 mA 8.3 10.2 mA
Rev. 0 | Page 4 of 20 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage 8 V Input Current at INPT 20 mA Internal Power Dissipation 500 mW θJA (Soldered Exposed Paddle) 80°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
1 INPT
2 VSET
3 SREF
4 COMM
8 IOUT
6 VPOS
5 RLIM
Figure 2. 8-Lead LFCSP Table 3. Pin Function Descriptions 1 INPT Input Current. Pin sources current only. VPOS − 1 V. Optional shielding of INPT trace. 5 RLIM External Resistor to VPOS. Sets current limit at INPT from 1 mA to 16 mA. ILIM = 48 V/(RLIM + 3 kΩ). 6 VPOS Positive Supply (2.7 V to 8.0 V). 7 N/C Optional Shielding of IOUT Trace. No connection to die. 8 IOUT Output Current. Mirrors current at INPT with a gain of 1.0. Sources current only. PADDLE Internally connected to COMM, solder to ground.
Rev. 0 | Page 10 of 20 The VSET control is intended primarily to provide a dc bias voltage for the mirror input, but it is also well behaved in the presence of the VSET transients. The rise time of VINPT is largely independent of input current because the mirror is capable of sourcing large currents to pull up the INPT pin. The fall time, however, is inversely proportional to I INPT because only IINPT is available to discharge the input compensation capacitor and other parasitics (see Figure 11). The mirror output current can vary significantly from zero to several milliamps until VINPT is fully settled. NOISE PERFORMANCE The noise performance for the ADL5315, defined as the rms noise current as a fraction of the output dc current, generally improves with increasing signal current. This partially results from the relationship between the quiescent collector current and the shot noise in the bipolar transistors. At lower signal current levels, the noise contribution from the JFET amplifier and other voltage noise sources appearing at INPT contribute significantly to the current noise. Filtering noise at VSET, whether provided by SREF or generated externally, as well as selecting optimal external compensation components on INPT, minimizes the amount of current noise at IOUT generated by the voltage noise at INPT. MIRROR RESPONSE TIME The response time of IOUT to changes in IINPT is fundamentally a function of input current, with small-signal bandwidth increasing roughly in proportion to IINPT (see Figure 10). The value of the external compensating capacitor on INPT strongly affects the IOUT response time (as well as the VSET to VINPT fall time, as noted in the Bias Control Interface section), although the value must be chosen to maintain stability and prevent noise peaking. INPUT CURRENT LIMITING The ADL5315 provides a resistor-programmable input current limit with a fixed maximum of 16 mA for the RLIM pin tied to VPOS. The fixed maximum provides input short-circuit protection to ground. The current limit is defined as the current that forces V INPT to 0 V (when using a current source on the INPT pin). Resistor RLIM between the VPOS and RLIM pins controls the current limit according to kΩ3 V 48 LIM LIM RI over an RLIM range of 0 to 45 kΩ, corresponding to 16 mA down to 1 mA. Larger values of RLIM can be used for currents below 1 mA (down to approximately 250 μA) with some degradation in accuracy. See Figure 14 for more performance detail.
0.80 MAX
0.65 TYP
0.50 BSC
0.05 MAX
0.02 NOM
Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
2 WP = Waffle pack
Rev. 0 | Page 18 of 20 NOTES
Rev. 0 | Page 19 of 20 NOTES
Rev. 0 | Page 20 of 20 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D05694–0–10/05(0)