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120 dB Range (3 nA to 3 mA) Dual Logarithmic Converter ADL5310 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
2 independent channels optimized for photodiode interfacing 6-decade input dynamic range Law conformance 0.3 dB from 3 nA to 3 mA Temperature-stable logarithmic outputs Nominal slope 10 mV/dB (200 mV/dec), externally scalable Intercepts may be independently set by external resistors User-configurable output buffer amplifiers Single- or dual-supply operation Space-efficient, 24-lead 4 mm × 4 mm LFCSP Low power: < 10 mA quiescent current
APPLICATIONS
Gain and absorbance measurements Multichannel power monitoring General-purpose baseband log compression PRODUCT DESCRIPTION The ADL53101 low cost, dual logarithmic amplifier converts input current over a wide dynamic range to a linear-in-dB output voltage. It is optimized to determine the optical power in wide-ranging optical communication system applications, including control circuitry for lasers, optical switches, atten- uators, and amplifiers, as well as system monitoring. The device is equivalent to a dual AD8305 with enhanced dynamic range (120 dB). While the ADL5310 contains two independent signal channels with individually configurable transfer function constants (slope and intercept), internal bias circuitry is shared between channels for improved power consumption and channel matching. Dual converters in a single, compact LFCSP package yield space-efficient solutions for measuring gain or attenuation across optical elements. Only a single supply is required; optional dual-supply operation offers added flexibility. The ADL5310 employs an optimized translinear structure that use the accurate logarithmic relationship between a bipolar transistor’s base emitter voltage and collector current, with appropriate scaling by precision currents to compensate for the inherent temperature dependence. Input and reference current pins sink current ranging from 3 nA to 3 mA (limited to ±60 dB between input and reference) into a fixed voltage defined by the VSUM potential. The VSUM potential is internally set to 500 mV but may be externally grounded for dual-supply opera- tion, and for additional applications requiring voltage inputs. FUNCTIONAL BLOCK DIAGRAM TEMPERATURE COMPENSATION REFERENCE GENERATOR 451 14.2k 80k20k 6.69k 4.99k COMM COMM VREF VREF VRDZ VNEG VSUM INP2 IRF2 2.5V0.5V ILOG OUT2 SCL2 BIN2 LOG2 04415-0-001 VBIAS TEMPERATURE COMPENSATION 451 14.2k 6.69k 4.99k COMM VNEG VSUM INP1 IRF1 ILOG OUT1 VOUT1 VOUT2 SCL1 BIN1 LOG1 VBIAS IPD1 IPD2 665k 665k Figure 1. The logarithmic slope is set to 10 mV/dB (200 mV/decade) nominal and can be modified using external resistors and the independent buffer amplifiers. The logarithmic intercepts for each channel are defined by the individual reference currents, which are set to 3 μA nominal for maximum input range by connecting 665 kΩ resistors between the 2.5 V VREF pins and the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets the x-intercept four decades below the reference current— typically 300 pA for a 3 μA reference. The use of individually optimized reference currents may be valuable when using the ADL5310 for gain or absorbance measurements where each channel input has a different current- range requirement. The reference current inputs are also fully functional dynamic inputs, allowing log ratio operation with the reference input current as the denominator. The ADL5310 is specified for operation from –40°C to +85°C. 1 US Patents: 5,519,308.
Rev. A | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A 11/03—Revision 0: Initial Version
Rev. A | Page 3 of 20 SPECIFICATIONS VP = 5 V , VN = 0 V , TA = 25°C, RREF = 665 kΩ, and VRDZ connected to VREF, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pins 1 to 6: INP1 and INP2, IRF1 and IRF2, VSUM Specified Current Range, IPD Flows toward INP1 pin or INP2 pin 3 n 3 m A Input Current Min/Max Limits Flows toward INP1 pin or INP2 pin 10 m A Reference Current, IREF, Range Flows toward IRF1 pin or IRF2 pin 3 n 3 m A Summing Node Voltage Internally preset; user alterable 0.46 0.5 0.54 V Temperature Drift –40°C < TA < +85°C 0.030 mV/°C Input Offset Voltage VIN − VSUM, VIREF − VSUM −20 +20 mV LOGARITHMIC OUTPUTS Pin 15 and Pin 16: LOG1 and LOG2 Logarithmic Slope 190 200 210 mV/dec –40°C < TA < +85°C 185 215 mV/dec Logarithmic Intercept1 165 300 535 pA –40°C < TA < +85°C 40 1940 pA Law Conformance Error 10 nA < IPD < 1 mA 0.1 0.4 dB 3 nA < IPD < 3 mA 0.3 0.6 dB Wideband Noise2 IPD > 3 µA; output referred 0.5 µV/√Hz Small Signal Bandwidth2 IPD = 3 µA 1.5 MHz Maximum Output Voltage 1.7 V Minimum Output Voltage Limited by VN = 0 V 0.10 V Output Resistance 4.375 5 5.625 kΩ REFERENCE OUTPUT Pin 7 and Pin 24 (internally shorted): VREF Voltage wrt Ground 2.45 2.5 2.55 V Maximum Output Current Sourcing (grounded load) 20 mA Incremental Output Resistance Load current < 10 mA 4 Ω OUTPUT BUFFERS Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1, and OUT1 Input Offset Voltage −20 +20 mV Input Bias Current Flowing out of Pins 13, 14, 17, and 18 0.4 µA Incremental Input Resistance 35 MΩ Incremental Output Resistance Load current < 10 mA; gain = 1 0.5 Ω Output High Voltage RL = 1 kΩ to ground VP − 0.1 V Output Low Voltage RL = 1 kΩ to ground 0.10 V Peak Source/Sink Current 30 mA Small-Signal Bandwidth Gain = 1 15 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/µs POWER SUPPLY Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG Positive Supply Voltage (VP – VN ) ≤ 12 V 3 5 12 V Quiescent Current Input currents < 10 µA 9.5 11.5 mA Negative Supply Voltage (Optional) (VP – VN ) ≤ 12 V −5.5 0 V 1 Other values of logarithmic intercept can be achieved by adjustment of RREF. 2 Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.
Rev. A | Page 4 of 20 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage VP − VN 12 V Input Current 20 mA Internal Power Dissipation 500 mW θJA 35°C/W1 Maximum Junction Temperature 125°C Operating Temperature Range –40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering 60 sec) 300°C 1 With paddle soldered down. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Figure 2. 24-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions summing node potentials. Pin 1 and Pin 6 are internally shorted. such that photocurrent flows into INP1. 3 IRF1 Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1. 4 IRF2 Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2. such that photocurrent flows into INP2. 7, 24 VREF Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted. 8, 9 VPOS Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally. Applications sections. All VNEG pins must be connected externally. 12 OUT2 Buffer Output for Channel 2. 13 SCL2 Buffer Amplifier Inverting Input for Channel 2. 14 BIN2 Buffer Amplifier Noninverting Input for Channel 2. 15 LOG2 Output of the Logarithmic Front End for Channel 2. 16 LOG1 Output of the Logarithmic Front End for Channel 1. 17 BIN1 Buffer Amplifier Noninverting Input for Channel 1. 18 SCL1 Buffer Amplifier Inverting Input for Channel 1. 19 OUT1 Buffer Output for Channel 1. 21, 22 COMM Analog Ground. Pin 21 and Pin 22 are internally shorted.
Figure 33. Simplified Schematic of Single Log Amp to a corresponding logarithmic voltage, as shown in Equation 1. degradation in law conformance. IC is the collector current. IS is a scaling current, typically only 10–17 A. temperature (PTAT), and is 25.85 mV at 300 K. dependencies must be eliminated. voltage is processed by what is essentially an analog divider. voltage-mode output, VLOG, scaled 200 mV/decade. where IINTC is the operational value of the intercept current.
Rev. A | Page 12 of 20 The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 kΩ, formed by the parallel combination of a 6.69 kΩ resistor to ground and a 14.2 kΩ resistor to Pin VRDZ (typically tied to the 2.5 V reference, VREF). At the LOG1 (LOG2) pin, the output current I LOG generates a voltage of VLOG = ILOG × 4.55 kΩ = 44 µA × 4.55 kΩ × log10(IPD/IINTC) (5) = VY log10(IPD/IINTC) where VY = 200 mV/decade or 10 mV/dB. Note that any resis- tive loading on LOG1 (LOG2) lowers this slope and results in an overall scaling uncertainty. This is due to the variability of the on-chip resistors compared to the off-chip load. As a con- sequence, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = −0.5 V or larger, the input Pins INP1 (INP2) and IRF1 (INP2) may be positioned at ground level simply by grounding VSUM. Care must be taken to limit the power consumed by the input BJT devices when using a larger negative supply, because self-heating degrades the accuracy at higher currents. MANAGING INTERCEPT AND SLOPE When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire 6-decade input current range. As noted in the Theory section, this introduces an accurate offset voltage of 0.8 V at the LOG1 and LOG2 pins, equivalent to four decades, resulting in a logarithmic transfer function that can be written as VLOG = VY log10(104 × IPD/IREF) = VY log10(IPD/IINTC) (6) where IINTC = IREF/104. Thus, the effective intercept current IINTC is only one ten- thousandth of IREF, corresponding to 300 pA when using the recommended value of IREF = 3 µA. The slope can be reduced by attaching a resistor between the log amp output pin, LOG1 or LOG2, and ground. This is strongly discouraged given that the on-chip resistors do not ratio correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer amps, which are provided to avoid such miscalibration and to allow higher slopes to be used. Each of the ADL5310’s buffers is essentially an uncommitted operational amplifier with rail-to-rail output swing, good load- driving capabilities, and a typical unity-gain bandwidth of 15 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage V Y, the buffer can be used to implement multipole, low- pass filters, threshold detectors, and a variety of other functions. Further details on these applications can be found in the AD8304 data sheet. RESPONSE TIME AND NOISE CONSIDERATIONS The response time and output noise of the ADL5310 are funda- mentally a function of the signal current, I PD. For small currents, the bandwidth is proportional to IPD, as shown in Figure 15. The output low frequency voltage-noise spectral-density is a function of IPD (see Figure 17) and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 data sheet.
An evaluation board is available for the ADL5310 (Figure 40 shows the schematic). It can be configured for a wide variety of experiments. the various configuration options. Table 4. Evaluation Board Configuration Options output offset voltage at the LOG1 and LOG2 outputs. Pins INP1, INP2, IRF1, and IRF2. ADL5310 in log ratio applications.
Figure 40. Evaluation Board Schematic
0.60 MAX
2.50 REF
0.80 MAX
0.05 MAX
0.02 NOM
0.080.20 REF
0.25 MIN
Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]
1 Branding is as follows:
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