ADL5308 (Rev.A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 25
Technical content
Fast Response 188 dB Range (10 pA to 25 mA) Logarithmic Converter Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Fast transient response (IPD stepped from 220 µA to 10 nA) ►Rise/fall time: <2.4 µs ►2 dB Electrical (1 dB optical) settling time: <3.5 µs ►Flat Frequency Response/No Undershoot ►Bandwidth: 970 kHz at IINP = 10 nA ►Accurately trimmed logarithmic response ►Logarithmic slope: 200 mV/dec ►Logarithmic conformance error: ±0.2 dB at 25°C (IINP from 10 nA to 1 mA) ►Ratio input for direct optical gain measurements ►Comparator with adjustable hysteresis and latch enable ►Analog and digital comparator reference ►I2C adjustable ►Adaptive photodiode bias ►Comparator reference level ►Minimal external components are required ►34 dB PSRR at 20 kHz and IINP = 10 nA ►2 mm × 3 mm, 14-terminal LGA package
APPLICATIONS
►Optical power monitoring ►Erbium-doped fiber amplifiers (EDFA) GENERAL DESCRIPTION The ADL5308 is a logarithmic transimpedance amplifier optimized for wide dynamic range signal level monitoring in fiber optic sys- tems. It produces an accurate, temperature-compensated output voltage proportional to the logarithm of the ratio between the input current at pin INP, and a reference current. The reference current can either be generated internally or externally provided through the IREF interface (LOG-ratio detection). The logarithmic slope and intercept are both accurately trimmed to a nominal value of 200 mV/decade and 10 pA respectively. The low-impedance VLOG logarithmic output has enough drive capability to drive a wide range of analog-to-digital converters (ADCs) and other circuits and its gain can be adjusted by adding a resistor-divider driving the FB pin. A built-in fast comparator provides a compact solution to compare the logarithmic output to an external reference level, either pro- grammed through I2C or supplied through the CREF interface. The comparator has adjustable hysteresis and an optional output latch function using the HYST pin. Adaptive photodiode (PD) biasing is supported through the PDB pin. At a low diode current, the reverse PD bias is kept small to minimize the dark current. At higher input currents, the bias voltage scales linearly with the current to avoid nonlinearity due to PD saturation. The starting bias level as well as the scale factor at higher currents are configurable through I2C. The ADL5308 is specified for operation from −40°C to +105°C ambient temperature and is offered in a small 2 mm × 3 mm, 14-terminal LGA package. FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram
analog.com Rev. A | 2 of 25
REVISION HISTORY
4/2024—Rev. 0 to Rev. A 8/2023—Revision 0: Initial Version
VCC = 5.0 V, TA = 25°C, Input current (IINP) = 10 nA, default register settings, unless otherwise noted. Table 1. Electrical Specifications
Table 1. Electrical Specifications (Continued) Figure 2. I2C Timing Diagram Table 2. I2C Timing Specifications
Table 3. Absolute Maximum Ratings ing conditions for extended periods may affect product reliability. environment. Careful attention to PCB thermal design is required. Table 4. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based upon use of
2S2P JEDEC PCB. For more information, see the Ordering Guide section. in a one cubic foot sealed enclosure. 3 θJB is the junction-to-board thermal resistance. 4 θJC is the junction-to-case bottom thermal resistance. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1, 4 SUM Guard Pins. The SUM pins are used to shield the input current lines to INP and IREF. 2 INP Photocurrent Input. INP is connected to the PD anode (current flows into INP). measurements (optical gain). 5 SDA I2C Interface Data Input/Output. 6 SCL I2C Interface Clock Input. 7 CREF Comparator Reference Level. Comparator output is high when the VLOG voltage exceeds the voltage applied to this pin. register content is not zero. 8 CMP Comparator Output Voltage. 10 VLOG Logarithmic Output. The voltage at this pin changes logarithmically with the current applied to INP and IREF. 11 FB Feedback Pin of Output Amplifier. Can be used to change the logarithmic slope with two external resistors. applied to this pin enables the latch function. 13 VCC Positive Power Supply. Decoupling with 1 nF and 4.7 μF capacitors to ground is recommended at this pin. low input currents, avoid resistive loading at this pin. the input pins. Connect all SUM pins together and leave floating. thermal and electrical connection to the ground of the PCB. Connect all ground pins to a low impedance ground plane.
Figure 34. VVLOG at IINP = 1 nA Distribution Figure 35. VVLOG at IINP = 10 mA Distribution
analog.com Rev. A | 13 of 25 LOGARITHMIC TRANSFER The logarithmic transimpedance amplifiers (TIA) produce an output voltage that is (approximately) linearly related to the logarithm of the input current IPD: V LO G = S LO PE × log 10 I PD I Z (1) The logarithmic slope (SLOPE) shows the amount by which the out- put voltage VLOG changes for each factor of 10 (decade) change in input current IPD, while the logarithmic intercept IZ shows the (extrapolated) input current for which the output voltage becomes zero. The actual device output voltage never reaches zero, but saturates to the starting voltage of 12 mV for input currents below 10 pA. Both SLOPE and IZ can be obtained by linear regression of the measured amplifier output voltage vs. a range of input current levels. The ADL5308 logarithmic slope and intercept of the VLOG − 1.1 V curve are accurately factory trimmed to 200 mV/dec and 3.16 µA respectively. The reason 1.1 V is subtracted from VLOG curve (the ideal value of VLOG at 3.16 µA) is to place the x-intercept in the geometric middle of the specified input current range. That way, the residual slope differences have a minimum impact on the x-intercept and its equation can be written as: VL OG − 1 . 1 = SL OPE × log 10 I PD I Z 1 P 1 (2) Expressed in dB of input current, Equation 2 can be written as: VL OG − 1 . 1 = S LO PE 20 × I PD , d B − I Z 1 P 1 , d B (3) Where IPD, dB is the input current in dBA and IZ1P1,dB is the intercept current in dBA (−110 dBA in this case). The measurement accuracy obtained with a logarithmic amplifier is determined by the following two factors: ►The logarithmic conformance error ►The temperature drift error The logarithmic conformance error describes the deviation of the actual TIA transfer from the ideal log-linear relationship of Equation 3, and is expressed in dB of input current: E L C = 20 × V LO G T SL OPE + I Z 1 P 1 , d B − I P D , d B (4) Thus ELC shows the resulting measurement error when VLOG of a logarithmic TIA is measured and Equation 3 is used to determine the input current that the device is sensing. Since SLOPE and IZ are usually determined at room temperature only, ELC typically also contains a contribution due to drift of the TIA transfer over temperature. The temperature drift error Edrift describes the measurement error introduced solely due to the temperature drift of the TIA transfer, excluding discrepancies of the actual TIA transfer to the ideal log-linear relationship (logarithmic conformance). E dr i f t T = 20 SL OP E × V LO G T − V LO G T o (5) The error, the difference between the output voltage measured at the operating temperature T and the actual output voltage measured at the reference temperature To, usually 25°C, is input referred and expressed in dB (of input current) using the logarithmic SLOPE. This is accurate as long as the error is relatively small and the TIA transfer is approximately logarithmic (linear in dB). OPTICAL MEASUREMENTS A high-dynamic range optical power monitor can be constructed by connecting the anode of a reverse biased PD to the input of the logarithmic TIA, such that the TIA senses the photon-generated di- ode current. Therefore, it is important to understand the transducer aspects of a PD, that is, how to interpret the PD current relative to the incident optical power. In the electrical circuits, the power dissipated in a resistive load is proportional to the square of the current, or, vice versa, the current through the load is proportional to the square root of the dissipated power: I R = P D I SS / R (6) In a reverse biased PD, however, the photon-generated PD current (IPD) itself is directly proportional to the optical power (POPT) absor- bed in the detector: I PD = ρ × P O PT (7) The proportionality constant ρ shows the conversion gain from optical power to electrical current, is called the responsivity of the PD. Using the same responsivity, the logarithmic intercept current IZ of the TIA can be related to an optical intercept power level PZ for which the ideal log-linear transfer produces an output voltage equal to zero. The transfer from measured optical power to amplifier output voltage can therefore be expressed as: VL OG = SL OPE × log 10 P O PT P z (8) For incident optical power expressed in dB, that is, P dB , O PT = 10 × log 10 P OPT (9) This becomes: V L OG = S L OPE 10 × P d B , OPT − P dB , Z (10) Thus the logarithmic slope in mV/dB optical power equals twice the logarithmic slope in mV/dB of input current IPD (see Equation 3). Similarly, the optical dynamic range of the TIA in dB equals half the electrical dynamic range in dB, that is, 70 dB optical vs. 140 dB electrical.
resistance on the measurement accuracy. therefore limits the sensitivity of an optical power measurement. sensitivity of the optical power measurement. is needed to minimize the impact of the PD series resistance. specified low-level VOS to minimize the impact of the dark current. the cathode of the PD should be connected to the PDB pin. Figure 36. Adaptive PDB Principle of Operation PDBG bit field adjusts the transresistance value in 11.72 Ω steps. PDBG = 0 disables the transresistance. goes infinite for PDBG_FIX = 1. and is therefore not necessarily 0 mV for OS = 8.
analog.com Rev. A | 15 of 25 BANDWIDTH The bandwidth of logarithmic TIAs changes with the input current IPD, which results in low bandwidth at low input currents, and gradually increases to high bandwidth at high current levels. In general, bandwidth and gain have an inverse relationship to each other, such that increasing the gain of an amplifier typically reduces its bandwidth and vice versa. Logarithmic TIAs are no exception to this rule. Using Equation 1, the small-signal gain (transimpedance) of a TIA, that is, the change in output voltage due to a (small) change in input current IINP can be expressed as: Z t = d V L OG d I PD = SL OPE ln 10 I I NP (14) Due to the inherent dynamic range compression by the logarithm, the TIA gain at low input levels is very high, and thus low bandwidth is to be expected. Similarly, the transimpedance at high input currents is much lower, expected to result in higher bandwidth. Further insight into this relationship between bandwidth and input current can be obtained from Figure 1, which shows a simplified schematic of a logarithmic TIA. The overall topology is usually a negative feedback amplifier using a diode or the base-emitter junction of a bipolar transistor to estab- lish the logarithmic transfer from input current to output voltage. Without feedback, that is, if the gain of the operational amplifier (Op Amp) is zero, the impedance (to ground) at the input node is high, most current from the source should flow into the diode, such that a small parasitic capacitance of the PD and circuit board has a major impact on the (open-loop) bandwidth of the circuit. The loop gain in the amplifier reduces the impedance at the input node by a factor approximately equal to the loop gain, which is roughly the product of op amp gain, input impedance, and the feedback diode transconductance. If the loop gain is infinite, the closed-loop input impedance of the TIA becomes zero, that is, a virtual ground, and the current through the feedback diode precisely equal to the source current IS. In a practical amplifier, where the op amp has high but finite gain, an increase of the transimpedance gain Zt corresponds to a decrease of the diode transconductance (which ideally equals the inverse of Zt) and thus a decrease of the amplifier loop gain. In turn, a decrease of the loop gain increases the closed-loop input impedance of the amplifier and given that the input capacitance is roughly fixed, decreases the amplifier bandwidth. To maintain as wide as possible bandwidth, it is thus critical to minimize capacitive loading of the TIA input pins. NOISE The noise level produced by a logarithmic TIA is also dependent on the input current IINP. The output voltage noise is highest at low input currents (corresponding to the highest small-signal gain), and lowest at high input current levels. Figure 26 shows the spot noise spectral density vs. IINP graph. For low input currents, one of the most dominant noise sources is the 1/f noise of the input NMOS, shown in Figure 37, which produces a 1/f noise voltage at the input node. With a capacitive load at the input, this noise voltage causes an input 1/f noise current and can produce a hill-shaped spot noise spectral density curve. Therefore, it is important to minimize the source capacitance by choosing a PD with as low as possible equivalent parallel capacitance and as short as possible trace to the input node. A trade-off between noise density and bandwidth at low IINP can be made by setting register CF as shown in Figure 23 and Figure 28 with maximum bandwidth and highest noise density for CF = 0 (trim default) and minimum bandwidth and lowest noise density for CF = 15.
- Before changing any register values, read and copy the internal
registers (0x70 to 0x7C) to preserve factory-trimmed settings.
- Write the copied values from Step 1 to the corresponding
control registers (0x10 to 0x1C).
- Set NVM_BYPASS (0x48) = 1 to flip the MUX switch from NVM
- Change the control registers to the desired register values/set-
not require aforementioned procedure. Figure 47. Simplified Diagram of the Control Registers
Table 6. ADL5308 I2C Register Details1 [3:0] IREF Reference current adjust. [3:0] IPDB Controls the PDB voltage at in 30 mV steps. [3:0] CF Low input current bandwidth (CF = capacitor feedback). [2:0] ZT Band-gap ZTAT control. [3:0] INT_REG_73 Internal register for IREF. [5:0] INT_REG_74 Internal register for PDBG. [3:0] INT_REG_75 Internal register for IPDB. [3:0] INT_REG_79 Internal register for CF.
Table 6. ADL5308 I2C Register Details1 (Continued) [2:0] INT_REG_7A Internal register for ZT. 1 Note that all other registers and undocumented bits are reserved.
Figure 48. Evaluation Board Schematic
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 51. 14-Terminal Land Grid Array [LGA] 2 The ADL5308-EVALZ package includes the board only. 3 A DC2026C Linduino One controller board is included with the ADL5308-KIT-EVALZ.