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160 dB Range 100 pA to 10 mA Low Cost Logarithmic Converter Data Sheet ADL5303 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Optimized for fiber optic photodiode interfacing 8 full decades of range Law conformance: 0.1 dB from 1 nA to 1 mA Single-supply operation: 3.0 V to 5.5 V Complete and temperature stable Accurate laser trimmed scaling Logarithmic slope of 10 mV/dB (at the VLOG pin) Basic logarithmic intercept at 100 pA Easy adjustment of slope and intercept Output bandwidth of 10 MHz, 15 V/μs slew rate Miniature 16-lead package (LFCSP) Low power: ~4.5 mA quiescent current (enabled)
APPLICATIONS
High accuracy optical power measurement Wide range baseband log compression Versatile detector for APC loops SIMPLIFIED BLOCK DIAGRAM PDB BIAS VREF IPD VPDB VSUM INPT VSUM GND GND VPS2 PWDN VPS1 VREF VLOG BFIN BFNG VOUT 0.5V ADL5303 ~10kΩ 5kΩ 15 14 ACOM 7 11 10 16 12 10661-001 TEMPERATURE COMPENSATION Figure 1. GENERAL DESCRIPTION The ADL5303 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems and offers a large dynamic range in a versatile and easily used form. Wide measurement range and accuracy are achieved using proprietary design and precise laser trimming. The ADL5303 requires only a single positive supply, V PS, of 5 V . When using low supply voltages, the log slope can be altered to fit the available span. Low quiescent current and chip disable facilitate use in battery-operated applications. The input current, I PD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range. An adaptive biasing scheme is provided for reducing photo- diode dark current at very low light input levels. The VPDB pin applies approximately 0.1 V reverse bias across the photodiode for I PD = 100 pA, rising linearly to 2.0 V of reverse bias at IPD = 10 mA to improve response time at higher power levels. The input pin INPT is flanked by the VSUM guard pins that track the voltage at the summing node. Connecting the exposed pad of the device to the VSUM pins provides a continuous guard to minimize leakage into the INPT pin. The default value of the logarithmic slope at the VLOG output is set by an internal 5 kΩ resistor. Logarithmic slope can be lowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. The addition of a capacitor at the VLOG pin provides a simple low-pass filter. The intermediate voltage, V LOG, is buffered in an output stage that can swing to within about 100 mV of ground and the posi- tive supply, V PS, and provides a peak current drive capacity of ±20 mA. An on-board 2 V reference is provided to facilitate the repositioning of the intercept. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At I PD =1 nA, the bandwidth of the ADL5303 is approximately 2 kHz increasing in proportion to IPD up to a maximum value of 10 MHz.
Rev. 0 | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
1/13—Revision 0: Initial Version
Rev. 0 | Page 3 of 24 SPECIFICATIONS VPS = 5 V, GND, ACOM = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min1 Typ Max1 Unit INPUT INTERFACE Pin 3, INPT; Pin 2 and Pin 4, VSUM Specified Current Range Flows toward Pin 3 100 pA 10 mA Input Node Voltage Internally preset; may be altered 0.46 0.5 0.54 V Temperature Drift −40°C < TA < +85°C 0.04 mV/°C Input Guard Offset Voltage VOFS = VIN – VSUM −20 +20 mV PHOTODIODE BIAS2 Established between VPDB and INPT Minimum Value IPD = 100 pA 70 100 mV Transresistance 200 mV/mA LOGARITHMIC OUTPUT Pin 8, VLOG Slope Laser trimmed at 25°C 195 200 205 mV/dec 0°C < TA < 70°C 193 207 mV/dec Intercept Laser trimmed at 25°C 60 100 140 pA 0°C < TA < 70°C 35 175 pA Law Conformance Error 10 nA < IPD < 1 mA, peak error 0.05 0.25 dB 1 nA < IPD < 1 mA, peak error 0.1 0.7 dB Maximum Output Voltage 1.6 V Minimum Output Voltage 0.1 V Output Resistance Laser trimmed at 25°C 4.95 5 5.05 kΩ REFERENCE OUTPUT Pin 6, VREF Voltage WRT Ground Laser trimmed at 25°C 1.98 2 2.02 V Output Resistance 2 Ω OUTPUT BUFFER Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT Input Offset Voltage −20 +20 mV Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 μA Incremental Input Resistance 35 MΩ Output Range RL = 1 kΩ to ground VPS − 0.1 V Output Resistance 0.5 Ω Wideband Noise3 IPD > 1 μA (see the Typical Performance Characteristics section) 1 μV/√Hz Small Signal Bandwidth3 IPD > 1 μA (see the Typical Performance Characteristics section) 10 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/μs POWER-DOWN INPUT Pin 16, PWDN Logic Level, High State −40°C < TA < +85°C, 2.7 V < VPS < 5.5 V 2 V Logic Level, Low State −40°C < TA < +85°C, 2.7 V < VPS < 5.5 V 1 V POWER SUPPLY Pin 10 and Pin 12, VPS2 and VPS1; Pin 14 and 15, GND Supply Voltage 3.0 5 5.5 V Quiescent Current 4.5 5.6 mA In Disabled State 60 μA 1 Minimum and maximum specified limits on parameters are guaranteed but not tested and are six sigma values. 2 This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground. 3 Output noise and incremental bandwidth are functions of input current; see the Typical Performance Characteristics section.
Rev. 0 | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VPS 6 V Input Current to INPT 20 mA Thermal Data, 2-Layer JEDEC Board, No Air Flow (Exposed Pad Soldered to PCB) θJA 61.6°C/W θJC 1.2°C/W Maximum Power Dissipation (Exposed Pad Soldered to PCB) 0.6 W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
- PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT
IT IS BETTER TO CONNECT THESE PINS TO GROUND. THESE PINS BECAUSE NOISE COUPLING MAY RESULT.
- EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE
VSUM PINS TO PROVIDE LOW LEAKAGE GUARD.
11 VOUT
12 VPS1
10 VPS2
9 BFIN
Figure 2. Pin Configuration Table 3. Pin Function Descriptions speed signals through these pins because noise coupling may result. 2, 4 VSUM Guard Pins. VSUM is used to shield the INPT current line. 3 INPT Photodiode Current Input. Connect this pin to the photodiode anode (the photo current flows toward INPT). otherwise, leave this pin floating. 6 VREF Voltage Reference Output of 2 V. 7 ACOM Analog Reference Ground. 8 VLOG Output of the Logarithmic Front-End Processor. ROUT = 5 kΩ to ground. 9 BFIN Buffer Amplifier Noninverting Input (High Impedance). 10 VPS2 Positive Supply, VPS (3.0 V to 5.5 V). 11 VOUT Buffer Output; Low Impedance. 12 VPS1 Positive Supply, VPS (3.0 V to 5.5 V). 13 BFNG Buffer Amplifier Inverting Input. 14, 15 GND Power Supply Ground Connection. 16 PWDN Power-Down Control Input. Device is active when PWDN is taken low. 17 EPAD Exposed Pad. Connect the exposed pad to the VSUM pins to provide low leakage guard.
Rev. 0 | Page 10 of 24 THEORY OF OPERATION BASIC CONCEPTS The ADL5303 uses an advanced circuit implementation that exploits the logarithmic relationship between the base-to- emitter voltage, VBE, and collector current, IC, in a bipolar transistor. Using these principles, the relationship between the input current, IPD, applied to the INPT pin, and the voltage appearing at the intermediate output VLOG pin is: VLOG = VY log10(IPD/IZ) (1) where: VY is the voltage slope (in the case of base-10 logarithms, it is also referred to as volts per decade). IZ is the fixed current in the logarithmic equation called the intercept. In the following example, the scaling is chosen so that VY is trimmed to 200 mV/decade (10 mV/dB). The intercept is positioned at 100 pA; the output voltage, VLOG, crosses zero when IPD is of this value. However, the actual VLOG must always be slightly above ground. Using Equation 2, calculate the output for any value of IPD. Thus, for an input current of 25 nA, VLOG = 0.2 V log10(25 nA/100 pA) = 0.4796 V (2) In practice, both the slope and intercept can be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two external resistors, often in conjunction with the trimmed 2 V voltage reference at the VREF pin. OPTICAL MEASUREMENTS When interpreting the IPD current in terms of optical power incident on a photodetector, it is necessary to be clear about the conversion (optical power to current) properties of a reverse biased photodiode. The units of this conversion are expressed in amps per watt and referred to as photodiode responsivity, ρ. For the typical InGaAs PIN photodiode, the responsivity is approximately 0.9 A/W . It is important to note that in purely electrical circuits, current and power are not related in this proportional manner. A current applied to a resistive load results in a power propor- tional to the square of the current, P = I2R. The difference in scaling for a photodiode is because IPD flow in a reverse-biased diode is largely dependent on the fixed built-in voltage of the PN junction and is relatively insensitive to the external bias voltage. In the detector diode, power dissipated is proportional to the IPD current and the relationship of IPD to the optical power, POPT, is preserved. IPD = ρPOPT (3) The same relationship exists between the intercept current, IZ, and an equivalent intercept power, PZ, thus, IPZ = ρPZ (4) Therefore, Equation 1 can be written as VLOG = VY log10(POPT/PZ) (5) For the ADL5303 operating in its default configuration, an IZ of 100 pA corresponds to a PZ of 110 pW, for a diode having a responsivity of 0.9 A/W . Thus, an optical power of 3 mW generates VLOG = 0.2 V log10(3 mW/110 pW) = 1487 V (6) Note that when using the ADL5303 in optical applications the VLOG output is referred to in terms of the equivalent optical power, the logarithmic slope remains 10 mV/dB at this output. This can be confusing because a decibel change on the optical side has a different meaning than on the electrical side. In either case, the logarithmic slope can always be expressed in units of millivolts per decade to help eliminate confusion. DECIBEL SCALING When power levels are expressed as decibels above a reference level (in dBm, for a reference of 1 mW), the logarithmic conver- sion has already been performed, and the log ratio in the previous expressions becomes a simple difference. Be careful in assigning variable names here, because P is often used to denote actual power as well as this same power expressed in decibels; how- ever, these are numerically different quantities. BANDWIDTH AND NOISE CONSIDERATIONS Response time and wideband noise of translinear log amps are a function of the signal current, IPD. Bandwidth becomes progressively lower as IPD is reduced, largely due to the effects of junction capacitances in the translinear device. Figure 9 shows ac response curves for the ADL5303 at eight representative currents of 1 nA to 10 mA, using R1 = 750 Ω and C1 = 1000 pF . The values for R1 and C1 ensure stability over the full 160 dB dynamic range. More optimal values may be used for smaller subranges. A certain amount of experi- mental trial and error may be necessary to select the optimum input network component values for a given application. The relationship between I PD and the voltage noise spectral density, SNSD, associated with the VBE of Q1, calculates to the following: PD NSD IS 7.14= (7) where: SNSD is nV/Hz. IPD is expressed in microamps. TA = 25°C.
Rev. 0 | Page 11 of 24 For an input of 1 nA, SNSD evaluates to almost 0.5 μV/√Hz; assuming a 20 kHz bandwidth at this current, the integrated noise voltage is 70 μV rms. However, this calculation is not complete. The basic scaling of the VBE is approximately 3 mV/dB; translated to 10 mV/dB, the noise predicted by Equation 7 must be multiplied by approximately 3.33. The additive noise effects associated with the reference transistor, Q2, and the temperature compensation circuitry must also be included. The final voltage noise spectral density presented at the VLOG pin varies inversely with IPD, but is not a simple square root relationship. Figure 10 shows the measured noise spectral density vs. frequency at the VLOG output, for the same nine-decade spaced values of IPD. CHIP ENABLE Power down the ADL5303 by taking the PWDN pin to a high logic level. The residual supply current in the disabled mode is typically 60 μA.
slope of 10 mV/dB at the VLOG pin to 25 mV/dB at VOUT. output stage when using the recommended 5 V supply. is trimmed to 5 kΩ, an accurate time constant can be realized. ground is essential for minimizing the noise on this node. these pins should be left unconnected. The choice of slope and intercept depends on the application. values for RS and the resulting slopes. Table 4. Examples of Lowering the Slope be inserted between VLOG and the inverting input BFNG pin. Figure 25. Basic Connections (R15, R18, C7 are Optional; R1 and C1 are the Default Values)
a maximum swing of 4.8 V , it amounts to 4.8 V/VY decades. and lower headroom in the output swing. resistor, RZ, from VLOG to VREF (2 V) as shown in Figure 26. combined with several slope variations. Table 5. Examples of Lowering the Intercept where G = 1 + RA/RB and RLOG = 5 kΩ. Figure 26. Method for Lowering the Intercept
resistor values for representative intercepts. Table 6. Examples of Raising the Intercept Figure 27. Method for Raising the Intercept
feeding the internal laser trimmed output resistance of 5 kΩ. ground in combination with an intercept lowering resistor, RZ. using voltage gain on the internal buffer amplifier. CE are not advised when large values of IPD are expected. Figure 28. Recommended Low Supply Application Circuit
aided by a small offset nulling voltage applied to VSUM. limited only by the drift in the input offset of the ADL5303. zand a full-scale output of ±3.6 V . with a slope of −0.6 V per decade, spanning the full range of IPD. Figure 30. Using the Buffer to Invert the Polarity of the Slope
Rev. 0 | Page 18 of 24 EVALUATION BOARD An evaluation board is available for the ADL5303, the sche- matic for which is shown in Figure 31, and the board layout is shown in Figure 32 and Figure 33. It can be configured for a wide variety of experiments. The board is factory set for photoconductive mode with a buffer gain of unity, providing a slope of 10 mV/dB and an intercept of 100 pA. By substituting resistor and capacitor values, all of the application circuits presented in this data sheet can be evaluated. The system is completed by the final buffer amplifier, which is an uncommitted op amp with a rail-to-rail output capability, a 10 MHz bandwidth, and good load driving capabilities. The buffer can be used to implement multipole low-pass filters for noise reduction. The buffer also facilitates modification of the output scaling and the intercept point using simple resistor divider networks and the 2 V output provided by the VREF pin. SHIELDS AND GUARDS Reducing errors from external sources in a current sensing circuit requires a different approach then the voltage sensing input of the typical high impedance op-amp circuit. Leakage can be a significant source of error for highly sensitive log amps, especially at the low end of their range. For example, a 1 GΩ leakage path to ground from the INPT input with a V SUM set to the default 0.5 V generates a 0.5 nA offset. The ADL5303 evaluation board makes extensive use of guards to reduce the effects of leakage at low input levels. It is important to carefully handle and clean the ADL5303 evaluation board to prevent contaminants from handling or improper washing of the PCB causing leakage currents. Circuit board designs for the ADL5303 must connect the EPAD to the VSUM pins to provide a continuous guard around the sensitive INPT pin to reduce the influence of surface contaminants. A common mistake for those unfamiliar with low level current sensing is to attach a high impedance scope probe or meter to measure the input for debug. This can cause significant error, as the typical 1M ~ 100 MΩ impedance of these probes sources/ sinks current from the input, depending on their bias. In instrumentation applications where measurements <1 nA are required, the use of triaxial cables and connectors is common to reduce leakage through the insulating dielectric by carrying a continuous guard from current source to sensing circuit on the intermediate conductor. This type of guarding circuit is differ- ent from a conventional electrostatic shield used in voltage sensing applications. An electrostatic shield relies on low impedance and the ability to flow current freely to minimize voltage induced on the shield that can capacitively couple into a high impedance input. A guard is actively driven to the same voltage as the current carrying center conductor eliminating leakage through the dielectric between the center conductor and the guard. The guard does not flow current other than the leakage from the guard to the outer shield. The guard is usually connected to a single end of the cable only because any signifi- cant current flow through the guard can couple inductively to the center conductor. Using the ADL5303 evaluation board, the guard can be driven either from the guard of an external current source or from the internal VSUM bias of the ADL5303. The ADL5303 evaluation board can bias the shield of a coaxial cable connected to the INPT input to the nominal V SUM voltage with Switch S1 but this requires careful consideration of the environment on the other side of the cable. For example if the ADL5303 evaluation board is configured for VSUM = 0.5 V connecting the other end of the INPT coaxial cable to an instrument with a ground referenced shield pulls VSUM to ground and collapses the input stage of the ADL5303. Floating the current source end of the shield provides a low leakage guard but a separate return path for the signal current must then be provided. If cable dielectric leakage is not a concern, the INPT can be connected directly to a coaxial cable with the shield providing a signal ground.
Figure 31. Schematic
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COMPLIANT TOJEDEC STANDARDS MO-220-WEED-6. Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Rev. 0 | Page 22 of 24 NOTES
Rev. 0 | Page 23 of 24 NOTES
Rev. 0 | Page 24 of 24 NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10661-0-1/13(0)