ADL5206

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1.0 GHz DGA with 30 dB Range and

Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

100 Ω differential input resistance 10 Ω differential output resistance Noise figure: 5.1 dB at 300 MHz, 5 V supply, and maximum gain OIP3 at maximum gain 39.4 dBm at 300 MHz at 5 V supply 38.1 dBm at 700 MHz at 5 V supply Gain step accuracy: ±0.2 dB −3 dB bandwidth at 32 dB: 1.0 GHz typical at 5 V supply Multiple control interface options Parallel 5-bit control interface with latch 3- and 4-wire SPI with fast attack Gain step-up and step-down interface Wide input dynamic range Power-down control Single 3.3 V or 5 V supply operation 112 mA quiescent current at 5 V supply 20-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

High intermediate frequency (IF) sampling receivers High output power IF amplification DOCSIS FDx upstream amplifier Instrumentation FUNCTIONAL BLOCK DIAGRAM 10Ω100Ω 32dB TO 2dB VPOS VIN– MODEx VIN+ SPI/PARALLEL INTERFACE VOUT+ VOUT– ADL5206 LOGIC PWUPEPAD 24682-001 Figure 1. GENERAL DESCRIPTION The ADL5206 is a wide bandwidth, variable gain amplifier (VGA) with digital control (also known as a digital gain amplifier (DGA)) that provides precise gain control, high output third-order intercept (OIP3), and low noise figure over the entire gain range. The excellent OIP3 performance of 39.4 dBm (at 300MHz,

5 V supply, and maximum gain) makes the ADL5206 an excellent

gain control device for a variety of receiver applications. For wide input dynamic range applications, the ADL5206 provides a broad 2 dB to 32 dB gain range with a 1 dB step size. The gain is adjustable through multiple gain control and interface options: parallel, serial peripheral interface (SPI), or gain step-up and step-down controls. The ADL5206 can be powered up independently by applying the appropriate logic level to the PWUP pin. The quiescent current of the ADL5206 is typically 112 mA with a 5 V supply. When disabled, the ADL5206 consumes only 8 mA and offers excellent input to output isolation. The gain setting is preserved when the device is disabled. Fabricated on the Analog Devices, Inc., high speed, silicon germanium (SiGe), bipolar complementary metal-oxide semiconductor (BiCMOS) process, the ADL5206 provides precise gain adjustment capabilities with good distortion performance. The ADL5206 amplifier comes in a compact, thermally enhanced, 4 mm × 4 mm, 20-lead LFCSP and operates over the temperature range of −40°C to +85°C. Note that throughout this data sheet, multifunction pins, such as CS /GS1/D3, are referred to by the entire pin name or by a single function of the pin.

Rev. 0 | Page 2 of 25 TABLE OF CONTENTS

REVISION HISTORY

9/2020—Revision 0: Initial Version

Rev. 0 | Page 3 of 25 SPECIFICATIONS TA = 25°C, load impedance (ZLOAD) = 100 Ω, maximum gain (gain code = 00000), frequency = 300 MHz, and 2 V p-p differential output, unless otherwise noted. Table 1.

3.3 V Supply 1 5 V Supply 1

Parameter2 Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth At 20 dB 1.7 1.6 GHz At 25 dB 1.4 1.3 GHz At 32 dB 1.2 1.0 GHz Slew Rate 4.3 4.3 V/ns INPUT STAGE VIN+ and VIN− pins Maximum Input Swing3 Gain code = 11111 4 6.2 V p-p Differential Input Resistance 100 100 Ω Input Common-Mode Voltage 1.65 2.5 V Common-Mode Rejection Ratio (CMRR) 56 56 dB GAIN Voltage Gain Range 30 30 dB Maximum Gain Gain code = 00000 32 32 dB Minimum Gain Gain code = 11110 to 11111 2 2 dB Gain Step Size 1 1 dB Gain Step Accuracy ±0.2 ±0.2 dB Gain Flatness From 30 MHz to 700 MHz 0.2 0.2 dB p-p Gain Temperature Sensitivity Gain code = 00000 and at

700 MHz

3 4 mdB/°C Fast Attack Step Response Delay For input voltage (VIN) = 0.1 V, FA changing from 0 to 1 with 16 dB step 5 5 ns COMMON-MODE INPUTS VCM Pin Input Resistance 2.6 2.6 kΩ OUTPUT STAGE VOUT+ and VOUT− pins Output Voltage Swing At 1 dB compression point (P1dB), gain code = 00000 4.1 6.25 V p-p Output Common-Mode Offset ((VOUT +) + (VOUT−))/2 − VCM/2 −10 +10 −10 +10 mV Differential Output Resistance 10 10 Ω Short-Circuit Current 20 25 mA NOISE AND HARMONIC PERFORMANCE

10 MHz

Noise Figure 6.2 6.3 dB Second Harmonic Distortion (HD2) V OUT = 2 V p-p −85 −89.2 dBc Third Harmonic Distortion (HD3) V OUT = 2 V p-p −76.5 −85.6 dBc Output Second-Order Intercept (OIP2) V OUT = 2 V p-p composite 84.3 87.1 dBm Third Intermodulation Distortion (IMD3) VOUT = 2 V p-p composite −78.9 −85.8 dBc Output Third-Order Intercept (OIP3) V OUT = 2 V p-p composite 39.4 42.9 dBm

Rev. 0 | Page 4 of 25 Parameter2 Test Conditions/Comments Min Typ Max Min Typ Max Unit

100 MHz

Noise Figure 5.8 5.9 dB HD2 V OUT = 2 V p-p −75.8 −78.4 dBc HD3 V OUT = 2 V p-p −72.2 −81 dBc OIP2 V OUT = 2 V p-p composite 74.7 76.8 dBm IMD3 V OUT = 2 V p-p composite −77 −84.8 dBc OIP3 V OUT = 2 V p-p composite 38.5 42.4 dBm

300 MHz

Noise Figure 4.6 5.1 dB HD2 V OUT = 2 V p-p −67.8 −77.6 dBc HD3 V OUT = 2 V p-p −56.2 −67.9 dBc OIP2 V OUT = 2 V p-p composite 70.5 79.5 dBm IMD3 V OUT = 2 V p-p composite −75 −78.8 dBc OIP3 V OUT = 2 V p-p composite 37.5 39.4 dBm

500 MHz

Noise Figure 4.5 5 dB HD2 V OUT = 2 V p-p −58.7 −65.6 dBc HD3 V OUT = 2 V p-p −52.6 −66.2 dBc OIP2 V OUT = 2 V p-p composite 58.3 65.7 dBm IMD3 V OUT = 2 V p-p composite −68.3 −76.6 dBc OIP3 V OUT = 2 V p-p composite 34 38.3 dBm OP1dB 14.3 18 dBm Noise Figure 6.7 7 dB HD2 V OUT = 2 V p-p −62.7 −69 dBc HD3 V OUT = 2 V p-p −55.4 −77.7 dBc OIP2 V OUT = 2 V p-p composite 64.2 67.2 dBm IMD3 V OUT = 2 V p-p composite −61.2 −76.3 dBc OIP3 V OUT = 2 V p-p composite 30.6 38.1 dBm

1000 MHz

Noise Figure 7.5 7.9 dB HD2 V OUT = 2 V p-p −60.3 −62.5 dBc HD3 V OUT = 2 V p-p −49 −61 dBc OIP2 V OUT = 2 V p-p composite 61.6 63.3 dBm IMD3 V OUT = 2 V p-p composite −56.5 −69.1 dBc OIP3 V OUT = 2 V p-p composite 28.2 34.5 dBm

1200 MHz

Noise Figure 6.6 7 dB HD2 V OUT = 2 V p-p −53.4 −57.2 dBc HD3 V OUT = 2 V p-p −44 −52 dBc OIP2 V OUT = 2 V p-p composite 53.6 57.5 dBm IMD3 V OUT = 2 V p-p composite −54.4 −66.9 dBc OIP3 V OUT = 2 V p-p composite 27.2 33.4 dBm

Rev. 0 | Page 5 of 25

3.3 V Supply1 5 V Supply1

Parameter2 Test Conditions/Comments Min Typ Max Min Typ Max Unit DIGITAL INTERFACE Input Voltage MODE1, MODE0, PWUP , LATCH, and SDIO pins Logic High (VIH) 2 VPOS 2 3.3 V Logic Low (VIL) 0 1.0 0 1.0 V Input Leakage Current Digital VIN = 0 V to 3.3 V ±3 ±3 µA Output Voltage SDIO pin Logic High (VOH) Output high current (IOH) = −2 mA 2.4 2.4 2.4 Logic Low (VOL) Output low current (IOL) = 2 mA 0.5 0.5 POWER INTERFACE Quiescent Current 87 112 mA Power-Down Current PWUP pin = low 8 8 mA 1 The 3.3 V supply is low power mode, and the 5 V supply is high performance mode. 2 When referring to a single function of a multifunction pin in the specifications table, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. 3 The maximum input swing of 6.2 V p-p is for the lowest gain setting of 2 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly to maintain the same maximum output swing. The maximum output swing is based on P1dB.

5 V Supply Voltage 4 V-GHz

3.3 V Supply Voltage 3 V-GHz

1 When referring to a single function of a multifunction pin in the parameters,

only the portion of the pin name that is relevant to the specification is listed. Function Descriptions section.

2 The differential input voltage limit is significantly lower than the maximum

output swing. The maximum output swing is based on P1dB. PCB thermal design is required. JA), die to board (θJB), and die to lead (θJC). Table 4. Thermal Resistance thermal impedance from the die to the leads of the ADL5206. θJB, and more layers tend to reduce thermal impedance slightly.

15 VOUT+

11 LATCH/SPI_HP_LP

91 SOPV

02 MIRETNICND

61 SOPV

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE

CONNECTED TO A LOW IMPEDANCE GROUND PLANE. Figure 5. Pin Configuration (Top View) Table 5. Pin Function Descriptions select low power parallel, SPI, or up and down interface mode. 3 MODE0 The LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or UPDN mode. 4 SDIO/SDO Serial Data Input and Output in 3-Wire SPI Mode (SDIO). Serial data output in 4-wire SPI mode (SDO). represents D4 when in the parallel gain control interface. mode, this pin represents D3 when in the parallel gain control interface. 4-wire SPI mode, this pin is the serial data input (SDI). logic low selects 3-wire SPI and logic high selects 4-wire SPI (3SPI_4SPI). 10, 12 DNC Do Not Connect. Do not connect to these pins.

high selects high performance mode, and logic low selects low power mode (SPI_HP_LP). pins. A logic high on this pin powers up, and a logic low on this pin powers down. 14 VOUT− Negative Analog Output. 15 VOUT+ Positive Analog Output. 16, 19 VPOS Positive Power Supply, 5 V. 17 VIN+ Positive Analog Input. 18 VIN− Negative Analog Input. a pull-up that is 50 kΩ to 3.3 V. plane is the ground (0 V) reference for all voltages in Table 1. Table 6. Pin Function Overview for Various Modes

Figure 18. HD2 vs. Frequency over VPOS = 5 V for Four Voltage Gains, Figure 19. HD2 vs. Frequency over VPOS = 5 V for Three Temperatures at Figure 20. HD2 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for Figure 21. HD2 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for Three Figure 22. HD3 vs. Frequency over VPOS = 5 V for Four Voltage Gains at

2 V p-p, High Performance Mode

Figure 23. HD3 vs. Frequency over VPOS = 5 V for Three Temperatures at

Figure 24. HD3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for Figure 25. HD3 vs. Frequency over VPOS = 3.3 V and VPOS = 5 V for Figure 26. Noise Figure vs. Frequency over Voltage Gain Ranges,

5 V High Performance Mode

Figure 27. Noise Figure vs. Frequency over Voltage Gain Ranges,

5 V Low Power Mode

Figure 28. Noise Figure vs. Frequency over Voltage Gain Ranges,

3.3 V Low Power Mode

Figure 29. SDD11 vs. Frequency at Gain = 2 dB, 5 V High Performance Mode

Figure 36. SDD22 vs. Frequency at Gain = 32 dB, 5 V High Performance Mode Figure 37. Gain vs. Frequency over Voltage Gains, Figure 38. Gain vs. Frequency over Voltage Gains, Figure 39. Gain vs. Frequency over Voltage Gains, Figure 40. Enable Time Domain Response, 5 V High Performance Mode Figure 41. Disable Time Domain Response, 5 V High Performance Mode

Figure 42. Enable Time Domain Response, 3.3 V Low Power Mode Figure 43. Disable Time Domain Response, 3.3 V Low Power Mode Figure 44. Fast Attack Enable Time Domain Response, Figure 45. Fast Attack Disable Time Domain Response, Figure 46. Fast Attack Enable Time Domain Response, Figure 47. Fast Attack Disable Time Domain Response,

Figure 48. CMRR vs. Frequency at Voltage Gain = 2 dB and Voltage Gain = Figure 49. Output Common-Mode Voltage vs. Settling Time,

5 V High Performance Mode, Maximum Gain Transition

Figure 50. Group Delay vs. Frequency at Maximum Gain, Figure 51. Group Delay vs. Frequency at Maximum Gain, Figure 52. Group Delay vs. Frequency at Maximum Gain, Figure 53. Output Common-Mode Voltage vs. Settling Time,

3.3 V Low Power Mode, Maximum Gain Transition

Rev. 0 | Page 19 of 25 THEORY OF OPERATION BASIC STRUCTURE The ADL5206 is a differential, digitally controlled VGA, which is also known as a DGA. The DGA consists of a 100 Ω differential input, digitally controlled passive attenuator, followed by a digitally controlled gain amplifier. On-chip logic circuitry maps the gain codes such that all gain changes, from the maximum gain to minimum gain, are accomplished by only using the digitally controlled resistors in the feedback of the amplifier. This technique does not require a digital step attenuator (DSA) on the input of the amplifier, thus providing SFDR increases as gain reduces. This topology also allows all 30 dB of gain reduction in the feedback with a total noise figure degradation of 7 dB only over the total 30 dB gain range at 700 MHz. The differential output impedance of the amplifier is 10 Ω. CONTROL AND LOGIC CIRCUITRY The ADL5206 features three different gain control interfaces: serial, parallel, or up and down control, which is determined by the combination of the MODE1 and MODE0 pins. For details on controlling the gain in each of these modes, see the Digital Interface Overview section. Typically, the gain step size is 1 dB. Larger step sizes can be programmed, as described in the Digital Interface Overview section. The amplifier has a maximum gain of 32 dB (Gain Code 00000) to a minimum gain of 2 dB (Gain Code 11110 to Gain Code 11111). COMMON-MODE VOLTAGE The ADL5206 is flexible in terms of input and output coupling. The ADL5206 can be ac-coupled or dc-coupled at the inputs and/or outputs within the specified output common-mode voltage reference range of 1.2 V to 1.8 V for the 3.3 V supply and 1.4 V to 2.7 V for the 5 V supply, depending on the supply voltage. If no external output common-mode voltage is applied, the input and output common-mode voltages are set internally to half of the supply voltage. The output common-mode voltages of the ADL5206 are controlled by the voltages on the VCM pin. The VCM pin is connected internally through 5 kΩ resistors to the VPOS pin as well as to the exposed pad. As a result, the common-mode output voltage is preset internally to half of the supply voltage at VPOS. Alternatively, the VCM pin can be connected to the common-mode voltage reference output from an ADC, and thus the common-mode levels between the amplifier and the ADC can be matched without requiring any external components.

Table 7. Register Summary Table 8. Bit Descriptions for CTL

7 RESERVED Reserved 0x0 R

Rev. 0 | Page 21 of 25 APPLICATIONS INFORMATION BASIC CONNECTIONS Figure 57 shows the basic connections for operating the ADL5206. Apply a 3.3 V or 5 V voltage to the VPOS pins. Decouple the supply pins with at least one low inductance, surface-mount, 0.1 µF ceramic capacitor and place the capacitor as close to the device as possible. The differential outputs (VOUT+ and VOUT−) have a dc common-mode voltage that is approximately half of the supply. Therefore, decouple these outputs using 0.1 µF capacitors to balance the load. The balanced differential inputs have the same dc common-mode voltage as the outputs. Note that the inputs are decoupled using 0.1 µF capacitors as well. The digital pins (that is the mode control pins, the associated SPI and parallel gain control pins, the power mode, and the PWUP pin) operate at a 3.3 V voltage. T o enable the ADL5206, pull the PWUP pin high (2.0 V ≤ PWUP ≤ 3.3 V). A logic low on the PWUP pin sets the ADL5206 to sleep mode, reducing the current consumption to approximately 7 mA. The VCOM pin is the output common-mode voltage, and the VCOM pin must be decoupled with a 0.1 µF capacitor for filtering noise. VOUT– 15VOUT+ PWUP PWUP DNC 11LATCH/SPI_HP_LP VCOM MODE0 MODE1 SDIO/SDO SCLK/D4 VCOM MODE0 MODE1 SDIO/SDO SCLK/D4 0 1 DNC INTERIM DNC INTERIM NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. EXPOSED PAD GROUND. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE. ADL5206 EXPOSED PAD BALANCED LOAD 5PO_VCC 0.1µF 0.1µF 0.1µF BALANCED SOURCE AC 0.1µF0.1µF 0.1µF 0.1µF VPOS VIN– VIN+ VPOSDNC CS/GS1/D3 FA/GS0/D2 UPDN_CLK/D1/SDI UPDN_DAT/D0/3SPI_4SPI CS/GS1/D3 FA/GS0/D2 UPDN_CLK/D1/SDI UPDN_DAT/D0/3SPI_4SPI ½RS RL ½RS 17003-052 LATCH/SPI_HP_LP F igure 57. Basic Connections

0.050 MAX

0.035 NOM

0.203 REF

Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the prop erty of their respective owners.