ADL5205 (Rev. A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 31
Technical content
Dual, 35 dB Range, 1 dB Step Size DGA Data Sheet ADL5205 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Dual, independent, digitally controlled gain amplifier (DGA) −9 dB to +26 dB gain range 1 dB step size, ±0.2 dB accuracy at 200 MHz 100 Ω differential input resistance 10 Ω differential output resistance 1.2 dB change in noise figure for first 12 dB of gain reduction Output third-order intercept (OIP3): 48.5 dBm at 200 MHz, 5 V, high performance mode −3 dB bandwidth: 1700 MHz typical in high performance mode Multiple control interface options Parallel 6-bit control interface with latch Serial peripheral interface (SPI) with fast attack Gain step up/down interface Wide input dynamic range Low power mode Power-down control Single 3.3 V or 5 V supply operation 40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
Differential analog-to-digital converter (ADC) drivers High intermediate frequency (IF) sampling receivers High output power IF amplification Instrumentation FUNCTIONAL BLOCK DIAGRAM 14dB TO 26dB GND VPOS VINA+ VINA– 0dB TO 23dB 10Ω 10Ω 100Ω 100Ω SIDE A SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN SIDE B SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN VOUTA– VOUTA+ ADL5205 PM MODE0 MODE1 VINB+ VINB– VOUTB– VOUTB+ 0dB TO 23dB LOGIC LOGIC CONTROL CIRCUITRY PWUPA PWUPB 14dB TO 26dB 13488-001 Figure 1. GENERAL DESCRIPTION The ADL5205 is a digitally controlled, wide bandwidth, variable gain dual amplifier (DGA) that provides precise gain control, high output third-order intercept (OIP3) and a near constant noise figure for the first 12 dB of attenuation. The excellent OIP3 performance of 48.5 dBm (at 200 MHz, 5 V , high performance mode, and maximum gain) makes the ADL5205 an excellent gain control device for a variety of receiver applications. For wide input dynamic range applications, the ADL5205 provides a broad 35 dB gain range with a 1 dB step size. The gain is adjustable through multiple gain control and interface options: parallel, SPI, or gain step up/down control. The two channels of the ADL5205 can be powered up independently by applying the appropriate logic level to the PWUPA and PWUPB pins. The quiescent current of the ADL5205 is typically 175 mA for high performance mode and 135 mA for low power mode. When disabled, the ADL5205 consumes only 14 mA and offers excellent input to output isolation. The gain setting is preserved when the device is disabled. Fabricated on the Analog Devices, Inc., high speed, silicon germanium (SiGe) complementary BiCMOS process, the ADL5205 provides precise gain adjustment capabilities with good distortion performance. The ADL5205 amplifier comes in a compact, thermally enhanced, 6 mm × 6 mm, 40-lead LFCSP package and operates over the temperature range of −40°C to +85°C. Note that throughout this data sheet, multifunction pins, such as CSA /A3, are referred to by the entire pin name or by a single function of the pin, for example, CSA, when only that function is relevant.
Rev. A | Page 2 of 31 TABLE OF CONTENTS
REVISION HISTORY
5/2019—Rev. 0 to Rev. A 4/2016—Revision 0: Initial Version
Rev. A | Page 3 of 31 SPECIFICATIONS Supply voltage (VPOS) = 3.3 V or 5 V , TA = 25°C, ZLOAD = 200 Ω, maximum gain (Gain code = 000000), frequency = 200 MHz, PM = 0 V , 2 V p-p differential output, unless otherwise noted. Table 1.
3.3 V Supply 5 V Supply
Parameter1 Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth High performance mode 1700 1700 MHz Low power mode 1500 1500 MHz Slew Rate 5 5 V/ns INPUT STAGE VINx+ and VINx− pins Maximum Input Swing2 Gain code = 111111 8 8 V p-p Differential Input Resistance Differential 100 100 Ω Input Common-Mode Voltage 1.65 2.5 V Common-Mode Rejection Ratio (CMRR) Gain code = 000000 48 48 dB GAIN Voltage Gain Range 35 35 dB Maximum Gain Gain code = 000000 26 26 dB Minimum Gain Gain code = 100011 to 111111 −9 −9 dB Gain Step Size 1 1 dB Gain Step Accuracy ±0.2 ±0.2 dB Gain Flatness From 30 MHz to 200 MHz 0.2 0.2 dB p-p Gain Temperature Sensitivity Gain code = 000000 2.4 4 mdB/°C Fast Attack Step Response Delay For VIN = 0.1 V, FA_A or FA_B changing from 0 to 1 with 16 dB step 15 80 ns COMMON-MODE INPUTS VCMA and VCMB Input Resistance 2.6 2.6 kΩ OUTPUT STAGE VOUTx+ and VOUTx− pins Output Voltage Swing At P1dB, gain code = 000000 4.5 5.4 V p-p Output Common-Mode Offset ((VOUTx+) + (VOUTx−))/2 − VCMx/2 −10 +10 −10 +10 mV Differential Output Resistance Differential 10 10 Ω Short-Circuit Current High performance mode 22 22 mA Low power mode 17 17 mA NOISE/HARMONIC PERFORMANCE Gain code = 000000, high performance mode
10 MHz
Noise Figure 6.3 6.5 dB Second Harmonic VOUT = 2 V p-p −103 −103 dBc Third Harmonic VOUT = 2 V p-p −101 −100 dBc Output Third-Order Intercept (OIP3) V OUT = 2 V p-p composite 48.5 47 dBm Output 1 dB Compression Point (P1dB) 13.7 17.5 dBm
100 MHz
Noise Figure 6.3 6.6 dB Second Harmonic VOUT = 2 V p-p −86 −90 dBc Third Harmonic VOUT = 2 V p-p −87 −94 dBc OIP3 V OUT = 2 V p-p composite 45 46 dBm Output P1dB 13.2 17.4 dBm
Rev. A | Page 4 of 31 Parameter1 Test Conditions/Comments Min Typ Max Min Typ Max Unit
200 MHz
Noise Figure Increase for First 12 dB of Gain Reduction Gain code = 000000 to 001100 1.2 1.2 dB Noise Figure 6.6 6.6 dB Second Harmonic VOUT = 2 V p-p −75.5 −75 dBc Third Harmonic VOUT = 2 V p-p −77 −87.5 dBc OIP3 V OUT = 2 V p-p composite 44 48.5 dBm Output P1dB 13 17 dBm
300 MHz
Noise Figure 6.6 6.9 dB Second Harmonic VOUT = 2 V p-p −63 −64 dBc Third Harmonic VOUT = 2 V p-p −68 −78 dBc OIP3 V OUT = 2 V p-p composite 43 43.5 dBm Output P1dB 12.8 17.3 dBm
500 MHz
Noise Figure 7.8 8.2 dB Second Harmonic VOUT = 2 V p-p −58 −61.5 dBc Third Harmonic VOUT = 2 V p-p −57.5 −67.5 dBc OIP3 V OUT = 2 V p-p composite 37 36 dBm Output P1dB 13.1 17.7 dBm DIGITAL INTERFACE Input Pins A0 to A5, B0 to B5, MODE1, MODE0, PWUPA, PWUPB, PM, LATCHA, LATCHB, SDIO VIH Logic high 2 VPOS 2 3.3 V VIL Logic low 0 1.0 0 1.0 V Input Leakage Current Digital input voltage = 0 V to 3.3 V ±3 ±3 μA Output Pins SDIO Logic High (VOH) I OH = −2 mA 2.4 2.4 V Logic Low (VOL) I OL =2 mA 0.5 0.5 V POWER-INTERFACE Quiescent Current High Performance Mode PM = low 175 175 mA Low Power Mode PM = high 135 135 mA Power-Down Current PWUPA and PWUPB = low 14 14 mA 1 When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. 2 The maximum input swing of 8 V p-p is for the lowest gain setting of −9 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly to maintain the same maximum output swing.
3 V-GHz
1 The differential input voltage limit is significantly lower than the maximum
signal presented on the pins goes directly on an input ESD protection circuit. Therefore, the input signal swing must be limited to a low value. (θJA), die to board (θJB), and die to lead (θJC), respectively. Table 4. Thermal Resistance
- DNC = DO NOT CONNECT. DO NOT CONNECT
- THE EXPOSED PAD MUST BE CONNECTED TO
Figure 5. Pin Configuration Table 5. Pin Function Descriptions 1 CSA/A3 Channel A Select in Serial Mode (CSA). When serial mode is enabled, a logic low selects Channel A. Bit 3 for Channel A in Parallel Gain Control Interface Mode (A3). 2 A4 Bit 4 for Channel A in Parallel Gain Control Interface Mode (A4). 3 A5 Bit 5 for Channel A in Parallel Gain Control Interface Mode (A5). DNC Do Not Connect. Do not connect to these pins. 8 SDIO/B5 Serial Data Input and Output in SPI Mode (SDIO). Bit 5 for Channel B in Parallel Gain Control Interface Mode (B5). 9 SCLK/B4 Serial Clock Input in SPI Mode (SCLK). Bit 4 for Channel B in Parallel Gain Control Interface (B4). 10 GS1/CSB/B3 MSB for the Gain Step Size Control in Up/Down Mode (GS1). Channel B Select in Serial Mode (CSB). When serial mode is enabled, a logic low selects Channel B. Bit 3 for Channel B in Parallel Gain Control Mode (B3). 11 GS0/FA_B/B2 LSB for the Gain Step Size Control in Up/Down Mode (GS0). according to the FA bit values in the control register. Bit 2 for Channel B in Parallel Gain Control Interface (B2). 12 UPDN_CLK_B/B1 Clock Interface for the Channel B Up/Down Function (UPDN_CLK_B). Bit 1 for Channel B in Parallel Gain Control Interface Mode (B1). 13 UPDN_DAT_B/B0 Data Pin for the Channel B Up/Down Function (UPDN_DAT_B). Bit 0 for Channel B in Parallel Gain Control Interface Mode (B0).
Rev. A | Page 8 of 31 Pin No. Mnemonic Description 14 LATCHB Latch B. A logic low on this pin allows the gain to change on Channel B in parallel gain control interface mode. A logic high on this pin prevents gain changes. 15 VINB− Channel B Negative Analog Input. 16 VINB+ Channel B Positive Analog Input. 17 PWUPB Channel B Power-Up. A logic high on this pin powers up Channel B, and a logic low on this pin disables it. 18 VCMB Channel B Common-Mode Output. 21 VOUTB− Channel B Negative Analog Output. 22 VOUTB+ Channel B Positive Analog Output. 24, 27 VPOS Positive Power Supply. 29 VOUTA+ Channel A Negative Analog Output. 30 VOUTA− Channel A Positive Output. 33 VCMA Channel A Common-Mode Output. 34 PWUPA Channel A Power-Up. A logic high on this pin powers up Channel A, and a logic low on this pin disables it. 35 VINA+ Channel A Positive Analog Input. 36 VINA− Channel A Negative Analog Input. 37 LATCHA Latch A. A logic low on this pin allows the gain to change on Channel A in the parallel gain control interface mode. A logic high on this pin prevents gain changes. 38 UPDN_DAT_A/A0 Data Pin for the Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A in Parallel Gain Control Interface Mode (A0). 39 UPDN_CLK_A/A1 Clock Interface for the Channel A Up/Down Function (UPD_CLK_A). Bit 1 for Channel A in Parallel Gain Control Interface Mode (A1). 40 FA_A/A2 Fast Attack for Channel A (FA_A). In serial mode, a logic high on this pin attenuates Channel A according to an FA SPI word. Bit 2 for Channel A in Parallel Gain Control Interface (A2). EP GND Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane. This is the ground (0 V) reference for all the voltages in Table 1.
impedance of the amplifier is 10 Ω. degradation in linearity performance. mode voltages are set internally to half of the supply voltage. requiring any external components. Figure 50. Basic Structure
Figure 58. Write Read Setup Value, 0x0100 Figure 59. Read Back Value, 0x0154 with an antialiasing filter and an ADC is shown in Figure 60. Nyquist band, resulting in a reduction of signal-to-noise ratio. Figure 60. ADC Interface (One of Two Channels Shown) Table 10. Component Values for a 500 MHz Acquisition System resumes the 1 dB degradation for each dB of gain reduction.
200 MHz 5V HP
Figure 61. Noise Figure vs. Gain
when the device is running on a 5 V supply. in the Signal Inputs and Outputs section. evaluate the performance of the ADL5205. Figure 62. ADL5205-EVALZ Evaluation Board
3.3 V voltage regulator and select it using the S3 and S2 jumpers,
Table 11. Power Supply Selection Jumpers into single-ended form to the VOUTA+ and VOUTB+ connectors. the switch is set to logic high. Table 12. Switch Block Functions (logic low or Logic 0), the device is in high performance mode. difference between the mode switch settings of 10 and 11. Table 13. Mode Switch Settings
00 Parallel
01 Serial (SPI)
10 Up/down
11 Up/down
when each channel is enabled. of the ADL5205, and the gain stops changing. is changed by Bits[B5:B0] in the same manner.
position when using the parallel interface to control the device. Table 14. Parallel Interface Pinout (P3)
1 PWUPB
2 AGND
3 LATCHB
4 AGND
6 AGND
8 AGND
10 AGND
12 AGND
14 AGND
16 AGND
17 VDD
18 AGND
19 Power mode (PM)
20 AGND
21 MODE0
22 AGND
23 MODE1
24 AGND
26 AGND
28 AGND
30 AGND
32 AGND
34 AGND
36 AGND
37 LATCHA
38 AGND
39 PWUPA
40 AGND
serial/SPI mode are brought out to Serial Interface Connector P2. The pinout for Serial Interface Connector P2 is listed in Table 15.
- CSA and CSB are the active low serial port enable pins for Channel A and Channel B, respectively.
- SDIO is the serial data input and output line. SDIO is a bidirectional pin.
- SCLK is the serial clock pin. For detailed operations and timing diagrams of the serial port interface, see the Serial Peripheral Interface (SPI) section. These signals operate at 3.3 V logic levels. The CSA and CSB lines can be tied together to program both channels at the same time.
Table 15. Serial Interface Connector (P2) Pinout
1 PWUPA
2 Not applicable
3 FA_A
4 Not applicable
5 CSA
6 Not applicable
8 Not applicable
9 SDIO
10 Not applicable
11 SCLK
12 Not applicable
13 CSB
14 Not applicable
15 FA_B
16 Not applicable
17 PWUPB
18 Not applicable
19 AGND
20 Not applicable
Figure 65. Main Screen of the ADL5205 Control Software Table 16. Features on the Control Software Main Screen
1 VOUTB+
0 DNI
1 SD_N
Figure 66. ADL5205-EVALZ Evaluation Board Schematic, Page 1
Figure 67. ADL5205-EVALZ Evaluation Board Schematic, Page 2
Table 17. Bill of Materials Qty. Description Reference Designator Manufacturer Part No.
1 PCB Not applicable Analog Devices 08_039771B
5 Connectors, PCB test points, red, CNLOOPTP 5V, VCC, VDD, 3P3V, VREG Components
1 IC, high accuracy, 200 mA, low dropout linear regulator,
2 Capacitors, ceramic, monolithic chip, C0G, 100 pF,
1 Capacitors, ceramic, 0805 X7R, 1 µF, C0805H53, 10%, 50 V C21 Murata GRM21BR71H105KA12L
1 Capacitor, ceramic, X5R, 10 µF, C0805H60, 10%, 10V C23 KEMET C0805C106K8PACTU
4 Connectors, PCB test point black, CNLOOPTP GND1to GND3, VNEG Components
1 Connectors, PCB vertical type receptacle SMD,
1 Connectors, PCB BERG header ST male 20P,
1 Connectors, PCB header 40P male, TSW-120-08-G-D,
21 Resistors, chip SMD jumper, 0 Ω, R0402, 5% R1, R2, R16 to R21, R24,
8 Resistors, high frequency chip, 0402, 50 Ω, R0402, 1% R39 to R42, R101 to R104 Vishay FC0402E50R0FST1
10 Resistors, film SMD 1206, 200 Ω, R1206, 2% R13, R22, R23, R28, R52 to
2 Resistors, precision thick film chip, R0402, 100 kΩ,
1 Resistors, film SMD 0805, 330 kΩ, R0805, 5% R51 Panasonic ERJ-6GEYJ334V
19 Resistors, thick film chip, 1 kΩ, R0603, 1% R58 to R65, R67 to R77 Vishay CRCW06031K00FKEAHP
3 Connectors, PCB BERG header ST male 3P,
2 Switches, DIP SPST, side actuated, 5435802-9,
1 Switch, SPST DIP, three position AU
2 XFMR RF 1:1, TC1-1-13M+, AT224-1 T2, T4 Mini-Circuits TC1-1-13M+
2 XFMR RF 2:1, TC2-1T+, AT224-1 T1, T3 Mini-Circuits TC2-1T+
1 IC, 35 dB step size programmable DGA, ADL5205,
1 IC, 32 kb serial EEPROM, 24LC32A-I/MS, MSOP8 U2 Microchip Technology 24LC32A-I/MS
2 Connectors, PCB test point yellow, CNLOOPTP VCMA, VCMB Components
8 Connectors, PCB coaxial SMA end launch,
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-2.
4.50 REF
Figure 70. 40-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.